From 68998469b805f407ad3b60cb101c1d032bbcc28d Mon Sep 17 00:00:00 2001 From: Baber Abbasi <92168766+baberabb@users.noreply.github.com> Date: Tue, 11 Jun 2024 22:13:19 +0500 Subject: [PATCH] USPTO (#71) * Add data processing and conversion scripts * Add process_uspto.sh script for processing USPTO data * Add TypeScript compilation step * replace bs4 with lxml. Also using polars for the main computation. * Add row limit for testing. * add multiprocessing to speed things up * split runtime script into setup and run * remove streaming. slower but will need alot more memory * fix typehint: Sequence defines `__len__` * add args to bash script * add readme * use pandoc --- courtlistener/get_data.sh | 2 +- licensed_pile/write.py | 4 +- uspto/README.md | 47 +++++++ uspto/examples/uspto_examples.jsonl | 110 +++++++++++++++ uspto/process_uspto.sh | 8 ++ uspto/requirements.txt | 3 + uspto/setup.sh | 9 ++ uspto/uspto-to-dolma.py | 206 ++++++++++++++++++++++++++++ uspto/utils.py | 42 ++++++ 9 files changed, 428 insertions(+), 3 deletions(-) create mode 100644 uspto/README.md create mode 100644 uspto/examples/uspto_examples.jsonl create mode 100644 uspto/process_uspto.sh create mode 100644 uspto/requirements.txt create mode 100644 uspto/setup.sh create mode 100644 uspto/uspto-to-dolma.py create mode 100644 uspto/utils.py diff --git a/courtlistener/get_data.sh b/courtlistener/get_data.sh index 6fc26fb..df9d4d1 100644 --- a/courtlistener/get_data.sh +++ b/courtlistener/get_data.sh @@ -11,7 +11,7 @@ download_dir="./data/courtlistener/raw" mkdir -p "$download_dir" # Only download the data from most recent CL dump -# The newest dump contains the previous dumps data +# The newest dump contains the previous dumps data # Differences from the previous data should not be included dates=( "2024-05-06" diff --git a/licensed_pile/write.py b/licensed_pile/write.py index 681964a..f5d9c34 100644 --- a/licensed_pile/write.py +++ b/licensed_pile/write.py @@ -7,7 +7,7 @@ import os from contextlib import ExitStack from queue import Queue -from typing import Dict, Sequence +from typing import Dict, Iterator import smart_open import tqdm @@ -23,7 +23,7 @@ def shard_name(filename: str, shard: str, padding: int = 5): # TODO: Add overwrite protection def to_dolma( - examples: Sequence[Dict], + examples: Iterator[Dict], path: str, filename: str, shard_size: int = 1, diff --git a/uspto/README.md b/uspto/README.md new file mode 100644 index 0000000..158fef7 --- /dev/null +++ b/uspto/README.md @@ -0,0 +1,47 @@ +# USPTP + +USPTO dataset extracted from [Google Patents Public Dataset](https://cloud.google.com/blog/topics/public-datasets/google-patents-public-datasets-connecting-public-paid-and-private-patent-data) and uploaded to HF. + +## Data Download and Processing + +To clone the unprocessed dataset from HuggingFace run `bash setup.sh`. The default location is `/uspto/data` + +`pandoc` is required to run the script. The command to install it is provided in the script (commented out). Alternatively you can install it with`sudo apt-get install pandoc` but that installs an older version. + + +The main script can be run with `bash run process_uspto.sh --output-dir --max-concurrency --limit `. + +Note: The script will take a long time to run. The `--max-concurrency` flag can be used to speed up the process. The `--limit` flag can be used to limit the number of rows processed. +It takes ~30 mins to process 1 file with 256 threads. The bulk of the processing is done by pandoc. + +To save the processed data to parquet add the `--to-parquet` flag. + +
+Under the hood of process_uspto.sh + +### setup.sh has 3 main steps: + +#### Usage +1. Ensure you are in the correct directory structure: + 1. The script expects to be run from the parent directory of the `uspto` directory. + +#### Running the Script: +- Make sure the script has execute permissions. If not, run: + ```sh + chmod +x process_uspto.sh + ``` + +#### It has the following steps: +1. The main bulk of the processing in the python script are the pandoc conversions. A progress bar is displayed for each column/file. + +
+ + +## Data Stats + + +## Example +Some output examples are in the examples dir. + +## License +Creative Commons - Attribution - https://creativecommons.org/licenses/by/4.0/ diff --git a/uspto/examples/uspto_examples.jsonl b/uspto/examples/uspto_examples.jsonl new file mode 100644 index 0000000..19bf904 --- /dev/null +++ b/uspto/examples/uspto_examples.jsonl @@ -0,0 +1,110 @@ +{ + "id": "US-1327908-A", + "text": "Interconnections of an integrated electronic circuit\n\nABSTRACT\n\nAn integrated electronic circuit includes superimposed insulating layers and metal elements distributed within said insulating layers. Each insulating layer comprises a first level within which the metal elements lie substantially in the plane of said first level, and a second level traversed by the metal elements in a direction substantially perpendicular to the plane of said second level, so as to come into contact with at least one metal element of the first level. The levels also comprise insulation zones for insulating the metal elements from each other. For at least one insulating layer, at least one of the levels of said at least one insulating layer comprises at least two insulation zones respectively realized of a first material and a second material which are different from each other.\n \n CROSS-REFERENCE TO RELATED APPLICATION\n This application claims the benefit under 35 U.S.C. \u00a7 119 of French Patent Application No. 07 00197, filed Jan. 11, 2007, which is incorporated herein by reference in its entirety.\n BACKGROUND\n 1. Technical Field\n This invention relates to the domain of integrated electronic circuits.\n 2. Description of the Related Art\n Integrated circuits are generally structured into an active part (the \u201cfront end\u201d) in which are the devices such as transistors, and a superimposed passive part (the \u201cback end\u201d). The back end is dedicated to transferring signals from one transistor type of device to another.\n The back end has a structure in multiple insulating layers, within which lie metal elements, typically metal interconnections, but also capacitors, coils, antennas, etc.\n Lines are metal interconnections which, for each layer, lie within a first level of the layer in the plane of said level, and define a pattern. Vias are metal interconnections which, for each layer, traverse a second level in a direction perpendicular to the plane of said second level, and which connect lines from one layer to another.\n Each layer thus comprises a first level, called the interconnection level, inside which lie the lines, and a second level called the contact level, inside which lie the vias.\n Insulation zones, generally realized of a dielectric material, separate the metal interconnections from each other. The material of the insulation zones is chosen so as to limit parasitic capacitance between the metal interconnections.\n The capacitance between interconnections increases with the permittivity between these interconnections, and decreases with the distance between them. The race towards miniaturization and performance optimization has therefore led to choosing a dielectric with a relatively weak permittivity \u201ck\u201d, typically less than 4.2, or even choosing to separate the interconnections by air gaps. ULK (\u201cUltra Low k\u201d) dielectrics thus present a permittivity of less than 4.2. ELK (\u201cExtreme Low k\u201d) dielectrics present a permittivity coefficient of less than 2.5.\n However, integrated circuits realized with ULK dielectrics or with air gaps are likely to be damaged relatively easily, particularly during fabrication. For example, a layer realized of a porous ULK dielectric can be broken off relatively easily during a CMP (Chemical Mechanical Polishing) step.\n Mechanical failures also include a lack of resistance to the stresses created by welding connections and injecting resin around the circuit.\n The document by Y. N. Su et al. entitled \u201cIntegration of Cu and Extra Low-k Dielectric (k=2.5\u02dc2.2) for 65/45/32 nm Generations\u201d, Electron Devices Meeting 2005, IEDM technical digest, IEEE International, 5-7 Dec. 2005, describes a hybrid structure, in which the dielectric material used for the interconnection levels has a lower permittivity than that of the dielectric material used for the contact levels. Such structures have a satisfactory mechanical resistance, but the capacitance between interconnections may be relatively high.\n BRIEF SUMMARY\n One embodiment improves the performance of integrated electronic circuits.\n One embodiment provides an integrated electronic circuit comprising superimposed insulating layers and metal elements distributed throughout said insulating layers. Each insulating layer comprises a first level, within which the metal elements lie substantially within the plane of said first level, and a second level, traversed by the metal elements in a direction substantially perpendicular to the plane of said second level, so as to come into contact with at least one metal element of the first level. The first level and the second level both comprise insulation zones which isolate the metal elements from each other. For at least one insulating layer, at least one of the levels of said at least one insulating layer comprises at least two insulation zones respectively realized of a first material and a second material which are not the same.\n \u201cMaterials which are not the same\u201d is understood to mean materials which differ in the chemical composition, structurally, or in some other way. For example, the two materials have the same chemical composition, but one of the materials is relatively dense and the other relatively porous, for example a material of a porosity exceeding 30% by volume. The first and second materials can typically have different mechanical properties, for example a Young's modulus or a Poisson ratio at least 10% higher or lower from one material to the other, different permittivities, and/or different thermal conductivity coefficients. At least one insulation zone can even integrate an air gap, meaning that one of the dielectric materials, for example the second, is air.\n Alternatively, the two materials may be solids, for example two dielectric materials. The dielectric materials usable for insulation zones include silicon dioxide (SiO2), materials based on fluorinated or carbon-doped silicon dioxide, whether dense or porous, carbon-doped polymer materials, etc.\n In this manner there are at least two groups of insulation zones for the same level, each group associated with a given material. The use of at least two different materials within the same level offers more flexibility in finding a compromise between the diverse performances required for the circuit.\n For example, the first material may present a permittivity of about 5%, preferably 10%, or even 15% or above, greater than that of the second material, and/or a Young's modulus of about 5%, preferably 10%, or even 15% or above, greater than that of the second material. This juxtaposition of insulation zones of different materials allows reconciling electrical performance with good mechanical resistance.\n In addition, the juxtaposition of different zones within the same level may allow better heat removal, via zones presenting a higher thermal conductivity coefficient. In particular, the materials presenting a relatively low permittivity, for example porous materials, generally present a relatively low thermal conductivity coefficient, such that the juxtaposition of zones having different permittivity coefficients allows satisfactory heat removal.\n There can be two distinct materials, or there can be more.\n It is advantageous if said at least one level comprising at least two insulation zones realized of different materials is a second level. In other words, in the case where the metal elements comprise metal interconnections, it is within the contact level that the insulation zones realized of distinct materials are found. As the metal elements of the second level occupy less area than the metal elements of the first level, the space available for the different insulation zones is relatively high in the second level. Thus there is a certain flexibility in choosing the locations for the different insulation zones.\n Alternatively, one may choose to place the different insulation zones within the first level, or within both levels.\n It is advantageous if at least one insulation zone realized of the first material, in the second level, is located adjacent to a corresponding metal element of the first level. In this manner, one can adjust the various capacitance values induced by each first level metal element corresponding to such an insulation zone. Because of the relatively high surface area occupied by the first level elements, it is primarily the capacitances induced by the first level metal elements which are likely to reduce the circuit's performance.\n Of course, such a distribution of the insulation zones in no way limits the scope of the invention.\n It is advantageous if at least one second level insulation zone adjacent to the corresponding metal element is self-aligned with said metal element. This avoids an overlay between an insulation zone and the corresponding metal element, and a resulting imprecision in the parasitic capacitance values. This also avoids the need for a supplemental mask for the deposition of self-aligned insulation zones during the fabrication of the circuit.\n Of course, the insulation zones do not have to be self-aligned.\n It is advantageous if the first material presents a permittivity and a Young's modulus greater than those of the second material. Thus one may obtain relatively low capacitances between metal elements of the same first level, due to the relatively low values of the fringe capacitances, as explained below with reference to FIG. 2. As an example, the permittivity for the first material can be at least 1%, preferably at least 10%, or even at least 15% above that of the second material, and the Young's modulus of the first material can be at least 10%, preferably at least 15%, or even at least 20%, above that of the second material.\n Alternatively, the first material can present a permittivity coefficient and/or a Young's modulus below those of the second material. For example, two first level metal elements belonging to successive insulating layers, and sandwiching the corresponding insulation zone, can thus be separated by a zone presenting a relatively low permittivity, such that the capacitance between these elements is also relatively low.\n One embodiment provides an electronic board comprising an electronic chip comprising a package and an integrated electronic circuit according to the first aspect of the invention.\n One embodiment provides a method for fabricating an integrated electronic circuit comprising superimposed insulating layers and metal elements distributed through said insulating layers, the method comprising, for at least one insulating layer of said superimposed layers:\n a/ depositing a first dielectric material onto a substrate so as to form a layer,\n b/ forming a trench in the layer,\n c/ filling the trench with a second dielectric material different from the first dielectric material, such that the layer now comprises insulation zones of the first dielectric material and insulation zones of the second dielectric material, and\n d/ executing a smoothing step so as to substantially eliminate the second dielectric material from the zones on the surface of the layer which correspond to the insulation zones of the first dielectric material,\n e/ forming another trench in the layer, and\n f/ filling in said trench with a metal, so as to form a metal element.\n This process allows obtaining an electronic circuit according to one embodiment.\n Steps b/, c/ and d/ can be performed before or after steps e/ and f/.\n The process can comprise, particularly in the context of a dual damascene method, additional steps consisting of forming a third trench and filling in said third trench with metal so as to form another metal element. This last step, consisting of filling the third trench, and step f/ can be realized simultaneously. In addition, the third trench formation step can occur before or after step f/.\n In general, the invention is not limited by the order in which the steps are executed.\n The locations of two of the trenches can be combined and the same mask may be used for the steps in which said trenches are formed. These two trenches are thus self-aligned.\n The process can additionally comprise a step of removing at least part of the first dielectric material, through contact with an agent that removes the first material. An electronic circuit comprising air gaps is thus obtained.\n Alternatively, this removal step does not take place, such that the circuit retains zones of the first dielectric material and zones of the second dielectric material.\n Other features and advantages of the invention will become apparent in the embodiments described below with respect to the figures.\n \n \n \n BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS\n FIG. 1 shows an example of a portion of an electronic circuit with a known prior art hybrid structure.\n FIGS. 2 and 3 respectively show two examples of a portion of an electronic circuit according to two embodiments of the invention.\n FIGS. 4A to 4G show an example of a circuit fabrication process according to one embodiment of the invention.\n FIGS. 5A to 5D show an example of a circuit fabrication process according to one embodiment of the invention.\n FIG. 6 shows an example of an electronic board according to one embodiment of the invention.\n \n \n \n DETAILED DESCRIPTION\n For clarity, the dimensions of the various elements represented in these figures are not proportional to their actual dimensions. FIGS. 1 to 5D are cross-section views of wafer segments which are substantially flat, viewed in a plane perpendicular to the surface of the wafer. The substrate is found in the lower part of each figure, and N indicates a direction perpendicular to the surface of the substrate, pointing towards the top of the figures. In what follows, the terms \u201con\u201d, \u201cunder\u201d, \u201cupper\u201d, \u201clower\u201d, \u201cabove\u201d and \u201cbelow\u201d are used with reference to this orientation. \u201cOn\u201d is understood to mean \u201cdirectly on\u201d as well as \u201cindirectly on\u201d, meaning that a layer deposited \u201con\u201d another may be completely separated from said other layer by at least one other layer.\n In the figures, the same numbers are used to indicate similar or identical objects.\n FIG. 1 shows a portion of a known prior art integrated electronic circuit. In addition to a front end not represented, the circuit comprises superimposed insulating layers, some of which are represented with the reference labels 1 and 1\u2032. The number of insulating layers can, for example, be seven or eight.\n The insulating layers 1, 1\u2032 are separated from each other by a thin barrier of dielectric 7, 7\u2032.\n Each layer 1, 1\u2032 comprises a level of interconnections 5, 5\u2032 and a level of contacts 6, 6\u2032, within which lie metal elements 2, 3, 2\u2032. The metal elements comprise lines 2, 2\u2032 lying within the interconnection levels 5, 5\u2032 and in the plane of the corresponding interconnection level 5, 5\u2032, and vias 3, 3\u2032 which traverse the contact levels 6, 6\u2032 in a direction substantially perpendicular to the plane of the contact level in order to connect two lines 2, 2\u2032 in two separate insulating layers.\n The lines and vias are isolated from each other by insulation zones 4, 4\u2032, 8, 8\u2032, generally of dielectric. In the case of a hybrid structure, the zones 4, 4\u2032 of the interconnection levels 5, 5\u2032 are realized of a material different from the one used for the zones 8, 8\u2032 of the contact levels 6, 6\u2032. The dielectric material used for the zones 4, 4\u2032 presents a lower permittivity than that of the material used for the zones 8, 8\u2032.\n FIG. 2 shows an example of a portion of electronic circuit according to one embodiment of the invention. The back end of this circuit comprises superimposed insulating layers 1, 1\u2032, 1\u2033, 1\u2032\u2033, separated from each other by thin barriers of dielectric 7, 7\u2032, 7\u2033. The layers 1, 1\u2032, 1\u2033, 1\u2032\u2033 can, for example, have a thickness on the order of a hundred nanometers, for example from 50 nm to 1 \u03bcm. The barriers 7, 7\u2032, 7\u2033 can for example be made of SiCN, SiC, or SiN.\n Each insulating layer 1,1\u2032, 1\u2033, 1\u2032\u2033 comprises an interconnection level 5, 5\u2032, 5\u2033, 5\u2032\u2033 within which lie lines 2 a, 2 b, 2\u2032, 2\u2033, 2\u2032\u2033, and a contact level 6, 6\u2032, 6\u2033, traversed by vias 3, 3\u2032, 3\u2032\u2033.\n The lines and vias are realized of copper or tungsten for example. It is well known to a person skilled in the art that the lines and vias may comprise a metal barrier (not represented), of TaN for example, to limit the distribution of the metallic species in the rest of the level.\n The lines 2 a, 2 b, 2\u2032, 2\u2033, 2\u2032\u2033 and the vias 3, 3\u2032, 3\u2032\u2033 are isolated from each other by insulation zones 24, 24\u2032, 25, 25\u2032, 25\u2033, 26, 27, 28, 28\u2032.\n In this example, the insulation zones 25, 25\u2032 25\u2033 of the interconnection levels 5, 5\u2032, 5\u2033, 5\u2032\u2033 are all of the same type, unlike those 24, 28, 24\u2032, 28\u2032 of the contact levels 6, 6\u2032 of most of the insulating layers.\n In this example, two dielectric materials presenting different permittivities have been used for the insulation zones 24, 28, 24\u2032, 28\u2032 of the contact levels 6, 6\u2032. There can of course be more than two.\n The zones 28, 28\u2032 are realized of a first dielectric material presenting a permittivity greater than that of the material of the zones 24, 24\u2032, called the second material. For example, the first material is a ULK dielectric material, for example dense SiOC presenting a permittivity of about 3, while the second material is an ELK dielectric material, for example porous SiOC presenting a permittivity which is less than or equal to 2.5.\n One can of course do otherwise: for example, the second material can be a carbon-doped polymer such as the polymer known under the commercial name SiLK, distributed by Dow Chemical.\n In this example, the zones 25, 25\u2032, 25\u2033 are realized of the same material as the zones 24, 24\u2032, but they can of course be of different materials.\n The zones 28, 28\u2032 are adjacent to the corresponding lines 2 a, 2 b, 2\u2032, 2 a\u2032, 2 b\u2032. In this example, the zones 28, 28\u2032 are self-aligned with the corresponding lines 2 a, 2 b, 2\u2032, 2 a\u2032, 2 b\u2032. \n The total capacitance Cline between two lines 2 a\u2032, 2 b\u2032 of a same interconnection level 5\u2032 can be modeled as the contribution of the terms:\n \n \n \n C\n line\n =C\n area\n +C\n 1\n fringe\n +C\n 2\n fringe \n \n \n where Carea indicates the capacitance created along the field lines which pass through the insulation zone 25\u2032,\n and C1 fringe,C2 fringe indicate the fringe capacitance created along the field lines which respectively pass through the insulation zones 24\u2032 and 24.\n Cfringe also comprises the contribution of the field lines which pass through the barrier portion 7\u2032 between the lines 2 a\u2032, 2 b\u2032. \n The capacitances C1 fringe,C2 fringe are proportional to the permittivity of the zones traversed by the respective field lines and are therefore relatively low, such that the total line capacitance Cline between the two lines 2 a\u2032, 2 b\u2032 is also relatively low.\n In addition, the interlayer capacitance Clayer between two lines 2 b, 2 b\u2032 of two successive insulating layers 1, 1\u2032 can be written as:\n C layer =C\u2032 area+2*C fringe \n where C\u2032area indicates the capacitance created along the field lines which traverse the insulation zone 28,\n and C\u2032fringe indicates the fringe capacitance created along the field lines traversing one of the insulation zones 24. Due to the nature of the zones 24, the fringe capacitance C\u2032fringe has a relatively low value.\n The coexistence within a same level of insulation zones of different materials thus improves the performance of the electronic circuit.\n The reference 20 indicates a part of the electronic circuit corresponding to a connection pad for connecting with the circuit exterior. As the dimensions of the pad are relatively large compared to the typical dimensions of the circuit core, there is less need for high electrical performance in the part 20 corresponding to the pad. However, this part may be required to withstand the strains of pad soldering and resin injection. It is possible to realize the insulation zones of the contact level of the part 20 of the same dielectric, presenting a relatively high Young's modulus, while using two different dielectrics for the insulation zones of the contact level in the parts of the circuit which require increased performance. Thus, the parts of the circuit can be adapted to the anticipated demands.\n The upper layer 1\u2032\u2033 is such that the insulation zones of its levels are all realized of the same dielectric material presenting a relatively high Young's modulus, for example the first material. The upper layer is the last layer in the superimposed insulating layers.\n The presence of certain parts (part 20, layer 1\u2032\u2033) in which the contact levels have insulation zones of a material with relatively high permittivity allows reinforcing the mechanical resistance of the entire circuit.\n FIG. 3 shows an example of a portion of an electronic circuit according to one embodiment of the invention. In this example, certain insulation zones 30, 30\u2032 of certain layers 1, 1\u2032 comprise air or vacuum gaps. Other insulation zones 26, 27, 28 are realized of a dielectric presenting a relatively high permittivity, for example of dense SiOC.\n FIGS. 4A to 4G show an example of a circuit fabrication process according to one embodiment of the invention. In what follows, the basic steps of the process which are known to a person skilled in the art are not reiterated in detail.\n In a substrate 12 of silicon for example, possibly comprising a dielectric barrier as well as other layers not represented, a first dielectric material, here porous SiOC, is deposited so as to form a layer 10. The deposition can occur via a PECVD (plasma enhanced chemical vapor deposition) process for example, or any other process.\n A hard mask layer HM 11 is also deposited, as represented in FIG. 4A. It is advantageous if the layer 11 is of metal, for example TiN, or dielectric, for example SiN or SiCN.\n As illustrated in FIG. 4B, a trench 13 is formed in the layer 10, for example by performing masking, photolithography, and dry etching operations.\n In the description there is only a small number of trenches. A person skilled in the art is well aware that in actuality, the number of trenches etched simultaneously in a wafer can be relatively high, for example on the order of a million per wafer, and that only a small number of trenches is described here for easier comprehension of the process.\n As illustrated in FIG. 4C, this trench 13 is filled with a second dielectric material presenting a permittivity greater than that of the first dielectric material, for example dense SiOC, thus defining insulation zones 14, 41 realized of different materials. The second dielectric material can be deposited via a PECVD process for example, or any other process.\n A smoothing step substantially eliminates the second dielectric material from the zones 42 of the surface which correspond to the insulation zones 41, such that the hard mask layer 11 is level with the surface as represented in FIG. 4D. The smoothing step can be achieved using a CMP (Chemical Mechanical Polishing) process or any other known process.\n Another trench 17 is formed, for example by performing masking, photolithography, and dry etching operations. In this example, the position of the trench 17 and the position of the trench 13 are partially combined, meaning that the position of the trench 17 partially covers the position of the trench 13, as illustrated in FIG. 4E.\n A third trench 17 b is also formed.\n In this example, the trench 17 allows the realization of a via, while the trench 17 b allows the realization of a line.\n The trench 17 is dug beyond the dielectric barrier 12, while the trench 17 b does not descend down to the dielectric barrier 12. The zone 14 is therefore reduced.\n The location of the trench 17 b and the location of the trench 13 are combined, as illustrated in FIG. 4F. In particular, the mask of the hard mask layer 11 can be reused as the mask for the trench 17 b. This avoids the repetition of certain operations such as lithography mask operations.\n Lastly, as illustrated in FIG. 4G, the trenches 17, 17 b are filled in with metal, for example copper, to form a line 18 b and a via 18, and a smoothing step is performed in order to level the surface. The hard mask layer 11 can be eliminated at this time.\n An insulating layer with two levels 45, 46 is thus obtained, with one of the two levels comprising insulation zones 14, 41 realized of different materials. As the same hard mask 11 was used, the zone 14 and the line 18 b are self-aligned.\n This process, based on a dual damascene method, is only given as an indication. Note that as the hard mask layer 11 is used twice, for forming the placement for the insulation zone 14 as well as the placement for the line 18 b, no additional lithography masking operations are done than in the known processes of the prior art.\n Alternatively, a process based on a simple damascene method can be used. In this case, one can for example form a first trench, fill it with a metal, execute a CMP polishing step, then form a second trench adjacent to the first trench by adding a supplemental lithography step followed by dry etching, fill it with a dielectric material, and execute a CMP polishing step. The two trenches are sufficiently deep to traverse the layer in which they are etched. Thus a contact level is obtained with a via at the position of the first trench, and an insulation zone at the position of the second trench. All that remains is to create an interconnection level in order to obtain a complete layer, which can be realized by depositing a dielectric material on the contact level, forming a trench in the deposited material, then filling this trench with metal in order to form a line.\n The FIGS. 5A to 5D show an example of a circuit fabrication method according to one embodiment of the invention. This method allows obtaining superimposed insulating layers in which some of the insulation zones comprise air gaps.\n One begins with a first insulating layer 1\u2032 similar to the layer obtained by the process illustrated in FIGS. 4A to 4G, and mounted on a dielectric barrier 7\u2033. The contact level for this layer therefore comprises insulation zones 28 of a first dielectric material, and insulation zones 24 of a second dielectric material.\n A self-aligned barrier labeled 51 in FIG. 5A is deposited, for example a barrier of copper silicide or CoWP, using a known process.\n As illustrated in FIG. 5B, a second insulating layer 1 is formed, using for example a process similar to the one illustrated by FIGS. 4A to 4G. A self-aligned barrier 51 is also deposited.\n One can continue to form insulating layers (not represented). Lastly, an upper insulating layer 1\u2032\u2033 is formed, with the insulation zones 26, 27 of this layer being realized of a dielectric material presenting a relatively high permittivity coefficient, for example the first dielectric material.\n Openings 52 reaching the dielectric material of the zones 24, 25 are realized in the upper layer 1\u2032\u2033, as illustrated in FIG. 5C, for example by performing masking, photolithography, and wet etching operations.\n Lastly, the second dielectric material is removed, for example by placing it in contact with an agent which removes the second dielectric material. The wafer supporting these superimposed layers 1, 1\u2032, 1\u2032\u2033 is immersed in said agent to remove the second dielectric material. For example, the first dielectric material is of dense SiOC and the second dielectric material is of SiO2. Said removal agent is for example hydrofluoric acid (HF), able to dissolve SiO2 but resisted by dense SiOC. The removal agent can dissolve the material in zones 24, 25 by passing through the openings 52, forming air gaps, as illustrated in FIG. 5D.\n In another example, the second dielectric material is removed by raising the temperature. For example, the first dielectric material is dense SiOC and the second dielectric material is a thermally degradable polymer such as the SiLK polymer, for example. The temperature is increased at least to a temperature at which SiLK degrades. The openings 52 allow the evacuation of the degraded polymer material.\n Of course, circuits with air gaps can be formed using different processes. For example, the material used for the insulation zones 26, 27 of the upper layer 1\u2032\u2033 can be of a porous material resistant to the removal agent. There is then no need to form the openings 52 in the FIGS. 5C and 5D.\n FIG. 6 shows an example of an electronic board according to one embodiment of the invention. The board 60 comprises pads 63, a coil 62, connections not represented, and electronic chips 61 integrating a circuit according to one embodiment.\n The various embodiments described above can be combined to provide further embodiments. All of the U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the Application Data Sheet, are incorporated herein by reference, in their entirety. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide yet further embodiments.\n These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.\n \n \n \n 1. An integrated electronic circuit, comprising:\nsuperimposed insulating layers and metal elements distributed within said insulating layers, with each insulating layer including: a first level, within which first level metal elements of the metal elements lie substantially in a plane of said first level; and a second level, traversed by second level metal elements of the metal elements in a direction substantially perpendicular to a plane of said second level, so as to come into contact with at least one of the first level metal elements of the insulating layer, wherein the first level and the second level also include insulation zones for insulating the metal elements from each other, wherein, for at least one insulating layer, the second level of said at least one insulating layer comprises a first insulation zone of a first material positioned immediately adjacent to a corresponding first level metal element, and a second insulation zone of a second material that is different from the first material, the first material having a permittivity coefficient greater than a permittivity coefficient of the second material. \n \n \n 2. An integrated electronic circuit according to claim 1, wherein:\nthe first insulation zone is self-aligned with said corresponding first level metal element. \n \n \n 3. An integrated electronic circuit according to claim 1, wherein:\nthe first material has a Young's modulus greater than a Young's modulus of the second material. \n \n \n 4. An integrated electronic circuit according to claim 1, wherein the second material is air.\n \n \n 5. A device, comprising\na circuit board; and an electronic chip that includes a package and an integrated electronic circuit including: superimposed insulating layers and metal elements distributed within said insulating layers, with each insulating layer including: a first level, within which first level metal elements of the metal elements lie substantially in a plane of said first level; and a second level, traversed by second level metal elements of the metal elements in a direction substantially perpendicular to a plane of said second level, so as to come into contact with at least one of the first level metal elements of the insulating layer, wherein the first level and the second level also include insulation zones for insulating the metal elements from each other, wherein, for at least one insulating layer, the second level of said at least one insulating layer comprises a first insulation zone of a first material positioned immediately adjacent to a corresponding first level metal element, and a second insulation zone of a second material that is different from the first material, the first material having a permittivity coefficient greater than a permittivity coefficient of the second material. \n \n \n 6. The device of claim 5, wherein:\nthe first insulation zone is self-aligned with said corresponding first level metal element. \n \n \n 7. The device of claim 5, wherein:\nthe first material has a Young's modulus greater than a Young's modulus of the second material. \n \n \n 8. The device of claim 5, wherein the second material is air.\n \n \n 9. A method for fabricating an integrated electronic circuit, the method comprising:\nforming superimposed insulating layers and metal elements distributed within said insulating layers, the forming comprising, for at least one insulating layer of said superimposed insulating layers: forming a first dielectric layer by depositing a first dielectric material on a substrate; forming a first trench in the first dielectric layer; filling in the first trench with a second dielectric material which is different from the first dielectric material, such that the first dielectric layer now comprises insulation zones of the first dielectric material and insulation zones of the second dielectric material; executing a smoothing step so as to eliminate substantially the second dielectric material from zones of a surface of the first dielectric layer which correspond to the insulation zones of the first dielectric material; forming a second trench in the layer; and forming a first metal element by filling said second trench with metal, wherein the second dielectric material has a higher permittivity than the first dielectric material. \n \n \n 10. A process for fabricating an integrated electronic circuit according to claim 9, additionally comprising:\nforming a third trench; and forming a second metal element by filling said third trench with metal. \n \n \n 11. A process for fabricating an integrated electronic circuit according to claim 10, wherein at least two of the trenches having positions that are adjacent or at least partially combined.\n \n \n 12. A process for fabricating an integrated electronic circuit according to claim 10, wherein:\ntwo of the trenches having positions that are combined; and the same mask is used for forming said two trenches. \n \n \n 13. A process for fabricating an integrated electronic circuit according to claim 9, further comprising:\nremoving at least part of the first dielectric material. \n \n \n 14. An integrated electronic circuit, comprising:\na first level that includes a first level insulating layer and a first level metal element extending laterally in the first level insulating layer; and a second level that includes: a second level metal element extending transversely to, and contacting, the first level metal element; a first insulation zone of a first material in contact with the first and second level metal elements; and a second insulation zone of a second material that is different from the first material, the second material being on an opposite side of the first insulation zone with respect to the second metal element and having a permittivity coefficient less than a permittivity coefficient of the first material. \n \n \n 15. An integrated electronic circuit according to claim 14, wherein the first insulation zone is self-aligned with said first level metal element.\n \n \n 16. An integrated electronic circuit according to claim 14, wherein the first material has a Young's modulus greater than a Young's modulus of the second material.\n \n \n 17. An integrated electronic circuit according to claim 14, wherein the first material is air. \n \n", + "added": "2008-01-11", + "source": "Google Patents Public Data", + "metadata": { + "license": "Creative Commons - Attribution - https://creativecommons.org/licenses/by/4.0/", + "language": "en", + "publication_date": "2008-07-31" + } +} +{ + "id": "US-201615015189-A", + "text": "Three-dimensionally stacked nonvolatile semiconductor memory\n\nABSTRACT\n\nA three-dimensionally stacked nonvolatile semiconductor memory of an aspect of the present invention including conductive layers stacked on a semiconductor substrate in such a manner as to be insulated from one another, a bit line which is disposed on the stacked conductive layers, a semiconductor column which extends through the stacked conductive layers, word lines for which the stacked conductive layers except for the uppermost and lowermost conductive layers are used and which have a plate-like planar shape, memory cells provided at intersections of the word lines and the semiconductor column, a register circuit which has information to supply a potential suitable for each of the word lines, and a potential control circuit which reads the information retained in the register circuit in accordance with an input address signal of a word line and which supplies a potential suitable for the word line corresponding to the address signal.\n \n CROSS-REFERENCE TO RELATED APPLICATIONS\n This application is a continuation of U.S. Reissue application Ser. No. 14/261,601 filed Apr. 25, 2014, which is continuation of U.S. application Ser. No. 13/164,938 filed Jun. 21, 2011 (now U.S. Pat. No. 8,228,733 issued Jul. 24, 2012), each of the foregoing applications is also an application for the reissue of U.S. Pat. No. 8,228,733, which corresponds to U.S. application Ser. No. 12/553,266 filed Sep. 3, 2009, thus the present application is a continuation reissue application.\n This application is a continuation of and claims the benefit of priority under 35 U.S.C. \u00a7120 from U.S. Ser. No. 12/553,266 filed Sep. 3, 2009, and claims the benefit of priority under 35 U.S.C. \u00a7119 from Japanese Patent Application No. 2008-271279 filed Oct. 21, 2008, the entire contents of each of which are incorporated herein by reference.\n \n \n BACKGROUND OF THE INVENTION\n 1. Field of the Invention\n The present invention relates to a three-dimensionally stacked nonvolatile semiconductor memory.\n 2. Description of the Related Art\n A bit cost scalable (BiCS) technique is known as a technique for achieving higher capacity by a three-dimensional structure to reduce a bit cost (e.g., refer to Jpn. Pat. Appln. KOKAI Publication No. 2007-266143).\n A nonvolatile semiconductor memory to which the BiCS technique is applied (hereinafter referred to as a BiCS memory) does not merely use a three-dimensional structure but also uses a device structure and a process technique that are elaborately designed. This enables bit cost scalability whereby the bit cost decreases in proportion to an increase in the number of stacked layers.\n For example, in the case of a NAND-type flash memory to which the BiCS technique is applied (hereinafter referred to as a BiCS-NAND flash memory), the number of cells constituting a NAND array is longitudinally increased due to the increase in the number of stacked layers, thereby obtaining a memory capacity far above the limit of the memory capacity of a two-dimensionally structured NAND-type flash memory.\n However, the BiCS memories including the BiCS-NAND flash memory have unique device structures. There are therefore many problems to solve in order to put such memories into practical use.\n One of the problems lies in characteristic variations of the memory cells due to variations in shape.\n In the BiCS memory, cell units constituting a memory cell array are formed on the side surfaces of a plurality of columnar active layers extending longitudinally to a semiconductor substrate. For example, after a plurality of conductive layers and insulating layers are alternately stacked, a hole extending through these layers is formed by, for example, a reactive ion etching (RIE) method. In this hole, charge storage layers and the columnar active layers are formed. The formed hole and the components formed in this hole are subject to an aspect ratio. This aspect ratio greatly depends on the number of stacked memory cells in the BiCS memory. That is, in the BiCS memory, due to an increase in the number of stacked layers, there may be a difference, between the upper side (bit line side) and the lower side (semiconductor substrate side) of the hole, in the diameter of the columnar active layers and in the thickness of a gate insulating film or the charge storage layer deposited on the side surface of the hole.\n As a result, even in the case of the memory cells formed on the side surface of the same one active layer, there is a difference in electric properties including threshold voltages between the memory cells on the upper side of the active layer and the memory cells on lower side of the active layer.\n BRIEF SUMMARY OF THE INVENTION\n A three-dimensionally stacked nonvolatile semiconductor memory of an aspect of the present invention comprising: a memory cell array provided in a semiconductor substrate; four or more conductive layers stacked on the semiconductor substrate in the memory cell array in such a manner as to be insulated from one another; a bit line which is disposed on the four or more conductive layers in such a manner as to be insulated from the conductive layers and which has a straight planar shape extending in a first direction; a semiconductor column which extends through the four or more conductive layers and which has an upper end connected to the bit line and a lower end connected to the semiconductor substrate; two or more word lines for which the conductive layers among the four or more conductive layers except for the uppermost and lowermost conductive layers are used and which have a plate-like planar shape; memory cells provided at intersections of the two or more word lines and the semiconductor column, respectively; a register circuit which retains operation setting information for the memory cell array and which has information to supply a potential suitable for each of the word lines; and a potential control circuit which controls the potentials supplied to the word lines and which reads the information retained in the register circuit in accordance with an input address signal of a word line and which supplies a potential suitable for the word line corresponding to the address signal.\n A three-dimensionally stacked nonvolatile semiconductor memory of an aspect of the present invention comprising: a memory cell array provided in a semiconductor substrate; three or more first conductive layers stacked on the semiconductor substrate in the memory cell array in such a manner as to be insulated from one another; three or more second conductive layers which are adjacent to the first conductive layers in a first direction and which are stacked on the semiconductor substrate in the memory cell array in such a manner as to be insulated from one another; a straight bit line which is disposed on the first and second conductive layers in such a manner as to be insulated from the first and second conductive layers and which extends in the first direction; a straight source line which is provided between the bit line and the uppermost second conductive layer and which extends in a second direction intersecting with the first direction; a first semiconductor column which extends through the plurality of first conductive layers and which has an upper end connected to the bit line; a second semiconductor column which extends through the plurality of second conductive layers and which has an upper end connected to the source line and a lower end connected to the first semiconductor column; two or more first straight word lines for which the conductive layers among the three or more first conductive layers except for the uppermost conductive layer are used and which extend in the second direction; two or more second straight word lines for which the conductive layers among the three or more second conductive layers except for the uppermost conductive layer are used and which extend in the second direction; memory cells provided at intersections of the two or more first word lines and the first semiconductor column and at intersections of the two or more second word lines and the second semiconductor column, respectively; a register circuit which retains operation setting information for the memory cell array and which has information to supply a potential suitable for each of the first and second word lines; and a potential control circuit which controls the potentials supplied to the first and second word lines and which reads the information retained in the register circuit in accordance with an input address signal of a word line and which supplies a potential suitable for the word line corresponding to the address signal.\n \n \n \n BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING\n FIG. 1 is a bird's-eye view of a BiCS memory;\n FIG. 2 is an equivalent circuit diagram of a memory cell array;\n FIG. 3 is a diagram for comparison between a BiCS NAND and a two-dimensional NAND;\n FIG. 4 is a bird's-eye view of a NAND cell unit;\n FIG. 5 is a sectional view showing the structure of the NAND cell unit;\n FIG. 6 is a plan view showing the structure of the NAND cell unit;\n FIG. 7 is a block diagram showing the overall configuration of a memory system using the BiCS memory;\n FIG. 8 is a block diagram showing the inside of a BiCS memory chip;\n FIG. 9 is a diagram for explaining reading of data in the BiCS memory;\n FIG. 10 is a diagram for explaining writing of data in the BiCS memory;\n FIG. 11 is a circuit diagram schematically showing the configuration of internal circuits in the BiCS memory;\n FIG. 12 is a flowchart for explaining a first adjustment example;\n FIG. 13 is a graph for explaining the first adjustment example;\n FIG. 14 is a circuit diagram schematically showing the configuration of the internal circuits in the BiCS memory;\n FIG. 15 is a circuit diagram schematically showing the configuration of the internal circuits in the BiCS memory;\n FIG. 16 is a flowchart for explaining a third adjustment example;\n FIG. 17 is a flowchart for explaining the third adjustment example;\n FIG. 18 is a diagram for explaining a modification of an embodiment of the present invention;\n FIG. 19 is a diagram for explaining an application of the embodiment of the present invention;\n FIG. 20 is a diagram for explaining the application of the embodiment of the present invention; and\n FIG. 21 is a diagram for explaining the application of the embodiment of the present invention.\n \n \n \n DETAILED DESCRIPTION OF THE INVENTION\n An embodiment of the present invention will hereinafter be described in detail with reference to the drawings.\n 1. Embodiment\n (1) BiCS Memory\n First, the basic configuration of a BiCS memory is described as an example of a three-dimensionally stacked nonvolatile semiconductor memory according to the embodiment of the present invention.\n FIG. 1 shows a bird's-eye view of the BiCS-NAND flash memory.\n The BiCS-NAND flash memory is composed of, for example, a plurality of blocks each serving as one unit for erasure. Here, two blocks BK, BK are shown.\n For example, one common source diffusion layer 24 formed in a semiconductor substrate is provided for all the blocks. The source diffusion layer 24 is connected to a source line SL\u22c5M1 via a contact plug PSL. Further, three or more conductive layers made of, for example, conductive polysilicon are stacked on the source diffusion layer 24 (in this example, a six-layer structure).\n Except for the uppermost layer, the remaining five conductive layers are plate-shaped in one block BK. The ends of the five conductive layers except for the uppermost layer in the x-direction are stepped to allow contact with each of these layers. The lowermost layer serves as a source line side select gate line (second select gate line) SGS, and the remaining four conductive layers except for the lowermost and uppermost layers serve as word lines WL<0>, WL<1>, WL<2>, WL<3>.\n The uppermost layer is composed of a plurality of linear (straight) conductive interconnections extending in the x-direction (a second direction). For example, six conductive interconnections are arranged in one block BK. For example, six conductive interconnections in the uppermost layer serve as bit line side select gate lines (first select gate lines) SGD<0> to SGD<5>.\n Furthermore, a plurality of active layers (active areas) AA for constituting a NAND cell unit (memory cell unit) are formed to be columnar in the z-direction (a direction perpendicular to the surface of the semiconductor substrate) so that these active layers reach the source diffusion layer 24 through the plurality of conductive layers.\n The upper ends of the plurality of columnar active layers (semiconductor columns) AA are connected to a plurality of bit lines BL<0> to BL extending in the y-direction (a first direction). Moreover, the source line side select gate line SGS is connected, via a contact plug PSGS, to a lead-out line SGS\u22c5M1 extending in the x-direction. The word lines WL<0> to WL<3> are connected, via contact plugs PWL<0> to PWL<3>, lead-out lines WL<0>\u22c5M1 to WL<3>\u22c5M1 extending in the x-direction, respectively.\n Furthermore, the bit line side select gate lines SGD<0> to SGD<5> are connected, via contact plugs PSGD<0> to PSGD<5>, lead-out lines SGD<0>\u22c5M1 to SGD<5>\u22c5M1 extending in the x-direction, respectively.\n The plurality of bit lines BL<0> to BL and the lead-out lines SGS\u22c5M1, WL<0>\u22c5M1, WL<1>\u22c5M1 to WL<3>\u22c5M1, SGD<0>\u22c5M1 to SGD<5>\u22c5M1, SL\u22c5M1 are formed of, for example, a metal.\n FIG. 2 shows an equivalent circuit diagram of a memory cell array. The BiCS-NAND flash memory has a three-dimensional structure. Accordingly, an equivalent circuit is three-dimensionally illustrated.\n A greater number of memory cells constituting a NAND string can make a greater contribution to higher capacity. However, due to the characteristics of the BiCS structure, the characteristics of the memory cells may vary in a manufacturing process along with an increase in the number of memory cells constituting the NAND string.\n FIG. 3 is a diagram showing the BiCS-NAND flash memory and a two-dimensional NAND flash memory in comparison with each other.\n In the two-dimensionally structured NAND type flash memory (referred to as a two-dimensional NAND), one NAND cell unit in one block is connected to one bit line BL. In contrast, in the BiCS-NAND, a plurality of NAND cell units in one block are connected to one bit line BL.\n Thus, in writing or reading operation, one of the plurality of cell units in one block connected to one bit line BL is selected by the bit line side select gate lines SGD<0> to SGD<5>.\n FIG. 4 shows a bird's-eye view of the NAND cell unit.\n One characteristic of the three-dimensionally structured NAND cell unit is that the source line side select gate line SGS, the word lines WL<0> to WL<3> and the bit line side select gate lines SGD<0> to SGD<5> are structured to enclose the side surface of the columnar active layer AA.\n Therefore, even if, for example, the plurality of active layers AA are thinned to form more active layers AA on a semiconductor substrate 23 for higher capacity, a sufficient driving force can be ensured for transistors constituting the NAND cell unit.\n FIG. 5 shows an example of the structure of a NAND cell unit NU of the BiCS-NAND flash memory. A plurality of memory cells MC and select transistors ST constituting one NAND cell unit are stacked in the z-direction via an interlayer insulating film 120.\n The memory cell MC has a MONOS structure. The MONOS structure means a gate structure including an insulator such as nitride as a charge storage layer. That is, as shown in FIG. 5, the memory cell MC includes, for example, an oxide-nitride-oxide (ONO) film 110 having a structure in which a charge storage layer 111 is held between two insulating films (oxide) 112, 113. The insulating film 112 intervenes between the charge storage layer 111 and the active layer AA. The insulating film 112 functions as a tunnel insulating film during writing of data. The insulating film 112 also functions as a block insulating film for preventing the leakage of a charge into the active area AA during retention of data. The insulating film 113 intervenes between the charge storage layer 111 and a gate electrode 144. The insulating film 113 functions as a block insulating film for preventing the leakage of a charge trapped by the charge storage layer 111 into a gate electrode 144. The gate electrode 144 functions as the word line WL<3>. In addition, the memory cell MC may be a memory cell of a MNOS structure which is not provided with the block insulating film 113.\n The select transistor ST has, for example, the same structure as that of the memory cell MC. However, a gate insulating film 115 of the select transistor ST intervening between the active layer AA and the source line side select gate line SGS (a gate electrode 130) may have a structure different from that of the memory cell MC, that is, may have a structure with no charge storage layer (e.g., a single silicon oxide film).\n As described above, the columnar active layers AA are formed in the hole extending through the plurality of stacked conductive layers and insulating layers. Therefore, when the hole is formed by the reactive ion etching (RIE) method, the sectional shape of the hole tends to be tapered if the aspect ratio of the hole is high. As a result, the active layers AA embedded in this hole are also tapered. FIG. 6 shows the planar structures of the lower side (semiconductor substrate side) first word line WL<0> and the upper side (bit line side) fourth word line WL<3>. The planar structures of the word lines WL<0>, WL<3> schematically shown in FIG. 6 correspond to sections (x-y planes) parallel with the surface of the semiconductor substrate.\n As described above, the active layers AA tend to be tapered, so that there may be a dimensional difference in shape between the memory cell provided on the upper side (the word line WL<3>) and the memory cell provided on the lower side (the word line WL<0>). For example, a hole diameter D1_WL<3> at the position where the fourth word line WL<3> is formed tends to be equal to or more than a hole diameter D1_WL<0> at the position where the first word line WL<0> is formed. A pillar diameter D2_WL<3> of the active layer AA at the position where the fourth word line WL<3> is formed also tends to be equal to or more than a pillar diameter D2_WL<0> of the active layer AA at the position where the first word line is formed.\n The insulating film (ONO film) 110 formed along the side surface of the hole is more difficult to deposit on the lower side surface of the hole than on the upper side surface of the hole. Thus, a thickness t_WL<3> of the insulating film at the position where the fourth word line WL<3> is formed may be equal to or more than a thickness t_WL<0> of the insulating film at the position where the first word line WL<0> is formed.\n The plurality of active layers AA are laid out in the x-direction or y-direction at predetermined intervals (pitch Ptc_WL<3>, Ptc_WL<0>). However, if the active layers AA are tapered, an interval (Ptc_WL<3>-D1_WL<3>) between adjacent active layers at the position where the fourth word line WL<3> is formed may also be different from an interval (Ptc_WL<0>-D1_WL<0>) between adjacent active layers at the position where the first word line WL<0> is formed. Specifically, the pillar diameter D2_WL<0> and the thickness t_WL<0> at the position where the first word line WL<0> is formed tend to be smaller than the pillar diameter D2_WL<3> and the thickness t_WL<3> at the position where the fourth word line WL<3> is formed, so that the interval (Ptc_WL<0>-D1_WL<0>) between the active layers at the position where the first word line WL<0> is formed tends to be greater than the interval (Ptc_WL<3>-D1_WL<3>) between the active layers at the position where the fourth word line WL<3> is formed.\n Furthermore, even the memory cells connected to the same word line are not necessarily uniform in the size of the active areas (holes) adjacently formed in the x-direction or y-direction or in the thickness of the ONO film 110.\n (2) Overall Configuration\n FIG. 7 schematically shows a memory chip 1 using the BiCS memory (hereinafter referred to as a BiCS memory chip 1), and a controller 2 and a host 3 which control the BiCS memory chip 1.\n The BiCS memory chip 1 has control pins 11A to 11G and an I/O pin 11H. The input/output of data between the memory chip 1 and the controller 2 and the control the operation of the memory chip 1 are performed by the pins 11A to 11G.\n A device selection signal (/CE) is input to the control pin 11A. A write enable signal (/WE) for bringing the I/O pin 11H into an input state is input to the control pin 11B. A read enable signal (/RE) for outputting data from the I/O pin 11H is input to the control pin 11C. An address latch enable signal (ALE) is input to the control pin 11D. The address latch enable signal is a signal for determining whether a signal provided to the I/O pin 11H is data or an address. A command latch enable signal (CLE) is input to the control pin 11E. The command latch enable signal (CLE) is a signal for writing an operation command provided to the I/O pin 11H into a command decoder. A write protect signal (/WP) for prohibiting writing or erasing operation is input to the control pin 11F. A ready/busy signal (R/B) for allowing the internal operation state of the memory chip 1 to be externally recognized is output to the control pin 11G. The I/O pin 11H is in charge of data input/output. Although one I/O pin is shown in FIG. 7, it should be understood that a plurality of I/O pins 11H may be provided on the chip. In addition, other pins may be provided without limiting to the control pins and the I/O pin.\n The controller 2 is connected to the memory chip 1 via an interface 15.\n The interface 15 includes pins corresponding to the control pins 11A to 11G and the I/O pin 11H of the BiCS memory chip 1, and sets an agreement for enabling communication with the memory chip 1. In addition, the interface 15 may not only have hardware such as control pins but also software for interfacing with the memory chip 1.\n The controller 2 has an MPU 12, a ROM 13 and a RAM 14. The MPU 12 controls the operations of the memory chip 1 and the controller 2. The MPU 12 reads firmware (control program) stored in the ROM 13 or setting information for the memory chip 1 onto RAM 14 in order to execute predetermined processing.\n Moreover, data input/output is performed between the controller 2 and the external device 3 such as the host via interfaces 16, 19.\n The host 3 includes hardware and software for accessing the controller 2. The host 3 includes software 17 such as an application and an operating system. The software 17 instructs a file system 18 to input/output data in accordance with an instruction from a user to input/output data to/from the memory chip 1. The file system 18 is a system for managing files (data) recorded in a recording medium to be managed. The file system 18 records management information into a storage area of the memory chip 1, and uses the management information to manage the files.\n FIG. 8 is a block diagram showing the circuit configuration of the BiCS memory chip 1 using the BiCS memory.\n A memory cell array 30 is composed of the BiCS-NAND flash memories described with FIGS. 1 to 6. Data is stored in a nonvolatile manner in each of the memory cells constituting the memory cell array 30.\n Write data is input to the memory chip 1 from the outside of the chip 1 via the I/O pin 11H. A data input buffer 39A temporarily retains the write data. A data output buffer 39B temporarily retains data read from the memory cell array 30.\n A control circuit 31 recognizes the states (e.g., high(H)/low(L)) of the control pins 11A to 11G, and controls the operations of the internal circuits in the memory chip 1.\n A command decoder 32A decodes an instruction provided from the outside of the chip via the control pins 11A to 11G and the I/O pin 11H.\n An address decoder 32B decodes the addresses of, for example, write, read or erasure target word lines or memory cells provided from the outside of the chip via the control pins 11A to 11G and the I/O pin 11H. The address decoder 32B temporarily retains these addresses.\n A register circuit (e.g., a RAM) 33 retains the setting information for the memory chip 1 read from a storage area in the memory cell array 30 or setting information provided from the outside of the memory chip 1. The register circuit 33 in the present embodiment retains, as one kind of setting information, values corresponding to a write potential suitable for each of the plurality of word lines WL and a word line supply potential such as a nonselection potential.\n A state machine 34 controls the operation of the whole memory chip 1 including reading, writing and erasing in the memory cells, in accordance with outputs from the control circuit 31 and the command decoder 32A.\n The operation of a potential control circuit 35 is controlled by the state machine 34. The potential control circuit 35 generates potentials to be supplied to a selected word line and nonselected word lines, in accordance with an address signal ADR input from the address decoder 32B. The potential control circuit 35 generates a supply potential in accordance with a value which indicates a supply potential suitable for each of the plurality of word lines and which is retained in the register circuit 33.\n A row control circuit 36A selects one of the plurality of word lines WL in accordance with a command signal CMD input from the state machine 34 and the address signal ADR input from the address decoder 32B.\n A word line driver 37 controls the potential of the word line WL, including the transfer of a potential to the word line WL and the discharge of a potential of the word line WL. The potential generated by the potential control circuit 35 is input to the word line driver 37 via the row control circuit 36A. The word line driver 37 then transfers the input potential to the memory cells connected to the word lines WL. In addition, the word line driver 37 controls the potentials of the select gate lines SGD, SGS as well as the potentials of the word lines WL, and also controls the turning on/off of the select transistor.\n A column control circuit 36B receives outputs from the potential control circuit 35 and the state machine 34, and then controls the operation of a data cache/sense amplifier 38.\n The data cache/sense amplifier 38 is controlled by the column control circuit 36B in accordance with the address signal ADR. Moreover, the data cache/sense amplifier 38 temporarily retains data to be written into the memory cells and data read from the memory cells. The data cache/sense amplifier 38 transfers a potential corresponding to the data to the bit line, or senses the potential of the bit line corresponding to the data. The data cache/sense amplifier 38 also temporarily retains data during the verification of a write.\n The data to be written into the memory cells is input to the data cache/sense amplifier 38 from the data input buffer 39A. The data read from the memory cells is output to the data output buffer 39B from the data cache/sense amplifier 38.\n The potentials supplied to the word lines WL, the bit lines BL and the select gate lines SGS, SGD in the memory cell array 30 are controlled by the configuration described above, such that data is written into a selected memory cell or data is read from a selected memory cell. In the writing operation and reading operation in the memory cell array 30, the potentials of the word lines WL and the select gate lines SGD, SGS are controlled, for example, as shown in FIGS. 9 and 10.\n FIG. 9 shows one example of set potentials for the word lines and the select gate lines in the NAND cell unit to which a selected memory cell (hereinafter referred to as a selected cell) belongs during reading of data.\n In FIG. 9, there are shown set potentials for the word lines WL<0> to WL<3> and the select gate lines SGD<5>, SGS for reading of data from the memory cell connected to the fourth word line WL<3> and for reading of data from the memory cell connected to the first word line WL<0>.\n During the reading operation, a potential VDD (e.g., a power supply potential) is applied to the select gate lines SGD<5>, SGS. Thus, the select transistors connected to the bit line side and source line side select gate lines SGD<5>, SGS are turned on.\n A read selection potential VSS (e.g., a ground potential) is applied to the word line WL<3> (or the word line WL<0>) selected as a read target.\n For example, read nonselection potentials Vread_WL<1>S, Vread_WL<1>D, Vread_WL<2>S, Vread_WL<2>D are applied to the word lines which are not selected as read targets such as the word lines WL<1>, WL<2>. This prevents erroneous reading from nonselected cells during the reading operation.\n FIG. 10 shows one example of set potentials for the word lines and the select gate lines in the NAND cell unit to which a selected cell belongs during writing of data.\n In FIG. 10, there are shown set potentials for the word lines WL<0> to WL<3> and the select gate lines SGD<5>, SGS for writing of data into the memory cell connected to the fourth word line WL<3> and for writing of data into the memory cell connected to the first word line WL<0>.\n During the writing operation, for example, the potential VDD is applied to the bit line side select gate line SGD<5>, while the ground potential VSS is applied to the source line side select gate line SGS.\n Write potentials Vpgm_WL<3>, Vpgm_WL<0> are applied to the word lines WL<3>, WL<0> selected as write targets.\n On the other hand, write nonselection potentials Vpass_WL<1>S, Vpass_WL<1>D, Vpass_WL<2>S, Vpass_WL<2>D are applied to the word lines (memory cells) which are not selected as write targets such as the word lines WL<1>, WL<2>. Channels of the nonselected cells are boosted up by the nonwrite potentials Vpass_WL<1>S, Vpass_WL<1>D, Vpass_WL<2>S, Vpass_WL<2>D such that erroneous writing is prevented.\n As described with FIG. 6, variations in the parameters of physical shapes such as the sizes (pillar diameters) of the active layers AA and the thickness of the ONO film 110 cause variations in the potential application time necessary for reading from the respective memory cells even if the same read potential is supplied to the word lines WL<0> to WL<3> during reading of data. Moreover, the variations in the parameters of physical shapes may result in variations in the speed of writing into the respective memory cells even if the same write potential is supplied to the word lines WL<0> to WL<3> during writing of data.\n Furthermore, in the memory cells for each word line, a difference of writing or reading reliability may be made between the selected/nonselected cells. For example, in the tapered active layers AA, there is a difference of pillar diameter between the bit line side (upper side) and the source line side (lower side). Therefore, even the memory cells formed on the same active layer AA have variations in on-resistance and are different in read current. If the charge storage layer 111, the gate insulating film 112 and the block insulating film 113 constituting the ONO film 110 are different in thickness, the write potential is different for each memory cell. The nonselection potentials for preventing erroneous writing/reading also vary.\n In the three-dimensionally stacked nonvolatile semiconductor memory (BiCS memory) according to the embodiment of the present invention, the register circuit 33 retains, as one kind of setting information, information for generating supply potentials which are adjusted in intensity for the respective word lines so that write potentials or nonselection potentials suitable for the plurality of word lines WL<0> to WL<3> may be supplied. Further, the potential control circuit 35 reads the setting information for the supply potentials retained in the register circuit 33 in accordance with an input address signal, and supplies the word lines WL<0> to WL<3> with the potentials suitable therefor.\n This compensates for the characteristic variations of the memory cells in the three-dimensionally stacked nonvolatile semiconductor memory in the present embodiment.\n For example, in the example shown in FIG. 9, for reading data from the memory cell connected to the fourth word line WL<3>, the register circuit 33 retains, as the setting information for the supply potentials suitable for the respective word lines, information for generating read nonselection potentials Vread_WL<0>S, Vread_WL<1>S, Vread_WL<2>S which are adjusted in consideration of the manufacturing variations (size variations) of the memory cells.\n The potential control circuit 35 reads the setting information in the register circuit 33 in accordance with the address signal ADR, generates potentials based on this information, and supplies the word lines WL<0> to WL<2> which are not selected for reading with the potentials suitable therefor.\n Similarly, when data is read from the memory cell connected to the first word line WL<0>, nonselection potentials Vread_WL<1>D, Vread_WL<2>D, Vread_WL<3>D suitable for the nonselected word lines WL<1> to WL<3> are generated in accordance with an address signal and the setting information in the register circuit 33, and the generated potentials are supplied to the word lines WL<1> to WL<3>.\n Moreover, the nonselected word lines WL<0>, WL<3> during reading shown in FIG. 9 are not necessarily provided with the same potential, and may be provided with potentials suitable therefor in accordance with the setting information retained in the register circuit 33.\n For the writing operation, the register circuit 33 retains, as the setting information, information for the word line supply potentials adjusted to be suitable for the word lines WL<0> to WL<3>, as in the case of the reading operation. Then, the potential control circuit 35 generates potentials based on this setting information, and supplies the generated potentials to the word lines WL<0> to WL<3>.\n For example, in the example shown in FIG. 10, the potential control circuit 35 generates, in accordance with the setting information retained in the register circuit 33, the write potential Vpgm_WL<3> suitable when the fourth word line WL<3> is selected and the write potential Vpgm_WL<0> suitable when the first word line WL<0> is selected. The potential control circuit 35 then supplies the potentials to the word lines WL<3>, WL<0>.\n On the other hand, when the fourth word line WL<3> is selected, write nonselection potentials Vpass_WL<0>S, Vpass_WL<1>S, Vpass_WL<2>S generated in accordance with the setting information in the register circuit 33 are provided to the nonselected word lines WL<0>, WL<1>, WL<2> as nonselection potentials suitable therefor. Similarly, when the first word line WL<0> is selected, write non-selection potentials Vpass_WL<1>D, Vpass_WL<2>D, Vpass_WL<3>D are also generated in accordance with the setting information and provided to the nonselected word lines WL<1>, WL<2>, WL<3> as nonselection potentials suitable therefor.\n In addition, the BiCS memory in the embodiment of the present invention supplies the plurality of word lines with the potentials suitable therefor in accordance with the setting information during the writing or reading operation. Thus, during the writing operation, a potential suitable for the writing of data has only to be supplied to the selected word line, so that the write potential Vpgm_WL<0> for the first word line WL<0> may be the same as or different from the write potential Vpgm_WL<3> for the fourth word line WL<3>. Similarly, the read nonselection potentials Vread_WL<2>D, Vread_WL<1>D when the first word line WL<0> is selected may be the same as or different due to interference between adjacent cells from the read nonselection potentials Vread_WL<2>S, Vread_WL<1>S when the fourth word line WL<3> is selected.\n Furthermore, even in the case of the write nonselection potentials for the same word line WL<1>, the write nonselection potential Vpass_WL<1>S when the fourth word line WL<3> is selected may be the same as or different due to interference between adjacent cells from the nonselection potential Vpass_WL<1>D when the first word line WL<0> is selected.\n Thus, according to the three-dimensionally stacked non-volatile semiconductor memory in the embodiment of the present invention, potentials suitable for the plurality of word lines are generated in accordance with the address signal and the setting information, and the generated potentials are supplied to the word lines. Consequently, in the memory cell array in which the memory cells are three-dimensionally arranged, even when the shapes of the active layers AA and the thickness of the ONO film 110 are different due to the structure and manufacturing process of the memory cell array, it is possible to compensate for variations in electric properties of the memory cells due to the three-dimensional structure, such as variations in writing speed or bias application time and variations in writing reliability.\n (3) Generation and Adjustment of Word Line Supply Potentials\n With reference to FIGS. 11 to 17, a circuit configuration and a method are described below wherein the potentials to be supplied to the word lines are adjusted to potentials suitable therefor, and the suitable potentials are supplied to the word lines. Write potentials are mainly described below by way of example.\n (3.1) First Adjustment Example\n A first adjustment example in the embodiment of the present invention is described with FIGS. 11 to 13.\n (a) Circuit Configuration\n FIG. 11 shows the configuration of the circuits for supplying potentials to the word lines. FIG. 11 schematically shows one example of the internal configurations of the register circuit 33, the potential control circuit 35 and the row control circuit 36A out of the internal circuits in the BiCS memory chip 1.\n The register circuit 33 has a plurality of registers 330 to 333. The registers 330 to 333 retain, as setting information, values (hereinafter referred to as potential codes) VVpgm_WL<0> to VVpgm_WL<3>, respectively, which are suitable for the corresponding word lines WL<0> to WL<3>. The potential codes VVpgm_WL<0> to VVpgm_WL<3> for the word lines retained in the registers are output to the potential control circuit 35. In the present embodiment, there are four word lines, and the four registers 330 to 333 corresponding to the four word lines WL<0> to WL<3> are therefore shown here. It goes without saying that the number of registers corresponding to the number of word lines is provided in the register circuit 33.\n The potential control circuit 35 includes a selector (arithmetic unit) 350, a D/A converter 351, a comparator 352 and a VPP pump (potential generator) 353.\n The selector 350 uses the address signal ADR as a selection signal to select a potential code corresponding to a write potential Vpgm_WL of a selected word line from among the potential codes VVpgm_WL<0> to VVpgm_WL<3> retained in the registers 330 to 333. Then, the selector 350 converts a selected one of the potential codes VVpgm_WL<0> to VVpgm_WL<3> into a digital signal Dig_Vpgm, and outputs the digital signal Dig_Vpgm to the D/A converter 351. In this example, the number of word lines is four, so that n=0, 1, 2, 3.\n The D/A converter 351 has a variable resistor 351A and a fixed resistor 351B. The resistance value of the variable resistor 351A is changed in accordance with the digital signal Dig_Vpgm selected by the selector 350.\n The comparator 352 compares the output from the D/A converter 351 with a reference potential (reference value) Vref to control the potential generated by the VPP pump 353.\n The VPP pump 353 outputs the write potential Vpgm_WL to the row control circuit 36A in accordance with the output of the comparator 352 and a write command signal CMD_PGM. The write command signal CMD_PGM is a signal for a writing operation instruction. Moreover, a read command signal CMD_READ shown in FIG. 11 is a signal for a reading operation instruction.\n The row control circuit 36A has a plurality of switch circuits 36A0 to 36A3. The plurality of switch circuits 36A0 to 36A3 are controlled by the address signal ADR and the external command signals CMD_PGM, CMD_READ. Under this control, the plurality of switch circuits 36A0 to 36A3 supply a potential to the word line indicated by the address signal via common interconnections CG<0> to CG<3> of the blocks in the memory cell array and via the word line driver 37.\n For example, during writing operation, the row control circuit 36A controls switches SW1<0> to SW1<3> in the switch circuits 36A0 to 36A3 in accordance with the address signal ADR for the selected word line and the write command signal CMD_PGM so that the write potential Vpgm_WL may be supplied to the selected word line WL. At this moment, switches SW2<0> to SW2<3> are controlled so that the nonselection potentials Vpass may be supplied to nonselected word lines.\n Furthermore, during reading operation, switches SW3<0> to SW3<3> are controlled so that the nonselection potentials Vread may be supplied to nonselected word lines except for a selected word line. At this moment, the ground potential Vss, for example, is supplied to the word line selected for reading.\n Although not shown in FIG. 11, the nonselection potentials Vpass, Vread during the writing operation and the reading operation are separately generated using circuits substantially similar to the circuits 33, 35 for generating the write potential Vpgm_WL.\n In the first adjustment example of the present embodiment, when the first word line WL<0>, for example, is the selected word line, the potential code VVpgm_WL<0> retained in the register 330 of the register circuit 33 is selected in accordance with the address signal ADR as the selection signal of the selector 350. The potential code VVpgm_WL<0> retained in the register 330 indicates the value of the write potential Vpgm_WL<0> to be supplied to the selected word line WL<0> indicated by the address signal ADR.\n The selector 350 outputs the selected potential code to the D/A converter 351 as a digital value Dig_Vpgm, and the D/A converter 351 (variable resistor 351A) outputs an analog value to the comparator 352 in accordance with the input digital value Dig_Vpgm.\n The comparator 352 compares the output value of the D/A converter 351 with the reference potential Vref to control the operation of the VPP pump 353. Under the control of the comparator 352, the VPP pump 353 then generates the write potential Vpgm_WL<0> to be supplied to the selected word line WL<0>.\n Thus, the potential control circuit 35 generates a supply potential suitable for the selected word line WL<0> in accordance with the potential code (setting information) for each word line retained in the register circuit 33, and the generated potential is supplied to the selected word line WL<0> via the row control circuit 36A and the word line driver 37.\n Similarly, the registers 331 to 333 in the register circuit 33 correspond to the second to fourth word lines WL<1> to WL<3>, respectively. In accordance with the address signal ADR input to the selector 350, the potential codes VVpgm_WL<1> to VVpgm_WL<3> retained in the registers 331 to 333 are selected, and the potential Vpgm_WL suitable for each of the word lines WL<1> to WL<3> is generated by the potential control circuit 35. Then, the generated potential is supplied to the selected word line.\n As described above, the supply potential (e.g., a write potential) suitable for each of the word lines WL<0> to WL<3> is generated by the circuits shown in FIG. 11 in accordance with the potential code retained in the register circuit, and the generated potential can be supplied to the selected word line.\n Consequently, according to the BiCS memory (three-dimensionally stacked nonvolatile semiconductor memory) in the first adjustment example of the embodiment of the present invention, the characteristic variations of the memory cells can be compensated for.\n (b) Adjustment Method\n A method of acquiring a potential suitable for each of the word lines is described with FIG. 12. In addition, the method is described here using FIGS. 7, 8 and 11.\n FIG. 12 is a flowchart for explaining the operation of adjusting the word line supply potential to a potential suitable for each of the word lines. FIG. 13 is a graph showing one example of the relation between the time of potential application to the word line and the intensities of the supply potentials during writing of data.\n For example, the BiCS-NAND flash memory is configured to complete writing with a constant pulse width and a constant number of pulses so that the writing speed (writing time) of the memory cell may be constant. Therefore, when there are variations in shape as shown in FIG. 6, the write potential provided to the upper side (bit line side) word line WL<3> is greater than the potential provided to the lower side (semiconductor substrate side) word line WL<0> if writing of data is set to be achieved within the constant writing time as shown in FIG. 13. In the case of the nonselection potential Vpass for sufficiently boosting up the channel area of the nonselected cell during the writing operation, the potential provided to the upper side word line WL<3> is also greater than the potential provided to the lower side word line WL<0>.\n Specifically described here is an operation wherein in the step of testing the BiCS memory chip 1, an initial write potential iniVpgm_WL provided to the word line is adjusted so that a write potential which allows writing of data to be finished within a predetermined writing time is set as a write potential suitable for each of the word lines WL<0> to WL<3> (hereinafter referred to as trimming processing).\n First, as shown in FIG. 12, the address signal ADR and a value (potential code) indicating the intensity of the initial write potential iniVpgm_WL are input to the internal circuits in the BiCS memory chip 1 from outside of the memory chip 1 (e.g., the controller 2) via the control pins 11A as to 11G and the I/O pin 11H.\n The address signal ADR indicates the addresses of the selected word line and the selected cell, and is input to the potential control circuit 35 and the row/column control circuits 36A, 36B.\n The potential code indicating the intensity of the initial write potential iniVpgm_WL is retained in the registers 330 to 333 of the register circuit 33 in accordance with the input address signal ADR (step ST1). This initial write potential iniVpgm_WL is a potential of given intensity applied to a certain word line WL (in the present embodiment, n=0, 1, 3, 4).\n In accordance with the input address signal ADR and the potential code (setting information), the initial write potential iniVpgm_WL is generated by the potential control circuit 35 shown in FIGS. 8 and 11. Further, the row/column control circuits 36A, 36B shown in FIG. 8 drive the word line driver 37 and the data cache/sense amplifier 38, and the word line and the bit line indicated by the address signal ADR are selected.\n Using the initial write potential iniVpgm_WL, given write data separately input from the I/O pin 11H is written into the selected cell connected to the selected word line (here, the first word line WL<0>) (step ST2).\n At this point, whether the data has been written within a predetermined period is judged (step ST3). The writing time is judged in such a manner that the controller 2 (or the host 3) provided outside the memory chip 1 performs monitoring at predetermined time intervals. This monitoring is performed in accordance with the output from the control pin 11G which is provided in the memory chip 1 and which corresponds to the ready/busy signal (R/B) or in accordance with a busy status judgment obtained via the I/O pin 11H.\n In addition, the threshold voltage of the memory cell after writing shows a given distribution shape depending on how the data is stored therein. Thus, it is possible to use a method wherein the controller 2 (or the host 3) acquires the distribution shape of the threshold voltage to judge whether data has been written in the predetermined distribution shape within a given time by the initial write potential used for writing.\n When writing of the data is completed within the predetermined writing time (predetermined period), the initial write potential iniVpgm_WL provided to the selected word line WL<0> is judged to be a potential suitable as the write potential for the selected word line WL<0>. Then, this initial write potential iniVpgm_WL<0> is set as the write potential Vpgm_WL<0> for the selected word line WL<0>.\n When writing of the data is not completed within the predetermined period, the initial write potential iniVpgm_WL<0> provided immediately before the writing is judged to be unsuitable. Then, in order to obtain a potential suitable for a write potential to be provided to the selected word line (the first word line WL<0>), the value provided immediately before the writing is replaced with another value to reset a new initial write potential (step ST4).\n Furthermore, data is written again into the memory cell connected to the same selected word line WL<0>, and whether the writing has been finished within the predetermined time is judged (steps ST2, ST3). In this manner, the operation from step ST2 to step ST4 is repeated until an initial write potential which allows writing of data to be finished within the predetermined period is obtained.\n For example, when writing of data considerably exceeds the predetermined period, the set initial write potential iniVpgm_WL<0> is judged to be too low, and the value of this initial write potential is increased to run a test again. In contrast, when writing of data is considerably shorter than the predetermined period, this means good writing characteristics of the memory cell, and there is no need to reset the initial write potential. However, considering deterioration over long-term use, a more suitable write potential Vpgm_WL<0> may also be obtained when writing of data is much shorter than the predetermined period.\n When it is judged that data has been written within the predetermined period, whether to perform the trimming processing for the same word line again is judged considering statistical variations and manufacturing variations of the plurality of memory cells connected to one word line (step ST5). In addition, whether to perform the trimming processing for the same word line may be judged considering the time required for the test and the accuracy of the test.\n When it is judged that the trimming processing is performed again for the same word line, a potential code having a value obtained by the trimming processing in steps ST1 to ST4 is stored in a setting information storage area (not shown) of the memory cell array 30 in the BiCS memory chip 1 or stored in a storage area (not shown) of the controller 2 or the host 3 outside the BiCS memory chip in order to obtain a more desirable trimming value of the write potential by use of averaging processing or minimum value searching processing (step ST6).\n Subsequently, the trimming processing is performed again for, for example, the word line for which the supply potential (write potential) has been once adjusted. When the trimming processing is thus performed more than one time for the same word line, the trimming processing may be performed more than one time for the same memory cell connected to the same word line or for a different memory cell connected to the same word line.\n When it is judged in step ST5 in FIG. 12 that the trimming processing is not performed again for the same word line, arithmetic processing such as the averaging processing, the minimum value searching processing and abnormal value exclusion is performed by the controller 2 (or the host 3) provided outside the BiCS memory chip 1 in order to obtain a trimming value suitable for the word line which has been subjected to the trimming processing (step ST7). A potential Vpgm_WL is obtained as a result of the arithmetic processing. In the case where a suitable potential is obtained by the trimming processing one time, the flow may move to the next step without performing the above-mentioned arithmetic processing.\n Furthermore, the arithmetic result is inspected with regard to the word line which has been subjected to the trimming processing by use of the trimming value (step ST8). The arithmetic result is thus inspected for the following reason. As a BiCS memory having high storage capacity is generally shipped permitting a certain number of defective bits and defective blocks, a certain percentage of defective bits or defective blocks may also be contained in the test step that uses the trimming processing as in this example. When it is detected in the process of inspecting the arithmetic result that a block includes an abnormal value and it is judged that the block should be treated as a defective cell (defective block), defect processing is separately performed, including, for example, replacement with a redundant block or bad block processing.\n After it is judged by the inspection step ST8 that the obtained potential Vpgm_WL is a proper trimming value, this trimming value is treated as a potential suitably supplied to the word line WL<0> which has been subjected to the trimming processing. Then, a potential code corresponding to this potential (trimming value) is written into the setting information area (not shown) of the memory cell array 30 in the BiCS memory chip 1 or into the register circuit 33 in accordance with a command signal from the controller 2 (or the host 3) (step ST9).\n Thus, the trimming processing for the word line targeted for the adjustment of the supply potential ends.\n As described above, the initial write potential iniVpgm_WL is adjusted so that the write potential Vpgm_WL suitable for each of the plurality of word lines (in the present embodiment, four word lines) in the memory cell army 30 may be obtained.\n Therefore, according to the BiCS memory in the first adjustment example of the embodiment of the present invention, the characteristic variations of the memory cells constituting the BiCS memory can be compensated for.\n In the case described in the present adjustment example, the potential provided to the first word line WL<0> is adjusted and set. However, it goes without saying that the potentials provided to the second to fourth word lines WL<1> to WL<3> can also be adjusted and set to suitable potentials by use of steps ST1 to ST9 shown in FIG. 12.\n Moreover, although the trimming processing for the write potential provided to each of the plurality of word lines has been illustrated in the present adjustment example, the non-selection potential Vpass for writing operation or the selection potential/nonselection potential for reading operation can also be adjusted and set to a potential suitable for each of the word lines by use of a similar circuit configuration and method.\n (3.2) Second Adjustment Example\n (a) Circuit Configuration\n A second adjustment example for the potentials provided to the word lines is described with FIG. 14. It should be noted that in the present adjustment example, the same symbols are assigned to the same components as the components in the first adjustment example described above and a detailed description of such components are given as needed.\n FIG. 14 shows the configuration of the circuits used in the second adjustment example of the embodiment of the present invention.\n The register circuit 33 in the present adjustment example has a plurality of registers 335 to 338. One (first register) 335 of these registers retains a reference value of a potential suitable for use in writing or reading. This reference value is, for example, a value which indicates a potential to be supplied to a certain word line, and in the description of this example, a potential code VVpgm_WL<0> indicating a write potential to be supplied to the first word line WL<0> is the reference value (hereinafter referred to as a reference code).\n The other registers (second registers) 336, 337, 338 provided in the register circuit 33 respectively retain potential codes (hereinafter referred to as difference codes) DVpgm_WL<1>, DVpgm_WL<2>, DVpgm_WL<3>. Each of these potential codes DVpgm_WL<1>, DVpgm_WL<2>, DVpgm_WL<3> corresponds to a difference value between the potential serving as the reference value and supplied to the first word line WL<0> and the write potential to be supplied to each of the other word lines WL<1>, WL<2>, WL<3>.\n Instead of the selector 350 in FIG. 11, a selector 355 and an adder 356 are provided in the potential control circuit 35 in FIG. 14.\n The selector (arithmetic unit) 355 uses an address signal ADR as a selection signal to select one of the inputs from the registers 336 to 338, and outputs the selected input to the adder (arithmetic unit) 356. In addition, the write potential for the first word line WL<0> is the reference value, so that when an address signal ADR indicating the first word line WL<0> is input, the selector 355 outputs \u201c0\u201d to the adder 356.\n The adder 356 adds the reference code VVpgm_WL<0> to one of the difference codes DVpgm_WL<1> to DVpgm_WL<3> output from the selector 355. This additional value is provided to the variable resistor 351A forming the D/A converter 351, as a digital value Dig_Vpgm for a write potential to be supplied to the selected word line.\n Thus, in the present adjustment example, a potential suitable for each of the word lines WL<0> to WL<3> is generated in accordance with the reference code VVpgm_WL<0> for a write potential and the difference code DVpgm_WL<1>, DVpgm_WL<2>, DVpgm_WL<3>, and the potential is supplied to the selected word line.\n In the present adjustment example, the potential to be supplied to a certain word line (here, the first word line WL<0>) is set as the reference value (reference code). In this case, the potential to be supplied to each of the other word lines WL<1> to WL<3> can be retained in each register as a difference value (difference code) with respect to the reference value.\n For example, when a write potential is represented by 8 bits, a register of 8 bits is needed for each of the word lines in the first adjustment example.\n In contrast, in the present adjustment example, although it depends on the extent that a write potential is represented, the difference code can be represented by a smaller number of bits than the reference code. For example, when the reference code is represented by 8 bits, the registers 336 to 338 for retaining the difference codes can supply potentials suitable for the respective word lines as in the first adjustment example if these registers can indicate a maximum of 7 bits. Thus, the storage capacities of the registers 336 to 338 can be lower, such that the registers 336 to 338 can be smaller in size.\n Thus, according to the second adjustment example, the characteristic variations of the memory cells can be compensated for by the reference code indicating the reference value of the supply potential retained in the register circuit 33 and by the difference codes, and the size of the memory chip can be reduced.\n In addition, in the present adjustment example, the write potential used as the reference value and supplied to the first word line WL<0> tends to be lower than the write potentials for the other word lines WL<1> to WL<3> (see FIG. 13). Therefore, when the write potential supplied to the first word line serves as the reference value as in the present adjustment example, a write potential equal to or higher than the reference value is set and generated, so that the circuit configuration includes the adder 356. This can make a contribution to easier control of the circuits and to the reduction in circuit scale. On the contrary, when the potential supplied to the fourth word line WL<3> is the reference value, the write potential supplied to the fourth word line tends to be higher than the write potentials for the other word lines. Therefore, in this case, write potentials equal to or lower than the reference value are set and generated for the other word lines WL<0> to WL<2>, so that a circuit configuration which uses a subtracter instead of the adder 356 is preferable.\n (b) Adjustment Method\n In the second adjustment example, a write potential suitable for each word line is adjusted and set by an operation substantially similar to that in steps ST1 to ST9 shown in FIG. 12.\n As described above, in this example, the supply potential for a certain word line (e.g., the first word line WL<0>) is used as the reference value (reference code VVpgm_WL<0>), and for the supply potential for each of the other word lines WL<1> to WL<3>, a difference value (difference code DVpgm_WL<1>, DVpgm_WL<1>, DVpgm_WL<3>) with respect to the reference value VVpgm_WL<0> is obtained.\n Thus, the write potential Vpgm_WL<0> suitable for the first word line WL<0> and serving as the reference value is set by the trimming processing shown in FIG. 12.\n In the trimming processing for the second to fourth word lines WL<1> to WL<3>, given difference codes DVpgm_WL<1> to DVpgm_WL<3> are added to the reference code VVpgm_WL<0>, such that the supply potentials are adjusted, and supply potentials suitable for the other word lines WL<1> to WL<3> are set.\n Then, the reference code indicating the supply potential (reference potential) suitable for the referential word line, and the difference codes DVpgm_WL<1> to DVpgm_WL<3> indicating the difference values between the reference potential and the supply potentials suitable for the other word lines WL<1> to WL<3> are stored in the register circuit 33 and the memory cell array 30.\n As described above, in the second adjustment example as well, a potential of given intensity can be adjusted to set a word line supply potential suitable for each of the word lines WL<0> to WL<3>.\n Thus, in the second adjustment example of the embodiment of the present invention, each of the word lines WL<0> to WL<3> of the BiCS memory can be supplied with the potential suitable therefor as in the first adjustment example.\n Consequently, in the second adjustment example of the embodiment of the present invention, the characteristic variations of the memory cells can be compensated for as in the first adjustment example.\n (3.3) Third Adjustment Example\n A BiCS memory according to a third adjustment example of the embodiment of the present invention is described with reference to FIGS. 15 to 17. It should be noted that the same symbols are assigned to the same components as the components in the first and second adjustment examples and such components are described as needed.\n As has been described with FIGS. 5 and 6, in the BiCS memory, fabrication dimensions such as the diameter of the hole in which the active layers are embedded tend to be smaller on the lower side (semiconductor substrate side) than on the upper side. For example, when the addresses (formation positions) of the word lines WL<0> to WL<3> are correlated with the variations in the hole diameter, the addresses of the word lines and several coefficients are provided to acquire an approximation function, and this approximation function may be used to enable the supply of potentials suitable for the word lines.\n In the illustration of the present adjustment example, variations in shape (fabrication) are represented by an approximation function, and a potential suitable for each of the word lines is set and supplied using the approximation function. In addition, approximation using a linear function is illustrated in this example.\n (a) Circuit Configuration\n FIG. 15 shows the configuration of the circuits used in the third adjustment example of the embodiment of the present invention.\n The register circuit 33 in this example has registers 339A, 339B for retaining coefficients A, B of a linear function. In this example, potentials supplied to the word lines are adjusted and set by the linear function, so that there are provided two registers for retaining the coefficient A indicating the inclination of the linear function and the coefficient B indicating the intercept of the linear function. However, it goes without saying that the number of registers varies depending on the order of the approximation function.\n In the potential control circuit 35, an arithmetic circuit 357 is provided instead of the selector and the adder. The coefficients A, B output from the register circuit 33 and an address signal ADR of a selected word line are input to the arithmetic circuit 357. In this example, the address signal ADR is a variable X. This arithmetic circuit 357 executes arithmetic processing, for example, on the basis of a linear function Y=AX+B. More specifically, in the case of Y=A\u00d7X (X\u2212ADR)+B, the multiplication A\u00d7X is first performed and then the addition of the coefficient B is performed in the arithmetic circuit 357.\n Furthermore, the arithmetic circuit 357 outputs the calculated value Y to the D/A converter 351 as a digital value Dig_Vpgm.\n Thus, when the calculated value Y (=Dig_Vpgm) can be represented by the linear function of the write selection address signal ADR, the coefficient A corresponding to the inclination and the coefficient B corresponding to the intercept are set, so that the potential suitable for each of the word lines can be supplied.\n In the case of the present adjustment example, the two coefficients are treated as setting information for supplying the potentials suitable for the respective word lines. Therefore, the present adjustment example requires neither the use of the registers 330 to 333 for retaining the potential codes of the potentials suitable for the respective word lines for all of the word lines WL<0> to WL<3> as in the first adjustment example nor the use of the registers 335 to 338 for retaining the reference code and the difference codes for the respective word lines as in the second adjustment example. That is, when the characteristic variations are approximated by the linear function as in the present adjustment example, two registers 339A, 339B have only to be disposed in the register circuit 33.\n Therefore, the present adjustment example enables a reduction in the number of registers, that is, a reduction in the scale of the register circuit 33. Especially, the effects of the present adjustment example are greater, for example, when the number of word lines is increased along with the increase of storage capacity.\n Therefore, according to the third adjustment example of the embodiment of the present invention, the potential supplied to each of the word lines is represented by the linear function so that the potential may be suitable for each of the word lines, thereby making it possible to compensate for the characteristic variations of the memory cells and contribute to the size reduction of the memory chip.\n (b) Adjustment Method\n In this example, a method of acquiring the coefficients A, B of the linear function used as the approximation function is described with FIGS. 16 and 17. In the method described here, trimming processing is performed for at least two different word lines, and an approximation function for providing a potential suitable for each of the word lines is derived from the difference between the addresses of the word lines and the difference between write potentials obtained by the trimming processing.\n The two coefficients A, B are indeterminate before the trimming processing. Therefore, in the example described here, an arithmetic operation to acquire the coefficients A, B is performed by use of the separately provided address signal ADR serving as the variable X, wherein the coefficient B corresponding to the intercept of the linear function is fixed at a given value, while the coefficient A is changed.\n First, as shown in FIG. 16, the operation of acquiring the coefficient A is executed for the word line corresponding to the address signal ADR=X1 (ST11). This search for the coefficient A is performed by steps ST11-1 to ST11-9 shown in FIG. 17. Specifically, this operation is as follows:\n As shown in FIG. 17, an initial value a1 is provided to a coefficient A1, and an initial value 0 is provided to the coefficient B (ST11-1).\n Then, using the address signal X1 indicating a certain word line (selected word line) and write data, data is written into the memory cell connected to the selected word line (ST11-2). Further, for example, as in the trimming processing described in the first adjustment example, whether the data has been written within a predetermined period is judged (ST11-3). Here, when writing of the data is not completed within the predetermined period, the initial value a1 is an inappropriate value. Thus, a value different from the value a1 is reset (ST11-4), and an initial value a1 which allows writing of the data to be completed within the predetermined period is searched for.\n When writing of the data has been completed within the predetermined period, it is judged as in the first adjustment example whether to reset the coefficient A1 to a different value for the same memory cell belonging to the same word line or a different memory cell belonging to the same word line to perform writing (ST11-5).\n When sampling of the coefficient A1 is performed again, the coefficient A1 obtained by steps ST11-1 to ST11-4 are temporarily stored in, for example, a storage outside the chip 1 (ST11-6).\n When it is judged in step ST11-5 that sampling of the coefficient A1 is not performed again, the search for the coefficient A for the word line corresponding to the address X1 is ended. When sampling of the coefficient A1 is performed a plurality of times, arithmetic processing such as averaging processing for a plurality of coefficients, the minimum value searching processing and abnormal value exclusion is performed, so that the coefficient A1 is standardized (ST11-7). When the sampling process of the coefficient A1 is performed only once, the obtained value is set as a coefficient A1.\n Subsequently, if necessary, the coefficient A1 is inspected to exclude any abnormal value (ST11-8). Then, the coefficient A1 suitable for the address signal X1 is temporarily retained in the storage area (not shown) provided in the controller 2 or in the setting information area of the memory cell array 30 (ST11-9).\n As a result, the coefficient A=A1 suitable for the address signal X1 is acquired, and the search for the coefficient A1 for the address signal X1 is completed.\n Then, for an address X2 indicating a word line different from the initially selected word line, a coefficient A=A2 suitable for this word line is searched for by an operation similar to the operation in ST11-1 to ST11-9 for obtaining the coefficient A1 (ST12). Thus, the coefficient A=A2 suitable for the word line corresponding to the address signal X2 is acquired.\n In the case of the approximation to the linear function as in this example, the coefficients A, B are obtained by using, for example, a two-point approximation (ST13).\n As the coefficient A indicates the inclination of the linear function, the coefficient A is calculated here from sample data for the two points (two address signals) X1, X2 by the following equation:\n\nA=(A2\u2212A1)/(X2\u2212X1)\n\n Furthermore, the coefficient B indicates the intercept of the linear function, the coefficient B is calculated by the following equation using, for example, the calculated coefficient A, the address X1 and a sample value Y1 at the address X1:\n\nB=Y1\u2212A\u00d7X1\n\n Consequently, the linear function Y=AX+B as an approximation function is obtained. In addition, the coefficient B may be obtained by the following equation:\n\nB=Y2\u2212A\u00d7X2\n\n Subsequently, the obtained approximation function is inspected (ST14), and the coefficients A, B of the approximation function are stored (ST15).\n As described above, in the third adjustment example of the embodiment of the present invention as well, characteristic variations are represented by the approximation function, so that the characteristic variations of the memory cells can be compensated for.\n Although the coefficients A, B are calculated by the two-point approximation here, the number of samples may be increased to improve accuracy.\n Moreover, the example shown here illustrates one method of setting the coefficients A, B suitable for the approximation function for providing potentials suitable for the respective word lines. As long as the characteristic variations of the memory cells can be compensated for using the approximation function, the present invention is not limited to the example in FIGS. 16 and 17.\n 2. Modification\n A modification of the embodiment of the present invention is described with FIG. 18. It should be noted that the same symbols are assigned to the same members as the members described above and such members are described as needed.\n In the configurations described in the first to third adjustment examples, the internal circuits provided in the memory chip 1 such as the register circuit 33 and the potential control circuit 35 are used to adjust and set the potential provided to each of the word lines to a suitable potential. However, in the embodiment of the present invention, an instruction (command) from the controller 2 or the host 3 may be output to the memory chip 1 via the pads 11A to 11H to adjust the supply potential for each of the word lines to a potential suitable therefor.\n In FIG. 18, for example, four memory chips 1 are connected in parallel to one controller 2. In this configuration, instructions for writing, erasing or reading in the memory cells in each of the memory chips 1 are given by the command issued by the controller 2. At the same time, for example, the setting and adjustment of the supply potentials described in the first to third adjustment examples may also be carried out using the I/O pin 11H and the control pins 11A to 11G so that a suitable potential is supplied to each of the selected word lines. Moreover, the write voltages of the word lines may also be adjusted by the command from the host 3.\n Thus, the devices outside the memory chip 1 such as the controller 2 and the host 3 can be used to adjust the supply potential for each of the word lines.\n Consequently, in the modification of the embodiment of the present invention, the characteristic variations of the memory cells can be compensated for.\n 3. Application\n The technique of the present invention is advantageous to a BiCS-NAND flash memory in which one cell unit is composed of a plurality of serially connected memory cells (NAND strings) to achieve bit cost scalability. While one example of the BiCS-NAND flash memory has been described with FIGS. 1 to 4, the BiCS memory used in the embodiment of the present invention is not limited thereto.\n For example, the embodiment of the present invention can also be applied to a BiCS-NAND flash memory shown in FIGS. 19 to 21. It should be noted that the same symbols are assigned in FIGS. 19 to 21 to members substantially similar in function to the members shown in FIGS. 1 to 4.\n FIG. 19 shows a bird's-eye view of the BiCS-NAND flash memory different in configuration from the example shown in FIG. 1. FIG. 20 shows a bird's-eye view of an extraction of a block (memory cell array). Further, FIG. 21 shows an equivalent circuit diagram of one NAND cell unit provided in the block.\n In the BiCS-NAND flash memory of the configuration shown in FIGS. 19 and 20 as well, three or more conductive layers made of, for example, conductive polysilicon are stacked (in this example, a six-layer structure). Further, a plurality of active layers (active areas) UAA extend through the plurality of stacked conductive layers. Moreover, a memory cell is formed at the intersection of the active layer and the conductive layer. While the lowermost one of the stacked conductive layers is plate-shaped in the BiCS-NAND flash memory shown in FIGS. 19 and 20, the other conductive layers except for the lowermost conductive layer are linearly shaped. In addition, as shown in FIG. 19, the ends of the stacked conductive layers in the x-direction are stepped to allow contact with each of these layers as in the example shown in FIG. 1.\n In the BiCS-NAND flash memory shown in FIGS. 19 and 20, the plurality of active layers UAA are U-shaped when viewed from, for example, the x-direction. As shown in FIG. 20, the U-shaped active layer UAA is structured so that the lower ends of two semiconductor columns SP are connected together by a joint portion JP.\n Accordingly, the source line SL is provided on the side of the semiconductor substrate 23 in the configuration shown in FIGS. 1 to 4. In contrast, in the configuration shown in FIGS. 19 to 20, a source line SL is provided in a layer higher than drain side select gate lines SGD<4>, SGD<5> which are provided on the upper end side of the active layers UAA. More specifically, in the BiCS memory shown in FIGS. 19 and 20, the source line SL is provided between a layer in which bit lines BL<0> to BL are provided and a layer in which the drain side select gate lines SGD<4>, SGD<5> are provided. The source line SL extends in the x-direction, and is connected to one of the two semiconductor columns SP constituting one U-shaped active layer UAA. Further, one source line SL is shared by two NAND cell units NU adjacent in the y-direction.\n Source line side select gate lines SGS<4>, SGS<5> are provided, for example, in the same layer as the bit line side select gate lines SGD<4>, SGD<5>, and are linear (straight) conductive interconnections extending in the x-direction.\n In the example shown in FIGS. 19 and 20, word lines WL<0> to WL<7> are linear (straight) conductive interconnections extending in the x-direction.\n Thus, in the BiCS-NAND flash memory shown in FIGS. 19 and 20, one NAND cell unit NU includes two semiconductor columns SP, so that the number of memory cells in one NAND cell unit is large (eight in this example) as shown in FIG. 21. In addition, four memory cells MC are provided in one semiconductor column SP.\n As in the example shown in FIGS. 20 and 21, the joint portion JP may be connected to a back gate line BG via a back gate transistor BGTr. A conductive layer serving as the back gate line BG is located in a layer lower than a conductive layer serving as the word line, and the plane shape of the back gate line BG is in the shape of, for example, a plate two-dimensionally expanding on the semiconductor substrate 23. The back gate transistor BGTr is provided at the intersection of the joint portion JP and the plate-shaped back gate line BG. The joint portion JP serves as the channel area of the back gate transistor BGTr. The back gate transistor BGTr has, for example, the same structure as the memory cell MC. In addition, in the case of the configuration provided with the back gate line BG as in this example, the joint portion JP is not electrically connected to the semiconductor substrate 23.\n Thus, the BiCS-NAND flash memory shown in FIGS. 19 to 21 also has the configuration in which the memory cells are three-dimensionally stacked, so that there are variations in element characteristics between the memory cell on the side of the select gate lines SGD<5>, SGS<5> and the memory cell on the side of the semiconductor substrate 23 (back gate line BG).\n In the BiCS-NAND flash memory shown in FIGS. 19 to 21, the circuit configuration and coordination method described in the first to third adjustment examples of the embodiment of the present invention can be used to compensate for the variations in element characteristics.\n In addition, in the BiCS-NAND flash memory shown in FIGS. 19 to 21, the diameters of the active layers UAA show about the same tendency (dimension) in the word lines which are provided in the same memory cell unit and which are located at the same position (height from the semiconductor substrate 23) in the z-direction, for example, the word line WL<3> and the word line WL<4>. In this case, the same common switch circuit may be used for the word line WL<3> and the word line WL<4> out of switch circuits 36A0 to 36A3 in a row decoder circuit 36A. Similarly, potentials supplied to the word lines WL<3>, WL<4> can be adjusted using about the same value, so that the same register in the register circuit 33 may be shared between the word line WL<3> and the word line WL<4>.\n It goes without saying that, similarly to the two word lines WL<3>, WL<4>, the switch circuit and the register can be shared between the word line WL<2> and the word line WL<5>, between the word line WL<1> and the word line WL<6> and between the word line WL<0> and the word line WL<7> as long as the two word lines are located at the same position in the z-direction.\n Thus, the embodiment of the present invention can be applied to the BiCS memory shown in FIGS. 19 to 21. Moreover, as shown in FIGS. 19 to 21, even if the number of memory cells (the number of word lines) constituting one NAND cell unit is increased, the switch circuit and the register are shared by the word lines having the same characteristic tendency, so that an increase in circuit scale can be inhibited.\n However, it goes without saying that the number of registers provided in the register circuit 33 or the number of switch circuits in the row decoder circuit 36A, for example, may be changed in accordance with the number (e.g., eight) of word lines in the BiCS-NAND flash memory shown in FIGS. 19 to 21.\n The embodiment of the present invention is not only applicable to the BiCS-NAND flash memories shown in FIGS. 1 to 19 but also to a three-dimensionally stacked nonvolatile semiconductor memory to which the BiCS technique is applied.\n Furthermore, as the memory cell structure of the BiCS memory, a MONOS type or MNOS type structure in which a charge storage layer is made of an insulator (e.g., nitride) is considered effective. However, the present invention is not limited to this example and can also be applied to a floating gate type structure in which a charge storage layer is made of conductive polysilicon.\n Moreover, a data value stored in one memory cell may be binary or multi-level equal to or more than ternary.\n 4. Alternatives\n The trimming processing for the write potential has been mainly described in the embodiment of the present invention. However, a similar configuration and method can be employed to various potentials provided to the word line, such as a supply potential for a selected word line during reading operation, a supply potential for a nonselected word line during writing or reading operation, or a supply potential for a word line during erasing operation.\n In the embodiment of the present invention, processing in the test step during the manufacture of a memory chip has been described by way of example. However, in a user service environment, the optimum value of the write voltage may change due to the deterioration of writing characteristics associated with the deterioration of memory cells. Accordingly, the present embodiment can also be applied to such a case where a potential suitably supplied to each of the word lines is reset.\n Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.\n \n \n What is claimed is:\n \n 1. A three-dimensionally stacked nonvolatile semiconductor memory comprising:\na memory cell array provided in a semiconductor substrate; conductive layers stacked above the semiconductor substrate in the memory cell array in such a manner as to be insulated from one another; a bit line which is disposed above the conductive layers in such a manner as to be insulated from the conductive layers; a semiconductor column which extends through the conductive layers and which has an upper end connected to the bit line and a lower end connected to the semiconductor substrate; word lines for which the conductive layers except for the uppermost and lowermost conductive layers are used; memory cells provided at intersections of word lines and the semiconductor column, respectively; a register circuit which retains operation setting information for the memory cell array and which has information to supply a potential suitable for each of the word lines; and a potential control circuit which controls the potentials supplied to the word lines and which reads the information retained in the register circuit in accordance with a position of a word line in a direction perpendicular to the surface of the semiconductor substrate and which supplies a potential suitable for the word line corresponding to an input address signal. \n \n \n 2. The three-dimensionally stacked nonvolatile semiconductor memory according to claim 1, wherein\nthe register circuit has registers which retain potential codes indicating the potentials suitable for the word lines, respectively, and the potential control circuit selects the potential code corresponding to the input address signal from registers, and supplies the suitable potential to the word line corresponding to the input address signal in accordance with the selected potential code. \n \n \n 3. The three-dimensionally stacked nonvolatile semiconductor memory according to claim 1, wherein\nthe register circuit has a first register which retains, as a reference code, a value indicating the potential suitable for one of the word lines, and one or more second registers which are respectively provided to correspond to the remaining word lines except for the one word line corresponding to the reference code and which retain a difference code between the reference code and a value indicating the potential suitable for each of the remaining word lines; and the potential control circuit selects the difference code corresponding to the input address signal from the one or more second registers, and supplies the suitable potential to a word line corresponding to the input address signal in accordance with a calculation result obtained from the selected difference code and the reference code. \n \n \n 4. The three-dimensionally stacked nonvolatile semiconductor memory according to claim 1, wherein\nthe register circuit has first and second registers which retain first and second coefficients of an approximation function, respectively, and the potential control circuit uses the input address signal as a variable of the approximation function, and supplies the suitable potential to the word line corresponding to the input address signal in accordance with the approximation function using the first and second coefficients. \n \n \n 5. The three-dimensionally stacked nonvolatile semiconductor memory according to claim 1, further comprising:\nan external device which externally controls the operation of the memory cell array, wherein the potential suitable for each of the word lines is set by an instruction from the external device. \n \n \n 6. The three-dimensionally stacked nonvolatile semiconductor memory according to claim 1, wherein\nthe potential control circuit has an arithmetic unit which outputs a value indicating the potential supplied to the one word line in accordance with an output of the register circuit and the address signal, a converter which outputs a converted value of the value indicating the potential supplied to the one word line, a comparator which outputs a comparison value between a reference value and the converted value, and a potential generator which generates a potential suitable for each of the word lines in accordance with the comparison value. \n \n \n 7. The three-dimensionally stacked nonvolatile semiconductor memory according to claim 1, wherein\nthe uppermost conductive layer is a straight first select gate line extending in a second direction intersecting with a first direction, and the lowermost conductive layer is a plate-like second select gate line. \n \n \n 8. The three-dimensionally stacked nonvolatile semiconductor memory according to claim 1, wherein\nthe potential supplied to upper one of word lines is equal to or more than the potential supplied to lower one of the word lines. \n \n \n 9. The three-dimensionally stacked nonvolatile semiconductor memory according to claim 1, wherein\nthe memory cell has an insulating film functioning as a charge storage layer. \n \n \n 10. The three-dimensionally stacked nonvolatile semiconductor memory according to claim 3, wherein\nthe number of bits indicating the difference value in each of the second registor is smaller than the number of bits indicating the reference value in the first registor. \n \n \n 11. The three-dimensionally stacked nonvolatile semiconductor memory according to claim 3, wherein the difference code using writing operation differs from the difference code using reading operation.\n \n \n 12. The three-dimensionally stacked nonvolatile semiconductor memory according to claim 1, wherein\nat least one of the operation setting information and the information to supply a potential suitable for each of the word lines includes adjusted values in each of the word lines to supply the potential suitable for the word line, and the adjusted values are determined based on arithmetic processing for driving results of each of the word lines. \n \n \n 13. A semiconductor memory comprising:\na semiconductor substrate; a stacked body disposed above the substrate, the stacked body including:\na first conductive layer disposed above the semiconductor substrate and configured as a first word line,\na second conductive layer disposed above the first conductive layer and configured as a second word line,\na third conductive layer disposed above the second conductive layer and configured as a third word line, and\na semiconductor column formed in a hole which penetrates the first conductive layer, the second conductive layer, and the third conductive layer in the stacked body, and extends in a first direction perpendicular to the semiconductor substrate;\n a first storage portion which surrounds the semiconductor column, is disposed between the first conductive layer and the semiconductor column, and is configured as a first memory cell, a gate of the first memory cell being electrically connected to the first word line, wherein the first word line, the first storage portion, and a portion of the semiconductor column surrounded by the first storage portion are disposed along a second direction parallel to the semiconductor substrate; a second storage portion which surrounds the semiconductor column, is disposed between the second conductive layer and the semiconductor column, and is configured as a second memory cell, a gate of the second memory cell being electrically connected to the second word line, wherein the second word line, the second storage portion, and a portion of the semiconductor column surrounded by the second storage portion are disposed along the second direction; a third storage portion which surrounds the semiconductor column, is disposed between the third conductive layer and the semiconductor column, and is configured as a third memory cell, a gate of the third memory cell being electrically connected to the third word line, wherein the third word line, the third storage portion, and a portion of the semiconductor column surrounded by the third storage portion are disposed along the second direction, and wherein the first memory cell, the second memory cell, and the third memory cell are connected in series and configured as a memory string; and a control circuit configured to perform a read operation on a condition that a first read voltage for reading first level data is applied to the first word line when the first word line is selected, a second read voltage for reading the first level data is applied to the second word line when the second word line is selected, or a third read voltage for reading the first level data is applied to the third word line when the third line is selected, wherein the third read voltage is larger than the second read voltage, and second voltage is larger than the first read voltage, and wherein a third diameter of the semiconductor column surrounded by the third storage portion in the second direction is larger than a second diameter of the semiconductor column surrounded by the second storage portion in the second direction, and the second diameter of the semiconductor column is larger than a first diameter of the semiconductor column surrounded by the first storage portion in the second direction. \n \n \n 14. The semiconductor memory according to claim 13, wherein\nthe control circuit is configured to perform the read operation on a condition that: a first un-selection voltage is applied to the first word line when the second word line is selected, a second un-selection voltage is applied to the second word line when the first word line is selected, the first un-selection voltage being different from the second un-selection voltage, and a third un-selection voltage different from the first and second un-selection voltages is applied to the third word line when either of the first and second word lines is selected. \n \n \n 15. The semiconductor memory according to claim 14, wherein\nthe first un-selection voltage is lower than the second and third un-selection voltages. \n \n \n 16. The semiconductor memory according to claim 13, wherein the control circuit is configured to perform the read operation on a condition that:\na first un-selection voltage is applied to the first word line when the second word line is selected, a second un-selection voltage is applied to the second word line when the first word line is selected, the first un-selected voltage being different from the second un-selection voltage, and a third un-selection voltage different from the first and second un-selection voltages is applied to the third word line when either of the first and second word lines is selected. \n \n \n 17. The semiconductor memory according to claim 16, wherein\nthe first un-selection voltage is lower than the second and third un-selection voltages. \n \n \n 18. The semiconductor memory according to claim 13, wherein\nthe control circuit is configured to a perform a program operation on a condition that: a first program voltage is applied to the first word line when the first word line is selected, a second program voltage is applied to the second word line when the second word line is selected, the first program voltage being different from the second program voltage, and a third program voltage different from the first and second program voltages is applied to the third word line when the third word line is selected. \n \n \n 19. The semiconductor memory according to claim 18, wherein\nthe control circuit is configured to perform the program operation on a condition that: a first pass voltage is applied to the first word line when the second word line is selected, a second pass voltage is applied to the second word line when the first word line is selected, the first pass voltage being different from the second pass voltage, and a third pass voltage different from the first and second pass voltages is applied to the third word line when either of the first and second word lines is selected. \n \n \n 20. The semiconductor memory according to claim 13, wherein the control circuit is configured to perform a program operation on a condition that:\na first program voltage is applied to the first word line when the first word line is selected, a second program voltage is applied to the second word line when the second word line is selected, the first program voltage being different from the second program voltage, and a third program voltage different from the first and second program voltages is applied to the third word line when the third word line is selected. \n \n \n 21. The semiconductor memory according to claim 20, wherein\nthe control circuit is configured to perform the program operation on a condition that: a first pass voltage is applied to the first word line when the second word line is selected, a second pass voltage is applied to the second word line when the first word line is selected, the first pass voltage being different from the second pass voltage, and a third pass voltage different from the first and second pass voltages is applied to the third word line when either of the first and second word lines is selected. \n \n ", + "added": "2016-02-04", + "source": "Google Patents Public Data", + "metadata": { + "license": "Creative Commons - Attribution - https://creativecommons.org/licenses/by/4.0/", + "language": "en", + "publication_date": "2020-02-18" + } +} +{ + "id": "US-30958809-A", + "text": "Sleeve For a T-Bolt and a Sleeve and T-Bolt Combination to Prevent T-Bolt Rotation\n\nABSTRACT\n\nA sleeve ( 1 ) for a T-bolt ( 21 ) comprises a longitudinally extending part ( 2 ) having a first end ( 3 ) and a second end ( 4 ), and a longitudinal axis ( 5 ) extending from the first end ( 3 ) to the second end ( 4 ). The longitudinally extending part ( 2 ) has a through-going interior bore ( 6 ) extending along said longitudinal axis ( 5 ) from said first end ( 3 ) to said second end ( 4 ). The longitudinally extending part ( 2 ) has an exterior surface ( 7 ) with a shape adapted to engage a recess of an object so that the sleeve ( 1 ) is rotationally retained about the longitudinal axis ( 5 ), when said longitudinally extending part ( 2 ) is inserted in said recess of said object. The sleeve ( 1 ) additionally comprises retaining means for retaining a T-bolt ( 21 ) so that said T-bolt ( 21 ) is rotationally retained about the longitudinal axis ( 5 ), when the T-bolt ( 21 ) is inserted in the bore ( 6 ) of said sleeve ( 1 ).\n \n TECHNICAL FIELD\n The present invention relates to a sleeve for a T-bolt, said sleeve comprising a longitudinally extending part having a first and a second end, and a longitudinal axis extending from the first end to the second end, said longitudinally extending part having a through-going interior bore extending along said longitudinal axis from said first end to said second end. The invention also relates to a T-bolt and sleeve combination.\n BACKGROUND ART\n A mechanical joint is a time-saving and easily installed joint that has to ensure a long-term, trouble-free performance. Mechanical joints as described in the ANSI/AWWA C111 standard are one of the primary methods of joining either Ductile-Iron or PVC pipes in the United States. The mechanical joints are for instance used for pipes on water, gas or other fluid distribution/transmission pipe lines. Such a joint comprises a socket or a bell, a gland, a gasket and T-bolts.\n A common problem in assembling this type of joint on a valve is that the T-bolts can rotate out of the mechanical joint recess of the valve during assembly when using power wrenches or manual wrenches. Valves have recesses instead of holes for T-bolts of the mechanical joint because the body of the valve, particular in the case of gate valves, interferes when trying to slide the T-bolt into a hole. After the pipe is inserted into the bell, the T-bolt is used to pull the gland tight. This causes the gasket to expand and seal the pipe.\n If the T-bolt has rotated during assembly, one end portion of the T-bolt head may no longer abut the flange of the valve, which weakens the joint and in worst case will make the mechanical joint disengage from the valve.\n DISCLOSURE OF INVENTION\n It is the object of the invention to provide a sleeve for a T-bolt, which is applicable for T-bolts used in for instance mechanical joints, and which ensures that the T-bolt does not rotate during assembly or use.\n This is according to invention obtained by said longitudinally extending part having an exterior surface with a shape adapted to engage a recess of an object so that the sleeve is rotationally retained about the longitudinal axis, when said longitudinally extending part is inserted in said recess of said object, and wherein the sleeve comprises retaining means for retaining a T-bolt so that said T-bolt is rotationally retained about the longitudinal axis, when the T-bolt is inserted in the bore of said sleeve.\n The sleeve thus ensures, when inserted in the recess of a valve, that the sleeve does not rotate in the recess. The retaining means ensure that the T-bolt does not rotate relative to the sleeve, thereby overall ensuring that the T-bolt does not rotate out of the recess.\n According to a particular embodiment of the sleeve, the interior bore is threaded, so that a threaded bolt can be secured to the sleeve via the threads.\n In a preferred embodiment of the sleeve, the exterior surface of the longitudinally extending part comprises at least a first substantially plane surface and a second substantially plane surface. If the sleeve is inserted into a recess with a corresponding first plane surface and a second plane surface, this yields a simple method to ensure that the sleeve is rotationally retained in the recess. Preferably, the first substantially plane surface and the second substantially plane surface are mutually parallel. More preferably, the two surfaces are substantially parallel to the longitudinal axis.\n According to a particularly preferred embodiment of the sleeve according to the invention, the retaining means comprises a bolt head engaging part at the second end of the longitudinally extending part, the shape of said bolt head engaging part being adapted to retain the head of the T-bolt, when said T-bolt is inserted through the bore of the longitudinally extending part. This provides a simple method to ensure that the bolt does not rotate about the longitudinal axis and that the head of the bolt has the correct orientation with respect to the recess.\n According to a preferred embodiment of the sleeve, the bolt head engaging part is oblong and oriented along a transverse axis substantially orthogonal to the two parallel surfaces. It can thereby be ensured that the head of the T-bolt is oriented along for instance the tangent of a circular flange of a valve having a radially extending recess.\n According to a particular embodiment of the invention, the bolt head engaging part has a first surface adapted to abut the bolt head, when said bolt is inserted in the bore of the sleeve, said first surface having a constant profile along the transverse axis. Thereby, it is possible to efficiently retain the head of a T-bolt having a substantially constant cross-section.\n In an embodiment according to the invention, said sleeve is made of plastic. In an alternative embodiment according to the invention, said sleeve is made of a metal or a metal alloy.\n The object of the invention is also obtained by a T-bolt and sleeve combination comprising one of the afore-mentioned sleeves and a T-bolt comprising an oblong head with a first end portion and a second end portion, and a threaded elongated shaft adapted to being inserted in the bore of the sleeve.\n According to a preferred embodiment, the T-bolt and sleeve are mutually fastened by use of an adhesive, such as glue. According to another preferred embodiment, the T-bolt and sleeve are welded together. In both embodiments, the sleeve need not comprise the bolt head retaining part, since the sleeve and T-bolt are mutually fastened. In this case, however, it is essential that the sleeve is correctly oriented with respect to the bolt head so that the bolt head is correctly oriented with respect to the recess, when the sleeve is inserted in the recess.\n \n \n \n BRIEF DESCRIPTION OF THE DRAWING\n The invention is explained in detail below with reference to the drawing, in which\n FIG. 1 shows a first side view of a sleeve and T-bolt combination according to the invention,\n FIG. 2 a second side view of the same sleeve and T-bolt combination according to the invention, rotated 90 degrees compared to FIG. 1,\n FIG. 3 a third side view of the same sleeve and T-bolt combination according to the invention, rotated 180 degrees compared to FIG. 1,\n FIG. 4 a top view of the same sleeve and T-bolt combination according to the invention,\n FIG. 5 a view of a mechanical joint comprising a sleeve and T-bolt combination fastened to a valve of a fire hydrant, and\n FIG. 6 a side view of a second embodiment of a sleeve and T-bolt combination according to the invention.\n \n \n \n BEST MODE FOR CARRYING OUT THE INVENTION\n FIGS. 1-3 show a sleeve 1 and T-bolt 21 combination according to the invention seen from three different sides, where the view of FIG. 2 is rotated 90 degrees compared to the view of FIG. 1, and FIG. 3 is rotated 180 degrees compared to the view of FIG. 1. FIG. 4 shows a top view of the sleeve 1 and T-bolt 21 combination. The sleeve 1 comprises a longitudinally extending part 2 having a first end 3 and a second end 4. The longitudinally extending part 2 is oriented along a longitudinal axis 5. A bore 6 extends through the sleeve 1 from the first end 3 to the second end 4 along the longitudinal axis 5. The sleeve has an exterior surface 7 having a shape adapted to engage a recess of an object, such as a recess in a flange of a fire hydrant valve. The exterior surface 7 has a first plane surface 8 and a second plane surface 9. The two plane surfaces 8 and 9 are mutually parallel and parallel to the longitudinal axis 5. Additionally, the exterior surface 7 has a rounded lateral surface 14 connecting the first plane surface 8 and the second plane surface 9.\n The sleeve 1 additionally comprises a bolt head retaining part 10 disposed at the second end 4 of the sleeve 1. The bolt head retaining part 10 is oblong and oriented along a transverse axis 11 perpendicular to and laterally spaced from the longitudinal axis 5. The bolt head retaining part 10 has a first surface 12, which is adapted to abut a bolt head of a bolt inserted in the sleeve 1.\n A T-bolt 21 is inserted through the bore 6 of the sleeve 1. The T-bolt 21 comprises an oblong head 22 and an elongated threaded 13 shaft 23 inserted through the bore 6 of the sleeve 1. The head 22 of the T-bolt is shaped so that it abuts the first surface 12 of the bolt head retaining part 10, when the T-bolt 21 is fully inserted in the sleeve 1. Thereby, it is ensured that the oblong head 22 of the T-bolt 21 can not rotate relative to the sleeve 1. In this particular embodiment, the bottom of the head 22 of the T-bolt 21 is rounded and the first surface 12 of the bolt head retaining part 10 of the sleeve 1 is correspondingly rounded. However, it is obvious to a person skilled in the art that a variety of shapes is possible in order for the bolt head retaining part 22 to rotationally retain the bolt head 21.\n FIG. 5 shows a mechanical joint 51 connected to a valve flange 41 of a fire hydrant. The flange 41 has a number of radially extending recesses 42, each having a first plane recess surface 43 and second plane recess surface 44. A sleeve 1 together with a T-bolt 21 is inserted in all of the recesses 42. The inner surfaces of the recess are shaped to accommodate the sleeve 1. Thus, the first recess surface 43 engages the first surface 8 of the sleeve 1, and the second recess surface 44 engages the second surface 9 of the sleeve 1. Preferably, the recesses 42 also have a rounded bottom portion in order to abut the rounded lateral surface 14 of the sleeve 1. Thereby, it is further ensured that the sleeve 1 is rotationally retained about the longitudinal axis 5, when inserted in the recess 42. It is, however, sufficient that the two plane surfaces 8 and 9 of the sleeve 1 engage the plane recess surfaces 43 and 44, and that the lateral surface 14 does not necessarily have to abut the bottom portion of the recess 42. Also, other shapes for the exterior surface 7 of the sleeve 1 and the shape of the recess 42 can be anticipated in order to rotationally retain the sleeve 1 in the recess 42.\n The mechanical joint 51 comprises a number of sleeve 1 and T-bolt 21 combinations, a flange 52 having a number of ears 53 with openings, a number of nuts 54, and a gasket 55. The flange 52 is connected to a pipe 56. The elongated shafts 23 of the T-bolts are each inserted through the bore 6 of the sleeve 1 and through an opening in each ear 53 positioned on the rim of the flange 52 of the mechanical joint 51. The mechanical joint 51 is tightened to the flange 41 of the fire hydrant by tightening the nuts 54 to the threaded shaft 23 of the T-bolts 21 so that the gasket 55 is tightly sealed to the flange 41 of the fire hydrant.\n Conventional mechanical joints do not make use of sleeves. Thereby, the T-bolts have a tendency to rotate out of the recesses, especially when power wrenches are used for tightening the nuts. Thereby, the retention force of the bolt head is decreased, since only one end portion of the oblong T-bolt head abuts the inner surface of the flange. This will in worst case make the mechanical joint disengage from the flange of the fire hydrant.\n The sleeves 1 according to the invention, however, each have a bolt head retaining part 10, which ensure that the heads 22 of the T-bolts 21 are rotationally retained about the longitudinal axis 5, when tightening the mechanical joint 51. Thereby, it is ensured that both end portions of the oblong bolt head 22 abut the inner surface of the fire hydrant flange 41, thereby maximising the retention force of the mechanical joint 51.\n However, the sleeve 1 need not have the bolt head retaining part 10 if the sleeve 1 is fastened to the T-bolt 21 by for instance gluing or welding the two parts together. In this case, it only has to be ensured that the sleeve 1 is fastened to the T-bolt 21 in such a way that the oblong bolt head 22 has the correct orientation with respect to the recess 42, when the sleeve 1 with the T-bolt 21 is inserted in the recess 42 of the flange 41. This second embodiment is shown in FIG. 6, where like numerals correspond to like parts of the first embodiment, and the shown view corresponds to the view of the first embodiment in FIG. 2.\n The invention has been described with reference to a preferred embodiment. However, the scope of the invention is not limited to the illustrated embodiment, and alterations and modifications can be carried out without deviating from said scope of the invention. The exterior surface of the sleeve 1 and the shape of the recess 42 can for instance be tapered so as to ensure that the sleeve 1 is radially retained in the recess 42. Furthermore, the sleeve 1 and the recess 42 can be tapered along the longitudinal axis 5, thereby ensuring that the sleeve 1 is axially retained in the recess 42.\n LIST OF REFERENCE NUMERALS\n \n \n 1 sleeve\n 2 longitudinal extending part\n 3 first end\n 4 second end\n 5 longitudinal axis\n 6 bore\n 7 exterior surface\n 8 first plane surface\n 9 second plane surface\n 10 bolt head engaging part\n 11 transverse axis\n 12 first surface of bolt head engaging part\n 13 thread\n 14 rounded lateral surface\n 21 T-bolt\n 22 bolt head\n 23 elongated shaft\n 41 flange\n 42 recess\n 43 first plane recess surface\n 44 second plane recess surface\n 51 mechanical joint\n 52 flange\n 53 loop\n 54 nut\n 55 gasket\n 56 pipe\n \n \n \n \n \n 1. A sleeve (1) for a T-bolt (21), said sleeve (1) comprising\na longitudinally extending part (2) having a first end (3) and a second end (4), and a longitudinal axis (5) extending from the first end (3) to the second end (4), said longitudinally extending part (2) having a through-going interior bore (6) extending along said longitudinal axis (5) from said first end (3) to said second end (4), wherein said longitudinally extending part (2) having an exterior surface (7) with a shape adapted to engage a recess of an object so that the sleeve (1) is rotationally retained about the longitudinal axis (5), when said longitudinally extending part (2) is inserted in said recess of said object, and wherein the sleeve (1) comprises retaining means for retaining a T-bolt (21) so that said T-bolt (21) is rotationally retained about the longitudinal axis (5), when the T-bolt (21) is inserted in the bore (6) of said sleeve (1). \n \n \n 2. A sleeve (1) according to claim 1, wherein the interior bore (6) is threaded.\n \n \n 3. A sleeve (1) according to claim 1, wherein the exterior surface (7) of the longitudinally extending part (2) comprises at least a first substantially plane surface (8) and a second substantially plane surface (9).\n \n \n 4. A sleeve (1) according to claim 3, wherein the first substantially plane surface (8) and the second substantially plane surface (9) are mutually parallel.\n \n \n 5. A sleeve (1) according to claim 1, wherein the retaining means comprises a bolt head engaging part (10) at the second end (4) of the longitudinally extending part (2), the shape of said bolt head engaging part (10) being adapted to retain the head (22) of the T-bolt (21), when said T-bolt (21) is inserted through the bore (6) of the longitudinally extending part (2).\n \n \n 6. A sleeve (1) according to claim 5, wherein the bolt head engaging part (10) is oblong and oriented along a transverse axis (11) substantially orthogonal to the two parallel surfaces.\n \n \n 7. A sleeve (1) according to claim 5, wherein the bolt head engaging part (10) has a first surface (12) adapted to abut the bolt head (22), when said bolt (21) is inserted in the bore (6) of the sleeve (1), said first surface (12) having a constant profile along the transverse axis (11).\n \n \n 8. A sleeve (1) according to claim 1, wherein said sleeve (1) is made of plastic.\n \n \n 9. A sleeve (1) according to claim 1, wherein said sleeve (1) is made of a metal or a metal alloy.\n \n \n 10. A T-bolt (21) and sleeve (1) combination comprising a sleeve (1) according to claim 1 and a T-bolt (21) comprising an oblong head (22) with a first end portion and a second end portion, and a threaded elongated shaft (23) adapted to being inserted in the bore (6) of the sleeve (1).\n \n \n 11. A T-bolt (21) and sleeve (1) combination according to claim 10, wherein the retaining means is an adhesive, such as glue, used for mutually fastening the T-bolt and the sleeve (1).\n \n \n 12. A T-bolt (21) and sleeve (1) combination according to claim 10, wherein the retaining means is a welding for mutually fastening the T-bolt (21) and the sleeve (1).\n \n", + "added": "2006-07-31", + "source": "Google Patents Public Data", + "metadata": { + "license": "Creative Commons - Attribution - https://creativecommons.org/licenses/by/4.0/", + "language": "en", + "publication_date": "2009-11-26" + } +} +{ + "id": "US-31317805-A", + "text": "Semiconductor component with passivation layer\n\nABSTRACT\n\nA semiconductor component has a semiconductor body and also a metal/insulation structure arranged above the semiconductor body and having a plurality of metal regions and insulation regions laterally adjoining one another. The metal regions serve for supplying the semiconductor body with electric current. Furthermore, the semiconductor component has a passivation layer arranged on the metal/insulation structure. The passivation layer includes a metal or a metal-containing compound.\n\n CROSS-REFERENCE TO RELATED APPLICATIONS\n This Utility patent application claims priority to German Patent Application No. DE 10 2004 061 307.9, filed on Dec. 20, 2004, which is incorporated herein by reference.\n BACKGROUND\n The invention relates to a semiconductor component with passivation layer.\n Semiconductor components are generally provided with a passivation layer in order to minimize the influences of the environment, for example temperature fluctuations or moisture, on the semiconductor components. The passivation layer may furthermore serve for mechanical stabilization of the semiconductor components.\n If a semiconductor component with passivation layer is exposed to severe temperature fluctuations, then cracks may arise in the passivation layer on account of different coefficients of thermal expansion of the passivation layer and of regions of the semiconductor component which adjoin the passivation layer. This is the case, for example, when the semiconductor component is closed off toward the outside by a molding compound adjoining the passivation layer, since the coefficients of thermal expansion of the passivation layer and the molding compound may deviate greatly from one another. If a crack arises within a critical region of the semiconductor component, for example in a region that insulates two conductive regions from one another, then the crack may lead to the impairment of the functioning of the semiconductor component. In the worst case, the cracking leads to a total failure of the semiconductor component.\n The problem area described above is explained by way of example in the description below with reference to FIGS. 1 to 3.\n FIG. 1 illustrates a cross section through a detail from a typical power semiconductor component. Arranged on a semiconductor body 1, which includes silicon in this embodiment, is a metal/insulation structure 2, which is in turn covered by a passivation layer 3. A buffer layer 4 is provided on the passivation layer 3, a molding compound layer 5, which functions as housing termination, in turn being arranged on said buffer layer. In this embodiment, the metal/insulation structure 2 has a first to third metal plane 6, 7 and 8, which are electrically connected to one another by conductive connections 9. The metal planes 6, 7, 8 are divided into different metal plane regions (in this embodiment, the first metal plane 6 is divided into five metal plane regions 6 1-6 5, and the second and third metal planes 7, 8 are divided into in each case three metal plane regions 7 1-7 3 and 8 1-8 3, respectively) which are electrically insulated from one another by insulation structures 10.\n Since the coefficients of thermal expansion of the passivation layer 3 and the molding compound layer 5 generally turn out to be greatly different, great tensile forces oriented in the lateral direction occur at the transition between the passivation layer 3 and the buffer layer 4 in the event of temperature fluctuations, which is indicated by the arrows 11 illustrated in FIG. 2. If the tensile stresses exceed specific threshold values, then cracks 12 arise within the passivation layer 2. The cracks 12 arise in particular in regions of the passivation layer 3 which adjoin edges 13 of the topmost metal plane (third metal plane 8).\n FIG. 3A illustrates a micrograph of a region from FIG. 2 which is identified by reference numeral 15. A crack 12 can clearly be seen, said crack having formed at an edge 13 of the metal region 8 2 within the passivation layer 3. The crack 12 illustrated in FIG. 3A is noncritical since moisture cannot pass into the semiconductor body 1 or into insulating intermediate regions (insulation structure 10) via said crack.\n The situation proves to be more critical in a case such as is illustrated in FIG. 3B. FIG. 3B illustrates a plan view of a semiconductor component with a metallization 16. The metallization 16 is pervaded or interrupted by insulating regions 17. A passivation layer (transparent here) is provided above the metallization 16 and the insulating regions 17, cracks 12 having arisen in said passivation layer due to thermal stress. The cracks 12 run above the insulating regions 17 and thus constitute a risk that has to be taken seriously since proper insulation between the individual regions of the metallization 16 or between conductive regions lying below the metallization is no longer ensured on account of the cracks 12.\n SUMMARY\n One embodiment of the invention specifies a semiconductor component whose functioning is not impaired, or is impaired only to a small extent, in the event of cracking in the passivation layer.\n The semiconductor component according to one embodiment of the invention has a semiconductor body and also a metal/insulation structure arranged above the semiconductor body and having a plurality of metal regions and insulation regions laterally adjoining one another. The metal regions serve for supplying the semiconductor body with electric current. Furthermore, the semiconductor component has a passivation layer arranged on the metal/insulation structure. The passivation layer includes a metal or a metal-containing compound.\n In one embodiment, the passivation layer includes NiP, NiB, NiMoP, NiMo, CoW, NiRe, W or TiN or a combination of such elements/compounds. If W, Ti or TiN or a combination of these metals is used, then in the case where a sputtering process is used, conductive connections between the interconnects are interrupted, for example by means of photopatterning.\n In one embodiment, passivation layer made of metal or a metal-containing compound has a very high tear strength. In addition, the adhesion between such materials and the materials usually used for the insulation regions (for example, oxide, nitride, SiC, oxide-nitride or a combination of these materials) is only very weak. This means that cracks in the passivation layer that run above an insulation region can propagate into the insulation region only with very great difficulty. This means that the probability that cracks running above the insulation regions will lead to the total failure of the semiconductor component is relatively low.\n In one embodiment, the passivation layer includes NiP or NiMoP and the material of the metal regions is aluminum.\n The direct bonding of bonding wires on the passivation layer is occasionally problematic since not every passivation layer material is suitable for utilization as a bonding contact area. In one embodiment, therefore, at least partial regions of the passivation layer are coated with thin layers made of Pd or Au that serve as bonding contact areas, so that an electric current can be fed to the semiconductor body via the Pd or Au layer, the passivation layer and the metal/insulation structure connected thereto.\n In one embodiment, thicknesses of the passivation layer are between 50 nm and 5 \u03bcm. However, the invention is not restricted to such thickness ranges.\n Not only the passivation layer itself but also a metal region lying beneath the passivation layer may be damaged by the tensile forces already described which act on the passivation layer in the lateral direction. Thus, in the event of large tensile forces, deformations occur in the metal regions and, in the extreme case, may lead to specific metal regions being bent over or torn away.\n In order to avoid this in one embodiment, the metal regions may be pervaded by stabilization structures. For this purpose, the metal regions are in each case divided into a plurality of metal subregions that are arranged alongside one another and are spaced apart from one another, and the free spaces situated between the metal subregions are (at least partly) filled by the passivation layer in such a way that the metal subregions are electrically connected to one another by the passivation layer. Parts of the metal regions are thus replaced by other conductive materials (the conductive material of the passivation layer). The metal regions are pervaded by conductive stabilization structures in this way. The stabilization structures may also be formed by cutouts in the metal regions which are at least partly filled by the passivation layer.\n In the forgoing description, it had been assumed that the passivation layer covers the whole metal/insulation structure. However, it is also possible that the passivation layer covers only a part of the metal/insulation structure. In this case, the part of the metal/insulation structure that is not covered by the passivation layer is then directly covered by the molding compound. In one embodiment, it is possible to sufficiently reduce external forces directed onto the metal/insulation structure even if the passivation layer covers only a part of the metal/insulation structure. Good results can be achieved for example already if the part of the metal/insulation structure covered by the passivation layer substantially only includes the outer corners and/or the outer edges of the metal regions.\n\n\n \n BRIEF DESCRIPTION OF THE DRAWINGS\n The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate the embodiments of the present invention and together with the description serve to explain the principles of the invention. Other embodiments of the present invention and many of the intended advantages of the present invention will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.\n FIG. 1 illustrates a detail from a known power semiconductor component in a cross-sectional illustration.\n FIG. 2 illustrates a detail from the power semiconductor component illustrated in FIG. 1 in the case of tensile stress in the lateral direction.\n FIG. 3A illustrates a micrograph of a detail from FIG. 2.\n FIG. 3B illustrates a plan view of a detail from a known semiconductor component.\n FIG. 4 illustrates a detail from a first embodiment of the semiconductor component according to the invention in a cross-sectional illustration.\n FIG. 5 illustrates a detail from a second embodiment of the semiconductor component according to the invention in a cross-sectional illustration.\n FIG. 6 illustrates one embodiment of a metal region in a semiconductor component according to the invention in plan view.\n FIG. 7 illustrates a further embodiment of a metal region in a semiconductor component according to the invention in plan view.\n FIG. 8 illustrates a detail from a third embodiment of the semiconductor component according to the invention in a cross sectional illustration.\n FIG. 9 illustrates a detail from the third embodiment of the semiconductor component according to the invention in plan view.\n \n\n\n DETAILED DESCRIPTION\n In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as \u201ctop,\u201d \u201cbottom,\u201d \u201cfront,\u201d \u201cback,\u201d \u201cleading,\u201d \u201ctrailing,\u201d etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments of the present invention can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.\n FIG. 4 illustrates a first embodiment of the semiconductor component according to the invention. The essential difference between this embodiment and the embodiment illustrated in FIG. 2 consists in the fact that the material of the passivation layer 3 includes a metal or a metal-containing compound. The material of the passivation layer 3 is in one case NiP or NiMoP. The consequence of using this material is that the passivation layer, at the locations identified by reference numeral 18, does not adhere or adheres extremely weakly on the insulation structures 10. If a crack arises within the passivation layer 3 above the insulation structures 10 or propgoates in the direction of the insulation structures 10, then said crack has only a very low probability of \u201cjumping over\u201d to the insulation structure 10 and thus damaging the latter, since the passivation layer 3 does not adhere on the regions 18. As already mentioned, the use of such a passivation layer material furthermore has the advantage that the tear strength of the passivation layer 3 is very high.\n FIG. 5 illustrates an embodiment in which a metal region of the topmost metal plane 8, for example the metal region 8 2, is divided into a plurality of metal subregions 19, 20 and 21. The metal subregions 19, 20, 21 are separated from one another by free spaces 22 that are filled by the passivation layer 3. The passivation layer 3 thus electrically connects the metal subregions 19 to 21 to one another. The free spaces 22 filled with passivation layer material constitute stabilization structures that pervade the metal region 8 2. In this way it is possible to prevent a deformation of the metal region 8 2.\n FIGS. 6 and 7 illustrate plan views of a horizontal cross section of a metal region, for example of the metal region 8 2. The metal region 8 2 is pervaded by vertically running cutouts (trenches, holes) 22 which, as indicated in FIG. 6, may have any desired geometrical shapes.\n FIG. 7 illustrates that the cutouts 22 may also be embodied in the form of contiguous trenches. In this embodiment, the metal region 8 2 is divided into four metal subregions 23, 24, 25 and 26. The cutouts 22 form stabilizing transverse bracing and prevent damage to the metal subregions 23, 24, 25 and 26 through deformation or tearing away in the event of high tensile forces in the lateral direction.\n In the embodiments described so far the complete metal/insulation structure 2 is covered by the passivation layer 3. FIG. 8 illustrates the case where the passivation layer 3 (here: NiMoP) covers only a part of the metal/insulation structure 2. The part of the metal/insulation structure 2 which is not covered by the passivation layer 3 may then be directly covered by the molding compound 5. This embodiment bases on the realization of the inventors that already a part of the passivation layer 3 is sufficient to reduce forces applied from outside (from the molding compound 5) onto the metal/insulation structure 2 remarkably. Good results can be achieved for example with the embodiment illustrated in FIG. 8, in which the part of the metal/insulation structure 2 covered by the passivation layer 3 includes substantially only the outer corners and/or the outer edges of the metal regions 8. FIGS. 8 and 9 illustrate a single transistor having a gate metallization (outer region of the metal region 8) as well as a source metallization (inner region of the metal region 8). A source pad 27 as well as a gate pad 28 illustrated in FIGS. 8 and 9 are part of the (structured) passivation layer 3 and serve also as mechanical stabilization elements.\n The embodiment illustrated in FIGS. 8 and 9 illustrates that it is not necessary to \u201cencapsulate\u201d all aluminum regions with NiMoP. Instead, it is also possible to cover only parts of the aluminum regions. Since NiMoP is considerably firmer as aluminum, it is possible to prevent shifted/displaced aluminum lines. The corners of aluminum regions are subjected to the highest risk of being damaged by external forces. It has to be mentioned that it is not absolutely necessary to cover the side walls of the aluminum regions with passivation material (for example NiMoP). It may also be sufficient to only cover parts on the top surface of the aluminum regions (that is, excluding the side walls) with passivation material strengthening elements. In this way, the aluminum regions are only partially strengthened against external forces (forces supplied by the molding compound).\n FIG. 8 illustrates an example of a single transistor having aluminum regions which are partially covered with an NiMoP passivation layer at the outer side of the aluminum regions. Since NiMoP is very rigid, it is possible to reduce forces applied to the corners over the whole conducting line. As a result, the conducting line is not significantly shifted towards the central region of the single transistor. The NiMoP passivation layer may for example be fabricated using a corresponding photo mask.\n FIG. 9 illustrates a plan view of the single transistor illustrated in FIG. 8. The NiMoP strengthening elements are positioned on the outer conducting lines (on the outer surfaces of the conducting lines). If, as illustrated in FIG. 9, a source plate (inner aluminum region 8) is provided, a \u201cminimalistic\u201d approach may be adopted. That is, it may be sufficient to only strengthening the corners of the source plate using NiMoP (or also another material). The strengthening NiMoP elements may be arbitrary shaped elements like triangular elements or other polygon strengthening elements.\n Further aspects of the invention will be discussed in the description below.\n In power IC technologies, large power DMOS transistors are generally positioned at the chip edges. The transistors have large metal plates, the sizes of which may be between a few 0.01 mm2 and a few mm2 and are insulated toward the molding compound of the plastic package with a several hundred nm thick passivation (FIG. 1). Since the chip, the leadframe on which the chip is fixed, and the molding compound have different coefficients of expansion, large tensile forces are exerted on the passivation. The topmost metal layer, comprising aluminum or copper, is often unable to absorb the forces (\u201cModeling of Die Surfaces Features on Integrated Circuits to Improve device Realiability,\u201d John Sauber; and \u201cThin film cracking and ratcheting caused by temperature cycling,\u201d M. Huang, Z. Sao). Therefore, passivation cracks occur and, if appropriate, failures of the chip during operation. The robustness of the chip is generally determined by running through a plurality of temperature cycles. In order to minimize the cracks, a buffer layer such as, for example, a polyimide is often provided between chip passivation and molding compound.\n It has hitherto been possible to keep the cracks fairly small. As a result of the increasing miniaturization of the functions, planarization techniques such as CMP (chemical mechanical polishing) have recently been used in the metallization. These techniques lead to absolutely planar metallization surfaces. As a result, the molding compound forces can accumulate over the areas, resulting in a huge number of large cracks (FIGS. 2 and 3). If these cracks also propagate in the electrical insulation between the individual metallization planes (interlayer dielectric (ILD)), then moisture can penetrate into the chip. In the worst case, short circuits occur, for example, if metal is pressed into the cracks.\n These effects are manifested to an increased extent if, due to the miniaturization, the topmost metal layer turns out to be thick in order to take up higher current densities. The deformability (plasticization) of aluminum increases as a result. This may lead to \u201ctilting over\u201d metal lines.\n Since the cracks in principle arise at the edges of the topmost metal layer and then run along the latter downward into the ILD (FIG. 3), it is necessary either to prevent the cracking itself or to prevent the crack from running into the ILD. Furthermore, the passivation should be provided such that the metal track to be passivated retains its form on account of the shearing forces induced by the molding compound, since a decrease in the electromigration (reliability of the metal track to be passivated under current) must otherwise be reckoned with. These requirements can be achieved by means of a coating of the topmost metal tracks by a metal (FIG. 2).\n Metals have a considerably higher tear strength in comparison with the passivation layer materials generally used (nitrides and oxides). NiP or NiMoP is used in one embodiment. The NiP or NiMoP may be deposited autogalvanically, for example. In one case, passivation layer thicknesses lie between 50 nm and 5 \u03bcm. NiP or NiMoP material does not tear as readily as an oxide or a nitride, and it adheres on aluminum, but not on the underlying ILD. It is thus unlikely that a crack in the NiP or NiMoP will jump over to the ILD. Since the NiP or NiMoP is very hard, the aluminum cannot deform either.\n In order to keep large aluminum regions dimensionally stable despite the huge forces brought about by the molding compound, large aluminum regions (more generally: the topmost metallization) can be patterned into smaller regions (see FIG. 5). The resulting distances between the smaller regions should in one case, however, turn out to be less than twice the thickness of the passivation layer (NiP or NiMoP) in order that the smaller regions are electrically connected to one another again via the NiP or NiMoP. The patterning of the topmost metallization can be carried out in various ways: firstly it is conceivable to introduce holes of whatever form into the topmost metal layer, which are filled either completely or only partly with NiP or NiMoP (see FIG. 6). In the latter case, the sheet resistance increases and is therefore not desirable. Another possibility is to decompose the metal layer into separate metal regions which are then electrically connected again via the NiP or NiMoP of the passivation layer (see FIG. 7).\n Since the bonding reliability on Nip or the NiMoP is not very high, an additional Pd, Au or Pd/Au deposition on the NiP used in one embodiment. These layers can turn out to be very thin and in one case are used in the region of the pads for connection of the bonding wires. Such layers would not be a disturbance on the rest of the NiP (NiMoP), however, so that these layers can be deposited there as well (that is to say over the whole area of the passivation layer). The adhesion between the topmost metallization passivated in this way and the buffer layer (in one case imide) or the molding compound may be produced if no buffer layer is used, by means of a chemical or mechanical adhesion promoter (an adhesion promoter is comparable with an adhesive. By way of example, it is possible to use imide as adhesion promoter between a chip passivation and a molding compound). Furthermore, it is possible to use imides and molding compounds which simultaneously adhere on noble metals and ILD layers.\n In one embodiment of the invention, accordingly, replaces the oxide or nitride passivation of the topmost metal layer by a passivating metal such as NiP, NiB, NiMo, NiMoP, CoW, CoWP or NiRe. Other metals such as W or TiN are also conceivable. These layers cannot be deposited selectively, for which reason an additional selective removal process is used. NiP, NiB, NiMo, NiMoP, CoW, CoWP or NiRe do not adhere in principle on ILDs. Thus, cracks that are induced in them owing to the large shearing forces present cannot run into the ILD.\n FIG. 5 illustrates that tensile forces arise on account of the different coefficients of thermal expansion essentially in the molding compound, which generally expands or contracts eight times more than the silicon chip and metallization. The tensile forces are reduced somewhat by means of the buffer layer 4 (in one case imide) and are directed from outside into the interior of the chip since the molding compound is injected at approximately 180\u00b0 C. around the chip. The operating temperature of the chip generally lies below that.\n Since NiP is conductive in comparison with the metals used as standard (Al and Cu), conductive transverse bracing can be incorporated by means of NiP. Said transverse bracing stabilizes the topmost metal layer with respect to the shearing forces from the molding compound.\n FIG. 6 illustrates a horizontal section through a large metal layer, revealing the side wall passivation and the patterned metal layer to be passivated. The transverse bracing may be regions within the topmost metal layer. They need not be contiguous. FIG. 7 illustrates that continuous transverse bracing is also possible. The latter should rather be used in the case of large metal regions.\n Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.\n\n\n \n 1. A semiconductor component, comprising:\na semiconductor body;\na metal/insulation structure arranged above the semiconductor body as an uppermost metal/insulation structure of the semiconductor component and having a plurality of metal regions and insulation regions laterally adjoining one another, the metal regions configured to supply the semiconductor body with electric current; and\na passivation layer covering exposed surfaces of the metal regions and exposed surfaces of the insulation regions of said uppermost metal/insulation structure that are not covered by the metal of the metal regions, said passivation layer being deposited as a sole layer of a uniform passivation material and configured to minimize influences of the environment and to avoid or minimize adverse effects on a function of the semiconductor component in the event of cracking in the passivation layer;\nwherein said uniform passivation material is a metal or a metal containing compound which has a high tear strength and a low adhesion strength on the insulation regions.\n\n \n \n 2. The semiconductor component of claim 1, wherein the uniform passivation material is one or more of a group comprising NiP, NiB, NiRe, NiMoP, NiMo, CoW, Ti and TiN.\n \n \n 3. The semiconductor component of claim 2, wherein a layer made of one or more of a group comprising Pd and Au is arranged on the sole passivation layer.\n \n \n 4. The semiconductor component of claim 1, wherein the thickness of the sole passivation layer is between 50 nm and 5 \u03bcm.\n \n \n 5. The semiconductor component of claim 1, wherein at least one of said metal regions is divided into a plurality of metal subregions that are arranged alongside one another and are spaced apart from one another, free spaces situated between the metal subregions being at least partly filled by the sole passivation layer in such a way that the metal subregions are electrically connected to one another by the passivation layer.\n \n \n 6. The semiconductor component of claim 1, wherein at least one of said metal regions has a cutout, which is at least partly filled by the sole passivation layer.\n \n \n 7. The semiconductor component of claim 1, wherein the shape and dimension of the sole passivation layer are chosen such that external forces directed onto the metal/insulation structure are reduced significantly and the metal or metal-comprising compound has a high tear strength against tensile forces acting on account of thermal expansion on the passivation layer in the lateral direction.\n \n \n 8. The semiconductor component of claim 1, wherein the part of the metal/insulation structure covered by the sole passivation layer includes the outer corners and/or the outer edges of at least one metal region.\n \n \n 9. A semiconductor component comprising:\na semiconductor body;\na plurality of metal regions above the semiconductor body configured to supply the semiconductor body with electric current;\ninsulating regions above the semiconductor body and laterally adjoining the metal regions, said plurality of metal regions and said insulating regions being provided as an uppermost metal/insulation structure of the semiconductor component;\na passivation layer covering exposed surfaces of the metal regions and exposed surfaces of the insulation regions of the uppermost metal/insulation structure that are not covered by a metal of the metal regions;\nwherein the passivation layer is deposited as a sole layer of a uniform passivation metal material or passivation metal compound material being selected for providing the passivation layer with a very high tear strength, the adhesion between said metal or metal compound and the insulating region being very weak.\n\n \n \n 10. The semiconductor component of claim 9, wherein the uniform passivation material is a metal-containing compound.\n \n \n 11. The semiconductor component of claim 10, wherein the uniform passivation material comprises one or more of a group comprising NiP, NiB, NiRe, NiMoP, NiMo, CoW, Ti and TiN.\n \n \n 12. The semiconductor component of claim 9, wherein the thickness of the sole passivation layer is between 50 nm and 5 \u03bcm.\n \n \n 13. The semiconductor component of claim 9, wherein at least one of said metal regions is divided into a plurality of metal subregions that are arranged alongside one another and are spaced from one another, free spaces situated between the metal subregions being at least partly filled by the sole passivation layer in such a way that the metal subregions are electrically connected to one another by the passivation layer.\n \n \n 14. The semiconductor memory component of claim 9, wherein at least one of said metal regions has a cutout, which is at least partly filled by the sole passivation layer.\n \n \n 15. The semiconductor memory component of claim 9, wherein the sole passivation layer covers only a part of the metal/insulation structure.\n \n \n 16. A method for fabricating a semiconductor component comprising:\nfabricating a semiconductor body;\narranging a metal/insulating structure above the semiconductor body, the metal/insulation structure being an uppermost metal/insulation structure of the semiconductor component and having a plurality of metal regions and insulation regions arranged laterally joining one another;\ndepositing a sole layer of a uniform metal-containing or a metal compound containing passivation material to cover exposed surfaces of the metal regions and exposed surfaces of the insulation regions of the uppermost/insulating structure that are not covered by the metal of the metal regions, wherein the metal or the metal compound contained in the sole layer of passivation material is selected such that the passivation layer has high tear strength and low adhesion strength on the insulation regions.\n\n \n \n 17. The method of claim 16, further comprising depositing the sole passivation layer with a material selected from a group comprising NiP, NiB, NiRe, NiMoP, NiMo, CoW and TiN.\n \n \n 18. The method of claim 17, further comprising arranging a layer on the sole passivation layer a layer of a material selected from a group comprising Pd and Au.\n \n \n 19. The method of claim 16, wherein the thickness of the sole passivation layer is between 50 nm and 5 \u03bcm.\n \n", + "added": "2005-12-20", + "source": "Google Patents Public Data", + "metadata": { + "license": "Creative Commons - Attribution - https://creativecommons.org/licenses/by/4.0/", + "language": "en", + "publication_date": "2008-12-30" + } +} +{ + "id": "US-30110189-A", + "text": "Splicing system\n\nABSTRACT\n\nThe known splicing system for paying out a rolled sheet and continuously feeding a sheet to a downstream machine of the type that the system includes a sheet splicer for stopping a running sheet and splicing a tip end of another new sheet therewith, a tension roll in a dancer roll section for forming a sheet pool downstream of that sheet splicer, which tension roll is provided for the purpose of feeding the running sheet without changing the speed of the downstream machine, an accelerating roll for stopping a running old sheet and accelerating the new sheet upstream of the dancer roll section and downstream of the sheet splicer, and a guide roll provided downstream of the dancer roll section and upstream of the downstream machine for feeding the sheet coming from the dancer roll section to the downstream machine in the prior art, is improved. The improvements reside in that when a rotational speed of the accelerating roll is represented by -N 2 , a rotational speed of the guide roll is represented by +N 3 , and a rotational speed of a drive shaft for moving the tension roll in the dancer roll section is represented by N 1 , the drive shaft is driven so as to fulfil the relation of ##EQU1## and thereby variation of the tension in the sheet applied to the tension roll accompanying the variation of the rotational speed of the accelerating roll can be made zero.\n \n BACKGROUND OF THE INVENTION\n 1. Field of the Invention\n The present invention relates to a splicing system, which is applicable to a control section for a dancer roll moving speed of a corrugate machine, a printing machine provided with an intermittent feeding device of a continuous sheet, a dancer roll section in a winder, and the like.\n 2. Description of the Prior Art\n A general construction of one example of a splicing system for use in a corrugate machine in the prior art is shown in FIGS. 4 and 5. Principal components of the illustrated apparatus are a raw material sheet feeder section 17, a sheet splicer section 3 and a dancer roll section 1. The raw material sheet feeder 17 is a device, in which a rolled sheet 18 consisting of a raw material sheet is rotatably supported via a shaft by a mill roll stand 15 and the sheet is successively rewound and fed in accordance with a necessary feed rate for manufacturing a corrugated cardboard sheet. The subsequent sheet splicer 3 is a device, in which in the case of order change or in the case where an old sheet 18 has been used up, a continuous sheet is formed by connecting the old sheet 18 to a new sheet 18'. The dancer roll section 1 is a section operable in such manner that since the splicing work is carried out while the feeding of the raw material sheet is kept stopped, a length of raw material sheet spent during that splicing work and to be supplemented later is preliminarily stored in the section so that the corrugated cardboard sheet can be manufactured continuously.\n Now description will be made briefly on the method (procedure) for splicing. At first, a tip end of a new sheet 2' paid out of a rolled sheet 18' on a mill roll stand 15, has a double-face adhesive tape 19 applied onto its surface after a cutting treatment, its back surface is sucked and held by a press-adhesion bar 20', and stands by under the condition shown in FIG. 5. On the other hand, with regard to the running old sheet 2, an accelerating roll 4 is decelerated by carrying out speed control of a motor 16, the sheet feeding speed is reduced by a braking action of a press roll 24 which pinches the sheet 2 jointly with the accelerating roll 4, further in a sheet stopper section 21 the sheet 2 is pinched by paired bars to be perfectly stopped, and then the stopped old sheet is spliced with the new sheet 2' via the double-face adhesive tape 19 by means of the press-adhesion bar 20'. The thus spliced sheet is pulled by the pinching rotation of the acceleration roll 4 and the press roll 24, and is fed to the dancer roll section 1. After predetermined acceleration, the acceleration roll 4 feeds the sheet to the dancer roll section 1 at a somewhat faster speed than the rate of ejecting the sheet from the dancer roll section 1 and consuming it at the next step of the process, and thus it functions to supplement the stocked amount of sheet that was consumed during the splicing operation. It is to be noted that in FIGS. 4(a) and 4(b), a motor 23 always continues to rotate at a predetermined speed for moving a pair of bearings 14 for a tension roll 5 connected to chains 13 at one location via a powder clutch 11 and sprockets 12, and thereby a proper tension is applied to the sheet being ejected. In the above-mentioned powder clutch 11 which is one kind of electromagnetic disc clutches, finely crushed dry magnetic particles are filled in the space between clutch elements, and a predetermined torque can be set by regulating a current flowing through the powder. It can operate also as a safety device such that in the event that an excessively large torque has been exerted upon the clutch elements, they would slip relative to each other and absorb the exerted torque.\n The splicing system in the prior art is constructed and operates in the above-described manner, hence upon sheet splicing work, in the event that the accelerating roll 4 and the press roll 24 have been momentarily decelerated or stopped, as the sheet speed for ejecting the sheet from the dancer roll section 1 to the next step of the process is a constant speed, the tension roll 5 would be pulled back against the inertia of the dancer roll section 1 and the tension roll 5, and so, abrupt change of the sheet tension would appear in the running sheet as shown in FIG. 3(c). On the contrary, after the sheet splicing work, as the feed speed of the sheet 2 is accelerated by the acceleration of the accelerating roll 4, it is necessary to decelerate the moving speed of the tension roll 5 in the pull-back direction, that is to accelerate the moving speed in the normal direction. However, this system had structural shortcomings that if this deceleration (i.e., acceleration in the normal direction) is slower than the acceleration of the sheet 2, the sheet 2 would slacken, while if the feed speed of the sheet 2 is insufficient, the dancer roll would continuously run in the pull-back direction and would strike against a limit stopper, resulting in break of the sheet 2.\n In summary, in the above-described sheet splicing system in the prior art, since the splicing between new and old sheets is carried out in the course when a corrugated cardboard sheet is being manufactured successively, upon the splicing work it is necessary to carry out the work while stopping feed of the sheet for a predetermined period of time. While the section having the function of supplementing the difference between the continuous consumption of the sheet on the demand side and the actually fed length of the sheet on the feed side during the stoppage, is the dancer roll section 1, upon splicing as the feed of the sheet is momentarily braked and stopped, the tension in the running sheet would rise abruptly as shown in FIG. 3(A) relating to the prior art, due to the inertia of the tension roll 5 in the dancer roll section 1. In addition, there were shortcomings that after the splicing, sagging was produced in the sheet or the tension in the sheet became extraordinarily high due to unbalance between the feed speed of the sheet and the moving speed of the tension roll 5. Consequently, the prior art system involved various problems that many troubles such as breaking, deformation and instability of running of the sheet were generated.\n SUMMARY OF THE INVENTION\n It is therefore one object of the present invention to provide an improved splicing system, which is free from the above-mentioned shortcomings inherent to the splicing system in the prior art.\n According to one feature of the present invention, there is provided a splicing system for paying out a rolled sheet and continuously feeding a sheet to a downstream machine, of the type that the system includes a sheet splicer for stopping a running sheet and splicing a tip end of another new sheet therewith, a tension roll in a dancer roll section for forming a sheet pool downstream of the sheet splicer, which tension roll is provided for the purpose of feeding the running sheet without changing the speed of the downstream machine, an accelerating roll for stopping a running old sheet and accelerating the new sheet upstream of the dancer roll section and downstream of the sheet splicer, and a guide roll provided downstream of the dancer roll section and upstream of the downstream machine for feeding the sheet coming from the dancer roll section to the downstream machine, in which system when a rotational speed of the accelerating roll is represented by -N2, a rotational speed of the guide roll is represented by +N3, and a rotational speed of a drive shaft for moving the tension roll in the dancer roll section is represented by N1, the drive shaft is driven so as to fulfil the relation of ##EQU2## and thereby variation of the tension in the sheet applied to the tension roll accompanying the variation of the rotational speed of the accelerating roll can be made zero.\n According to the present invention, owing to the above-described construction of the splicing system, the feed speed of the sheet delivered through the dancer roll section to a single facer or a double facer in the next step of the process is a speed corresponding to a manufacturing speed of a corrugated cardboard sheet. The guide roll continues to rotate at a speed corresponding to the manufacturing speed of the corrugated cardboard sheet, the rotational speed of the accelerating roll is maintained nearly equal to the rotational speed of the guide roll, and so, feeding of the sheet is effected with the tension roll positioned nearly at a fixed location. In the sheet splicing work, when the rotational speed of the accelerating roll has been decelerated and stopped by controlling the speed of the accelerating motor and thereby feed of the raw material sheet from the mill roll stand has been stopped, the rotational speed (-N2) of the accelerating roll becomes zero, hence from the relation of ##EQU3## the rotational speed N1 of the drive shaft for moving the tension roll in the dancer roll section becomes ##EQU4## and therefore, the tension roll moves at a speed of 1/2 times the sheet feed speed in the direction for reducing the sheet pool, so that the sheet pooled in the dancer roll section can be released without being accompanied by variation of the tension.\n On the other hand, in the case where the sheet splicing has been finished and the sheet pooled in the dancer roll section is supplemented by accelerating the speed of the accelerating roll, also the tension roll moves in the opposite direction to that described above without generating variation of the tension in the sheet nor sagging of the sheet.\n The above-mentioned and other objects, features and advantages of the present invention will become more apparent by reference to the following description of one preferred embodiment of the present invention taken in conjunction with the accompanying drawings.\n \n \n BRIEF DESCRIPTION OF THE DRAWINGS\n In the accompanying drawings:\n FIG. 1(a) is a plan view of a splicing system according to one preferred embodiment of the present invention;\n FIG. 1(b) is a side view of the same;\n FIG. 2 is a cross-section front view of differential speed reduction gears employed in the system shown in FIG. 1;\n FIG. 3(a) is a schematic view showing preset rotational speeds of the respective portions in the illustrated embodiment;\n FIG. 3(b) is a diagram showing a running behavior of a sheet and variations of a tension in the sheet upon splicing in the splicing system according to the present invention;\n FIG. 3(c) is a diagram showing modes of variation of a tension in a sheet in the system known in the prior art and in the system according to the present invention;\n FIG. 4(a) is a plan view of a splicing system in the prior art;\n FIG. 4(b) is a side view of the same; and\n FIG. 5 is a detailed partial side view showing an essential part in the system shown in FIG. 4(b).\n \n \n DESCRIPTION OF THE PREFERRED EMBODIMENT:\n In the following, the present invention will be described in more detail in connection to one preferred embodiment of the invention illustrated in FIGS. 1, 2 and 3(a). It is to be noted that the respective rotational speeds N1, (-N2) and N3 are defined so that the rotational speed in the direction of increasing the amount of the sheet stock in the dancer roll section 1 may be positive and that in the direction of decreasing the stock amount may be negative.\n Now, in the dancer roll section 1, the route of a continuous sheet 2 passing through a sheet splicer not shown and running around an accelerating roll 4, a tension roll 5 and a delivery section guide roll 6, respectively, and the capability of stocking a necessary amount of sheet to be consumed during a splicing operation, are the same as those employed in the prior art system shown in FIG. 4. However, the preferred embodiment of the present invention illustrated in FIG. 1 has a characteristic feature in that drive for the accelerating roll 4, movement of the tension roll 5 in the dancer roll section 1 and drive for the delivery section guide roll 6 are mutually interlocked via differential speed reduction gears 7 to perform effective control.\n The differential speed reduction gears 7 employed in one preferred embodiment of the present invention consists of a planetary gear mechanism as shown in FIG. 2, which comprises three rotary elements of a shaft 8, a flange 9 and a casing 10. In addition, in FIG. 2 reference characters A and D designate sun gears and reference characters B and C designate planet gears. As is well known by those skilled in the art, the relation among the rotational speeds of the respective rotary elements that is, the shaft 8, the flange 9 and the casing 10 is represented by ##EQU5## where symbol N1 represents the rotational speed of the shaft 8, symbol -N2 /2 represents the rotational speed of the flange 9, and symbol N3 /2 represents the rotational speed of the casing 10.\n Explaining now the construction and function of the dancer roll section 1, the dancer roll section 1 makes use of the differential reduction gears 7 which operate in the above-described manner, by rotating the shaft 8 the bearings 14 pivotably supporting the tension roll 5 in the dancer roll section 1 is reciprocated via a powder clutch 11, sprockets 12 and chains 13, the casing 10 is rotated at a rotational speed of N3 /2 by transmitting the rotation (at the rotational speed of N3) of the sheet delivery section guide roll 6 thereto via power transmission means, and the flange 9 is rotated at a rotational speed of -N2 /2 by transmitting the rotation (at the rotational speed of -N2) of the accelerating roll 4 that is driven by an accelerating motor 16 for controlling a sheet feeding state (deceleration, stoppage or acceleration) from a mill roll stand not shown, via power transmission means.\n The running behavior of the sheet in the above-described system is shown in FIG. 3(b), in which the feed speed of the sheet delivered from the mill roll stand to the dancer roll section 1 is normally coincides with the circumferential speed of the accelerating roll 4 (only upon splicing, a press roll 24 is pressed against the accelerating roll 4 by the action of a cylinder 25), and by making that sheet feed speed equal to or a little faster than the ejection speed of the sheet delivered from the guide roll 6 in the dancer roll section, the position of the tension roll 5 is set to be stopped or to be moved very slowly to the left as seen in FIG. 3(a).\n In addition, the ejection speed of the sheet delivered through the dancer roll section 1 to a single facer or a double facer in the next step of the process is a speed corresponding to the manufacturing speed of the corrugated cardboard sheet, and so, the casing 10 of the differential speed reduction gears 7 would continue to rotate at a rotational speed corresponding to the manufacturing speed of the corrugated cardboard sheet.\n Accordingly upon sheet splicing, when the rotational speed of the accelerating roll 4 has been decelerated and stopped via the accelerating motor 16 and thus the feed of the raw material sheet from the mill roll stand has been stopped, the shaft 8 would rotate in the reverse direction, and the tension roll 5 would move rightwards as viewed in FIG. 3(a). The moving speed of the tension roll 5 at that time would be ##EQU6## in view of the relation of ##EQU7## that is, the moving speed would become 1/2 times the sheet ejection speed, and so, the sheet pooled in the dancer roll section 1 can be released without being accompanied by variation of the tension in the sheet (Since the tension roll is moved rightwards at the speed of N3 /2, that is, at the speed equal to half times the sheet speed N3, variation of the tension in the sheet is none at all.). Owing to the above-mentioned capability, abrupt increase of the tension in the sheet caused by the innertia of the tension roll 5 which was a shortcoming of the prior art system, can be eliminated, and a constant tension can be maintained.\n After finishment of the splicing work, the circumferential speed of the accelerating roll 4 is increased via the accelerating motor 16, and the sheet feed speed from the mill roll stand 15 to the dancer roll section 1 is accelerated. Until the sheet feed speed coincide with the sheet ejection speed, according to the relation of ##EQU8## the rightward moving speed of the tension roll 5 in the dancer roll section 1 is reduced by the amount corresponding to the increment of the sheet feed speed accelerated by the accelerating roll 4, and when the sheet feed speed and the sheet ejection speed coincides, the moving speed of the tension roll 5 becomes zero. Furthermore, the accelerating roll 4 is driven a little faster than the sheet ejection speed N3, thus the tension roll 5 in the dancer roll section 1 is moved leftwards at the speed of ##EQU9## and thereafter, a sheet length corresponding to the area of the hatched portion in FIG. 3(b) becomes an additionally supplemented amount of the sheet stock in the dancer roll section 1. It is to be noted that after the sheet capacity that can be stocked in the dancer roll section 1 has been completely supplemented, the accelerating roll 4 is brought into a freely rotatable state (i.e. an idling state), and the movement of the tension roll 5 is stopped by making the sheet feed speed and the sheet ejection speed coinside with each other.\n In addition, as described already in connection to the prior art system in FIG. 4, the powder clutch 11 directly coupled to the shaft 8 can delicately control the tension in the delivered sheet by regulating the action force for moving the tension roll 5. In other words, the tension in the sheet delivered to a single-facer or a double-facer in the next step of the process is generated by a tension applied at the delivery section and a braking force in the inverse direction produced by a braking action at the accelerating roll, and upon extraordinary increase of the sheet tension, the clutch 11 is made to slip. Thus, this system operates to control the sheet tension so that it can be maintained always within a predetermined range.\n It is to be noted that the present invention should not be limited only to the above-described embodiment, but various changes and modifications in design can be made without departing from the spirit of the invention. For instance, when the speed on the sheet ejection side is represented by N3, the speed on the deceleration/acceleration side is represented by -N2, and the moving speed of the tension roll in the dancer roll section located therebetween is represented by N1, the respective speed N1, -N2 and N3 can be controlled by individual motors so as to fulfil the relation of ##EQU10## In other words, by driving the tension roll in the dancer roll section at a moving speed N1 which fulfils the relation of ##EQU11## an excessive sheet tension and sagging of the sheet can be eliminated. While the above explanation was made for the example of a single dancer (a single tension roll is provided), in the case of a double dancer (two tension rolls are provided), the same effect can be obtained by driving the tension rolls so as to fulfil the relation of ##EQU12##\n Since the splicing system according to the present invention is constructed as described above, in the event that upon a sheet splicing work, the rotational speed of the accelerating roll has been reduced and running of the old sheet has been stopped, the tension roll in the dancer roll section can be moved towards the sheet ejection side so as to slacken the sheet tension in response to the deceleration and stoppage, while upon acceleration of the new sheet after the splicing, the moving speed of the tension roll can be reduced, stopped and reversed (so as to move in the opposite direction to the sheet ejection side), and thereby abrupt increase and decrease of the sheet tension generated upon every splicing work as described above, can be mitigated. Thereby, the problems to be resolved in the prior art such as breaking, deformation and running instability of the sheet, can be resolved. Accordingly, degradation of a productivity accompanying generation of troubles such as sheet breaking or the like, can be eliminated, moreover, variation of the tension is eliminated, and manufacturing of high-quality corrugated cardboard sheets is possible.\n \n \n What is claimed is:\n \n 1. A splicing system for paying out a rolled sheet and continuously feeding a sheet to a downstream machine, which includes a sheet splicer for stopping a running sheet and splicing a tip end of another new sheet therewith, a tension roll in a dancer roll section for forming a sheet pool downstream of said sheet splicer, which tension roll is provided for the purpose of feeding the running sheet without changing the speed of said downstream machine, an accelerating roll for stopping a running old sheet and accelerating the new sheet upstream of said dancer roll section and downstream of said sheet splicer, and a guide roll provided downstream of said dancer roll section and upstream of said downstream machine for feeding the sheet coming from said dancer roll section to the downstream machine; characterized in that when a rotational speed of said accelerating roll is represented by -N2, a rotational speed of said guide roll is represented by +N3, and a rotational speed of a drive shaft for moving the tension roll in said dancer roll section is represented by N1, said drive shaft is driven so as to fulfil the relation of ##EQU13## and thereby variation of the tension in the sheet applied to said tension roll accompanying the variation of the rotational speed of said accelerating roll can be made zero, wherein the rotational speed of the accelerating roll is set to be somewhat faster than the rotational speed of the guide roll, and thereby the tension roll in the dancer roll section can be moved in the direction for increasing the pooled amount of the sheet, according to the rotational speed of ##EQU14## and wherein the drive shaft for moving the tension roll in said dancer roll section is coupled to said guide roll and said accelerating roll via planetary gears.\n \n \n 2. A splicing system for paying out a rolled sheet and continuously feeding a sheet to a downstream machine, which includes a sheet splicer for stopping a running sheet and splicing a tip end of another new sheet therewith, a tension roll in a dancer roll section for forming a sheet pool downstream of said sheet splicer, which tension roll is provided for the purpose of feeding the running sheet without changing the speed of said downstream machine, an accelerating roll for stopping a running old sheet and accelerating the new sheet upstream of said dancer roll section and downstream of said sheet splicer, and a guide roll provided downstream of said dancer roll section and upstream of said downstream machine for feeding the sheet coming from said dancer roll section to the downstream machine; characterized in that when a rotational speed of said accelerating roll is represented by -N2, a rotational speed of said guide roll is represented by +N3, and a rotational speed of a drive shaft for moving the tension roll in said dancer roll section is represented by N1, said drive shaft is driven so as to fulfil the relation of ##EQU15## and thereby variation of the tension in the sheet applied to said tension roll accompanying the variation of the rotational speed of said accelerating roll can be made zero, wherein the drive shaft for moving the tension roll in said dancer roll section is coupled to said guide roll and said accelerating roll via planetary gears.\n \n ", + "added": "1989-01-25", + "source": "Google Patents Public Data", + "metadata": { + "license": "Creative Commons - Attribution - https://creativecommons.org/licenses/by/4.0/", + "language": "en", + "publication_date": "1990-05-29" + } +} +{ + "id": "US-97554293-A", + "text": "Correlated photon pair optical communications system\n\nABSTRACT\n\nAn optical communications system (10) comprises a transmitter (12) and a receiver (14). A source (16) of correlated pairs of photons of conjugate energies provides first and second photon beams (38, 36). The first photon beam (38) passes through a modulated filter (50) to which a communications signal (52) is applied. A variable spectrum beam (54) is produced which is converted to a timing signal (68) of macroscopic optical pulses (66). The second photon beam (36) and timing signal (68) are transmitted to the receiver (14). The received timing signal (84) is converted to a series of electrical timing pulses (90). The received second photon beam (82) passes through an unmodulated filter (94) matched to the modulated filter (50) when the signal (52) is not applied. The unmodulated filter splits the beam (82) into two conjugate spectra photon beams (96, 98) which are then converted to first and second series of electrical pulses (108, 110) respectively. The pulses (90, 108, 110) enter a coincidence counter (92) which records coincidences between the timing pulses (90) and the first series of pulses (108) and between the timing pulses (90) and the second series of pulses (110). Two coincidence rates are obtained and subtraction of one from the other yields an output communications signal (112).\n \n BACKGROUND OF THE INVENTION\n 1Field of the Invention\n The invention relates to an optical communications system, and more particularly to a system in which signals are transmitted in the form of coincidences between optical beams.\n 2. Discussion of Prior Art\n Optical communications systems based on coincident photon pairs have been described previously, for instance by Hong, Friberg and Mandel in Applied Optics Vol. 24, No 22, Pages 3877-3882. The system they describe employs a non-linear crystal to produce simultaneous photon pairs by non-degenerate parametric downconversion of an input pump beam. These photon pairs form two beams of correlated photons, each beam including one photon of each pair. The beams are transmitted separately and in a receiver are detected separately. When a correlated photon pair is detected, one in each beam, a coincidence is recorded. A digital signal is transmitted by direct modulation of the input pump beam, that is by switching it on and off. The off periods in both beams are filled in using light which is spectrally similar to the downconverted photon pairs. The fill-in light is not, however, correlated, and therefore when it is detected in the receiver significant numbers of coincidences are not recorded. Thus periods of coincidences in the receiver correspond to binary one digits and periods of no coincidences (above noise) correspond to binary zero digits.\n The system described has the advantage that the use of coincident detection allows discrimination against background noise to be achieved. Communication may therefore be achieved with relatively few photons and where the signal photons would otherwise be lost in the noise in each of the two beams.\n The system is also relatively secure from interception due to the fill-in light. If only one beam is intercepted, and the light used to fill in is sufficiently well matched to the signal photons, then the signal cannot be decoded. However, matching the spectrum, intensity and statistical properties of the downconverted photons is difficult in practice. Consequently, detailed analysis of the properties of one beam would, in many cases enable the signal to be decoded. In addition, if both beams are intercepted the signal may be decoded by simple coincidence counting. The system is not therefore very secure.\n A similar system employing time modulation in place of direct modulation has also been described. This time modulation system has two pulsed correlated photon beams. A digital signal is transmitted by time modulation of one of the two correlated beams. That is a variable delay is introduced into one of the pulsed beams. As with the direct modulation system described above, if one of the two beams is intercepted the signal cannot be decoded simply. However, careful analysis of statistics of time delays between pulses would enable some modulation to be detected. If the delays used are short compared to the period between pulses of the unmodulated beam, then the modulation detected by such analysis would be minimal. If both beams are intercepted, then as for the direct modulation system, simple coincidence counting will decode the signal. This system also, therefore, is not very secure.\n Both of the prior art systems described above also suffer from the severe disadvantage of quadratic reduction in signal to noise as a function of loss in both channels. This puts very real constraints on the practical applications of the systems, particularly limiting the distances over which they may be used.\n SUMMARY OF THE INVENTION\n It is an object of the present invention to provide an improved optical communications system.\n The present invention provides an optical communications system comprising:\n transmitter including a source of correlated pairs of photons with conjugate energies in first and second photon beam channels respectively, and\n a receiver including:\n (i) coincidence counting means arranged to count coincidences between received photons, and\n (ii) discriminating means responsive to variation in coincidence counting rate and arranged to provide a communications signal,\n characterised in that:\n the transmitter includes:\n (a) transmitter filtering means in the first photon beam channel having modulatable spectral dispersion characteristics responsive to a signal input, and\n (b) means responsive to the transmitter filtering means output for transmitting a timing signal, and the receiver includes receiver filtering means having spectral dispersion characteristics conjugate to those of the transmitter filtering means in the absence of signal input and arranged to separate received photons into differing receiver channels on the basis of their spectral characteristics.\n The invention provides the advantage that even if both the timing signal and photons from the second transmitter photon beam channel are intercepted during transmission the signal cannot be decoded. The invention therefore offers greater security of communication than in the prior art.\n The invention also provides the advantage that communication may be achieved in relatively high levels of background light, for instance when the received signal intensity is two orders of magnitude less than the received background light intensity. This enables the invention to be used in unfavourable conditions. Alternatively the signal beam may be disguised, to enhance security, by mixing in spurious light thus making it more difficult to identify the signal beam.\n An additional advantage of the invention over prior art coincidence counting systems is improved signal/noise characteristics. The invention suffers only linear reduction in signal/noise ratio as a function of of signal whilst prior art systems suffer quadratic reduction.\n In one embodiment, the receiver filtering means has two filter channels with spectrally conjugate filter characteristics. The receiver filtering means therefore provides two photon beams with conjugate spectra. The coincidence counting means is arranged to count coincidences between the timing signal and the two conjugate spectrum beams separately. Thus two coincidence rates are obtained and one is subtracted from the other in order to obtain the communications signal. Although the use of two filter channels does not add any new information, it increases the signal/noise ratio, and is thus advantageous.\n Such an embodiment may be arranged for the transmission of a digital communications signal. In this case the transmitter filtering means is switched between two conjugate spectral dispersion characteristics in response to the digital signal.\n Such an embodiment may be provided with transmitter and receiver filtering means in the form of respective Mach Zehnder interferometers. The transmitter filtering means may include an electro-optic modulator in one interferometer arm to which the communications signal is applied. The receiver filtering means Mach Zehnder interferometer is matched to that in the transmitter, ie the filtering means have equivalent optical path lengths when the electro-optic modulator is inactive.\n The invention may be arranged for the communication of information at the rate of one bit per photon pair. In such an embodiment modulation of the transmitter filtering means is arranged to produce substantially one hundred per cent modulation of the two coincidence rates measured by the coincidence counter. This embodiment may include a transmitter filtering means with modulatable spectral dispersion characteristics. The transmitter and receiver filtering means may each be arranged for modulation between at least three respective predetermined phase differences in response to respective input signals. At least one of these combinations of phase differences is such as to provide substantially are one hundred per cent modulation of the two measured coincidence rates. In such an embodiment the transmitter and receiver filtering means may each be Mach Zehnder interferometers with an electro-optic modulation in one arm.\n The invention may be arranged such that the timing signal and second photon beam are combined for transmission as a single beam. They may be separated in the receiver by means of a polarising beam splitter or dichroic beam splitter as appropriate.\n The invention may also be arranged such that the timing signal and second photon beam are transmitted to the receiver through free space. Alternatively, they may be transmitted to the receiver via a fibre optic.\n The invention may be provided with a source of correlated photon pairs comprising a pump laser, a non-linear crystal and two apertures. Alternatively, the source of correlated photon pairs may be a cascade atomic source.\n \n \n BRIEF DESCRIPTION OF THE DRAWINGS\n Embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings in which:\n FIG. 1 schematically illustrates an optical communications system of the invention;\n FIG. 2 schematically illustrates a source of correlated photon pairs used in the FIG. 1 system;\n FIG. 3 schematically illustrates a coincidence counter used in the FIG. 1 system;\n FIG. 4 schematically illustrates a modulated filter used in the FIG. 1 system;\n FIG. 5a and 5b graphically illustrate the cosinusoidal transmission characteristics of the modulated filter of FIG. 4;\n FIG. 6 schematically illustrates an unmodulated filter used in the FIG. 1 system;\n FIG. 7 illustrates graphically the relative timing of operation of the communications system of FIG. 1;\n FIG. 8 graphically illustrates the variation of coincidence rate with path length difference; and\n FIG. 9 schematically illustrates an alternative optical communications system of the invention.\n \n \n DETAILED DISCUSSIONS OF PREFERRED EMBODIMENTS\n Referring to FIG. 1, an optical communications system 10 of the invention is illustrated schematically. The system 10 has two main parts, a transmitter 12 and a receiver 14.\n Referring now also to FIG. 2, a source 16 of correlated pairs of photons with conjugate energies for use in the transmitter 12 is illustrated schematically. The source 16 consists of a short wavelength laser 18, a non-linear crystal 20 and two apertures 32, 34. In this embodiment the laser 18 is a 100 mW krypton ion laser with a wavelength \u03bbo =413.4 nm and the crystal 20 is lithium iodate. The laser 18 emits photons 22 of wavelength \u03bbo which are incident on the crystal 20. In the crystal 20 the photons 22 undergo non-degenerate downconversion as described by Burnham and Weinburg in Physical Review Letters 25 (1970) page 84, and by Mollow in Physics Review A8 (1973) page 2684. Each photon 22 produces first and second downconverted photons 24, 26 with wavelengths \u03bb1 and \u03bb2 respectively, at angles \u03b81 and \u03b82 respectively to the input photon direction.\n The downconverted photons 24, 26 are a correlated pair. They are emitted substantially simulataneously and have conjugate energies; that is their energies must sum to the energy of the photon 22. Thus if the energy of the first photon 24 of a pair is known, that of the second photon 26 is also known, and vice versa. This follows from the conservation of energy and momentum which is observed when the photon pair 24, 26 is produced. The following relationships apply:\n \n \u03c9.sub.o =\u03c9.sub.1 +\u03c9.sub.2 (1) ##EQU1## where \u03c9.sub.o, \u03c9.sub.1 and \u03c9.sub.2 are the angular frequencies of the photons 22, 24, 26 respectively. There are many solutions to equations 1 to 3 and therefore many possible angles \u03b8.sub.1, \u03b8.sub.2 for the downconverted photons 24, 26.\n \n The downconverted photons 24, 26 form first and second mixed energy dispersed beams 28, 30. The two apertures 32, 34 select first and second beams 36, 38 of conjugate photons 40, 42; that is they select pairs of photons 40, 42 which correspond to one solution of equations 1 to 3.\n The apertures 32, 34 have equal finite widths giving the photons 40, 42 like frequency bandwidths of 2\u03b4\u03c9. The aperture 32 selects photons 40 with an angular frequency \u03c91 \u00b1\u03b4\u03c9 and the aperture 34 selects photons 42 with an angular frequency \u03c92 \u00b1\u03b4\u03c9. In this embodiment the symmetrical solution of \u03c91 =\u03c92 =\u03c9o /2 has been implemented by appropriate aperture positioning. The apertures 32, 34 accept photons 40, 42 at an angle of \u03b81 =\u03b82 =14.5\u00b0 corresponding to \u03bb1 =\u03bb2 =826.8 nm with a bandwidth of 5 nm.\n The two beams 36, 38 have a low light level. The first beam 36 passes via a mirror 44 and a lens 46 to a polarising beam splitter 48. The second beam 38 passes to a modulated filter 50 which is modulated by an input digital signal 52. The operation of the modulated filter 50 will be described in more detail later.\n The modulated filter 50 generates an output beam 54 of photons 56 which passes to an actively quenched photon counting avalanche photodiode 58. A suitable photodiode is described by Brown, Jones, Rarity and Ridley in Applied Optics, Vol 26, pages 2383-2389. The photodiode 58 produces a respective electrical pulse 60 in response to each photon 56 detected. Each electrical pulse 60 passes to a laser diode modulator 62 controlling a laser diode 64. These are standard communications grade components, and in this embodiment the laser diode 64 has an output wavelength of 1.5 \u03bcm.\n The laser diode 64 produces a respective optical pulse 66 for each electrical pulse 60. Thus the modulated low light level beam 54 has been converted to a macroscopic light beam 68 in which each laser output pulse 66 corresponds to a respective photon 56. The beam 68 constitutes a timing signal. It passes via a lens 70 to the polarising beam splitter 48.\n The polarising beam splitter 48 combines the macroscopic light beam 68 and first low light level beam 36 into a combined beam 72. The combined beam 72 is transmitted through free space to the remote receiver 14 as indicated by a discontinuity 74.\n The combined beam 72 enters the receiver 14 through a collimating lens 76. The beam 72 then passes to a dichroic beamsplitter 78 which separates it into a received macroscopic light beam 80 and a received low light level beam 82. The received macroscopic light beam 80 consists of optical pulses 84 of wavelength 1.5 \u03bcm and the received low light level beam 82 consists of photons 86 of wavelength 826 nm. The macroscopic light beam 80 passes to a communications grade detector 88 which produces an electrical pulse 90 for each optical pulse 84. The electrical pulses 90 pass to a multichannel coincidence counter 92, described in more detail later.\n The received low light level beam 82 passes to an unmodulated filter 94, matched to the modulated filter 50 in the transmitter. The unmodulated filter 94 will be described in more detail later. It generates first and second output low light level beams 96, 98 of photons indicated by 100, 102 respectively. The beams 96, 98 pass to two actively quenched photon counting avalanche photodiodes 104, 106 respectively. The photodiode 104 produces a respective electrical pulse 108 for each photon 100 detected. Likewise the photodiode 106 produces a respective electrical pulse 110 for each photon 102 detected. The electrical pulses 108, 110 pass to the coincidence counter 92.\n Referring now to FIG. 3, the coincidence counter 92 is illustrated schematically. The counter 92 includes first and second coincidence gates 120, 122 and a digital subtraction circuit 124. Pulses 90 and 108 enter the first coincidence gate 120 and for each coincidence counted a pulse 126 is output from the gate 120. Periods of high coincidence rate between pulses 90 and 108 indicate a binary zero level in the digital signal 52. Pulses 90 and 110 enter the second coincidence gate 122 and for each coincidence counted a pulse 128 is output from the gate 122. Periods of high coincidence rate between pulses 90 and 110 indicate a binary one level in the digital signal 52. The pulses 126 and 128 pass to the digital subtraction circuit 124. The circuit 124 measures the respective rates of pulses 126 and 128 and subtracts the rate of pulses 126 from the rate of pulses 128. A discrimination level is set at zero, such that when the subtracted coincidence rates are positive a binary one digit is produced, and when the subtracted coincidence rates are negative a binary zero digit is produced. This generates a decoded digital output signal 112.\n Referring now to FIG. 4, a modulated filter 50 as used in the transmitter 12 is illustrated schematically, parts common to FIG. 1 being like referenced. The modulated filter 50 is Mach-Zehnder (MZ) Interferometer with unequal path lengths. The MZ interferometer 50 has input and output beam splitters 150, 152. A first path 154 through the MZ interferometer 50 is that directly between the beam splitters 150, 152, and is of length L1. A second MZ interferometer path 156 extends to the output beam splitter 152 via two mirrors 158, 160, and is of length L2. The second path 156 is longer than the first by a length (L2 -L1)=P, the path length difference. The second path 156 incorporates an electro-optic phase modulator 162 activated by a modulator driver 164. The input digital signal 52 is converted by the modulator driver 164 into a control signal for the modulator 162.\n The electro-optic modulator 162 is used to alter the optical length L2 of the second path 156. The digital signal 52 has binary 0 and 1 levels 52a and 52b respectively. When it is 0 the second path length remains L2. When the digital signal 52 is 1, the second path length is increased to L2 +\u03b4x. Thus the path length difference becomes P+\u03b4x.\n The photons 42 enter the modulated filter at 38. They are divided into parts 42a and 42b taking paths 154 and 156 respectively. At the output beam splitter 152, each of the parts' 42a and 42b is partially reflected and partially transmitted. In consequence, the modulated low light level beam 54 is the sum of the transmitted component of part 42a and the reflected component of part 42b. A second modulated low light level beam 168 is also formed, by partial reflection of part 42a and partial transmission of 42b. The second beam 168 is however not used in this example. The MZ interferometer 50 acts as a cosinusoidal filter, with first and second output intensity functions I1 (\u03c9) and I2 (\u03c9) given by:\n \n I.sub.1 (\u03c9)=1.sub.38 (\u03c9)[1+cos (\u03c9P/c)]/2 (4)\n \n \n .sub.2 (\u03c9)=I.sub.38 (\u03c9)[1-cos (\u03c9P/c)]/2 (5)\n \n where I38 (\u03c9) is the intensity of beam 38 as a function of angular frequency \u03c9, P is the previously defined path length difference and c is the speed of light. The path length difference P is arranged to be smaller than the coherence length of the laser 18, and larger than the coherence length of the beams 38, 36.\n Referring now also to FIG. 5, the transmission characteristics of the modulated filter 50 are illustrated graphically in the form of first and second output intensity functions I1 (\u03c9) and I2 (\u03c9). They transmit equal total intensity over the bandwidth 2\u03b4\u03c9, but exhibit conjugate spectral form. In other words, these functions are mirror images of each other about the central frequency \u03c91. When the digital signal 52 is binary zero and the path length difference is P, then the beam 54 has the output intensity function given by I1 (\u03c9), illustrated in FIG. 5a). The beam 168 has the conjugate spectral output intensity function I2 (\u03c9) illustrated in FIG. 5b). In practice the intensity functions I1 (\u03c9) and I2 (\u03c9) will have many more fringes over the frequency bandwidth 2\u03b4\u03c9 than shown in FIG. 5, typically of the order of 100.\n The photons 42 have a frequency band \u03c91 \u00b1\u03b4\u03c9 with \u03c91 >>\u03b4\u03c9 and the change in the length of path 156, \u03b4x is arranged to be \u03b4x=\u03c0/\u03c91. Thus when the digital signal 52 is binary 1, and the path length difference is P+\u03b4x, the beam 54 has the output intensity function I2 (\u03c9) and the beam 168 has the function I1 (\u03c9). A change in path length of \u03b4x thus causes an exchange of output intensity functions I1 (\u03c9) and I2 (\u03c9) between the beams 54 and 168. Thus the beam 54 carries the digital signal 52 by switching between two alternative states of the transmission characteristics of the modulated filter 50. When the signal 52 is zero, the beam 54 has a frequency spectrum indicated by I1 (\u03c9); when the signal 52 is one, the beam 54 has a frequency spectrum indicated by I2 (\u03c9). Provided P\u03b4\u03c9/c>>1, the exchange of intensity functions I1 (\u03c9), I.sub. 2 (\u03c9) does not change the mean intensity of beam 54. The condition that P\u03b4\u03c9/c>>1 is satisfied when P is larger than the coherence length of the beams, 38, 36.\n Referring now also to FIG. 6, the unmodulated filter 94 used in the receiver 14 is illustrated schematically. Parts common to the modulated filter 50 are like referenced but with the addition of an asterisk. The unmodulated filter 94 is matched to the modulated filter 50 in the absence of communications signal modulation, ie. when it is quiescent. Thus the first path 154* is of length L1 and the second path 156* is of length L2, and the path length difference is given by (L2 -L1)=P. Since the unmodulated filter 94 is matched to the modulated filter 50 its filter function is also given by equations 4 and 5. Thus the beam 98 has an intensity function I1 (\u03c9) and the beam 96 has an intensity function I2 (\u03c9), each over the bandwidth of the pair photons 40, \u03c91 \u2213\u03b4\u03c9. The unmodulated filter 94 acts as a reference filter.\n Photon by photon energy matching is required between each correlated photon pair 40, 42. That is if a photon 42 has a particular angular frequency, given by \u03c9a, within the bandwidth \u03c91 \u2213\u03b4\u03c9 then the correlated photon 40 must have the conjugate angular frequency, given by \u03c9b, within the bandwidth \u03c91 \u2213\u03b4\u03c9, where \u03c9a +\u03c9b =\u03c9o. Thus if a photon 42, with frequency \u03c9a, passes through the modulated filter 50 when the beam 54 has intensity spectrum I1 (\u03c9) then the received correlated pair photon 86, with frequency \u03c9b, will pass through the unmodulated filter 94 into beam 96 which has the conjugate intensity spectrum I2 (\u03c9). Similarly when a photon 42 passes through the modulated filter 50 when the beam 54 has intensity spectrum I2 (\u03c9) then the received correlated pair photon 86 will pass through the unmodulated filter 94 into beam 98 which has the conjugate intensity spectrum I1 (\u03c9). In general the transmission characteristics of the unmodulated filter 94 are conjugate to those of the modulated filter 50 if the transmission characteristics of the unmodulated filter 94 giving rise to either beam 96 or beam 98 (but not both) are conjugate to those of the modulated filter 50 giving rise to beam 54 in the absence of a communications signal 52.\n Each transmitter filtered photon 56 gives rise (by virtue of elements 58 to 88) to an electrical pulse 90 passing to the coincidence counter 92. Each received filtered photon 100 in beam 96 results in an electrical pulse 108 passing to the coincidence counter 92. When there is a high coincidence rate between the electrical pulses 90 and 108 this indicates that the transmitter filtered photons 56 had the I1 (\u03c9) spectral form, and hence that the digital signal 52 is binary 0.\n Likewise when the transmitter filtered photons 56 have the I2 (\u03c9) spectral form, the correlated received photons 86 will have the I1 (\u03c9) spectral form, and consequently will leave the unmodulated filter 94 in beam 98. The photons 56 result in electrical pulses 90 and the photons 102 in beam 98 result in electrical pulses 110. The pulses 90 and 110 pass to the coincidence counter 94. When there is a high coincidence rate between the pulses 90 and 110 this indicates that the transmitter filtered photons 56 had the I2 (\u03c9) spectral form, and hence that the digital signal 52 is binary 1.\n Referring now to FIG. 7, a timing diagram for the system 10 is given. Amplitude is plotted against time in a series of graphs 200 to 216. The binary digital signal 52 to be transmitted is illustrated in the first graph 200. Graphs 202 to 210, and 214 and 216 show discrete electrical pulses as vertical lines. The second, third and fourth graphs 202-206 indicate the timing of photodetection pulses 90, 110 and 108 respectively input to the coincidence counter 92. The fifth graph 208 illustrates electrical pulses produced within the coincidence counter 92 on the occurrence of a coincidence between a pulse 90 and a pulse 110; the first six of these coincidences are indicated by dotted lines such as 209 extending from graph 204 to graph 208. Similarly the sixth graph 210 illustrates electrical pulses produced within the coincidence counter 92 on the occurrence of a coincidence between a pulse 90 and a pulse 108; the first four of these coincidences are indicated by dotted lines such as 211 extending from graph 202, through graph 206 to graph 210. Periods of high coincidence rate between electrical pulses 90 and 110 correspond to the signal 52 being the binary digit one. Similarly periods of high coincidence rate between electrical pulses 90 and 108 correspond to the signal 52 being the binary digit zero. Thus the output decoded digital signal 112 is obtained from subtraction of one of these coincidence rates from the other. The output decoded digital signal 112 is illustrated in graph 212.\n If the unmodulated filter 94 is characterised by a path length difference P', different to that (P) of the modulated filter 50 then the filter characteristics are changed. If the difference (P-P') is shorter than the coherence length of the downconverted photons 40, 42, that is |(P-P')\u03b4\u03c9|<<2\u03c0, the change over the bandwidth is small and there is negligible loss of signal 52. With difference (P-P') larger than the coherence length, that is |(P-P')\u03b4\u03c9|>>2\u03c0, the filters 50 and 94 move in and out of phase many times over the full optical bandwidth 2\u03b4\u03c9 and the signal 52 is lost. This situation is illustrated in the eighth and ninth graphs 214, 216 of FIG. 6, in which vertical lines represent electrical pulses produced in the coincidence counter 92 on the occurrence of coincidences between pulses 90 and 110 and between 90 and 108 respectively. Clearly there is no pattern to the coincidences counted. Coherence lengths of the correlated photon beams 36, 38 are small, typically less than 100 \u03bcm. In consequence, it is important to match the pathlength differences P and P' in the filters 50 and 94.\n The system may support a signal of particular bandwidth, this bandwidth being dependent on the coincidence rate Co practically achievable given the losses in transmission. Signal loss in the macroscopic pulse path may be made negligible since gain may be used. Therefore assuming no loss of pulses in the macroscopic pulse path we may write,\n \n C.sub.o =\u03b7.sub.T \u03b7.sub.R \u03b7.sub.tr r (6)\n \n where \u03b7T and \u03b7R are quantum efficiencies of collection and detection in the transmitter and receiver photon counting detectors 58, 104, 106 respectively, \u03b7tr is a lumped transmission efficiency through the low light level beam 36, 82, and r is the initial pair photon rate at the crystal 20. To maximise signal the coincidence rates between pulses 90 and 108, and 90 and 110, which are in antiphase, are both measured and subtracted. If the modulator 162 is arranged to introduce a \u03c0 phase difference then a difference coincidence rate modulation of Co /2 between binary 1 and binary 0 bits is ensured. If, for instance, we require 10 difference coincidences per bit, have \u03b7T =\u03b7R =10%, \u03b7tr =10% and a maximum baud rate of 10,000 bits per second, then a correlated pair photon rate of r=2\u00d7108 s-1 would be required. The accidental coincidence rate, B, neglecting background light and detector dark count, is given by\n \n B=\u03b7.sub.T \u03b7.sub.R \u03b7.sub.tr r.sup.2 t (7)\n \n where t is the coincidence gate width, defined as the maximum delay between the start of the first pulse and the start of the second pulse for which a coincidence will be recorded. For negligible accidental coincidence rate B= 3.9 required") + + +def process_datasets( + data_dir: str = r"data/uspto/", + limit: int = 0, + max_concurrency: int = 4, +) -> Iterator[dict]: + """ + This function `run_dataset` scans a dataset located in a directory, converts each file in the dataset to a desired + format using pandoc,and returns an iterable of dictionaries containing the converted data. + + Parameters: + - `data_dir` (str): The directory where the dataset is located. Default value is "./data/uspto/". + - `limit` (int): The maximum number of rows to convert. Default value is 0, which means convert all rows from all files in the dataset. + - `max_concurrency` (int): The maximum number of concurrent conversions to perform. Default value is 2. + + Returns: + - `Iterable[dict]`: An iterable of dictionaries containing the converted data from each file in the dataset. + + Note: + - The `data_dir` parameter should be a valid directory path ending with a forward slash '/'. + - The `limit` parameter determines how many row to read. Set it to 0 to convert all files. + - The `max_concurrency` parameter determines how many parquet files to process concurrently. + + Example usage: + ```python + for data in run_dataset(data_dir=r"./data/uspto/", limit=10, max_concurrency=2): + # Process each converted data entry + print(data) + ``` + """ + data_path = Path(data_dir) + logger.info(f"Processing files in {data_path}") + file_names = list(data_path.glob("*.parquet")) + for i, file_name in enumerate(file_names): + for x in scan_dataset(file_name, limit, max_concurrency).iter_rows(named=True): + yield x + + +def to_parquet( + output_dir: str, data_dir: str, limit: int, max_concurrency: int +) -> None: + output_dir = Path(output_dir) + datapath = Path(data_dir) + logger.info( + f'Processing {len(list(datapath.glob("*.parquet")))} files in {datapath}' + ) + for i, files in enumerate(tqdm(datapath.glob("*.parquet"))): + file_path = output_dir.joinpath(f"uspto{i}.parquet") + scan_dataset(files, limit, max_concurrency).write_parquet(file_path) + + +def scan_dataset(file_name, limit, max_concurrency) -> pl.DataFrame: + """ + Scans an individual parquet file and returns a processed DataFrame. + + Returns: + DataFrame: A processed DataFrame containing the selected columns from the dataset. + + Example Usage: + file_name = "dataset.parquet" + limit = 100 + max_concurrency = 4 + + result = scan_dataset((file_name, limit, max_concurrency)) + """ + parallel_apply_desc = partial(parallel_apply, False, max_concurrency) + parallel_apply_claims = partial(parallel_apply, True, max_concurrency) + columns = ( + "title_text", + "title_language", + "abstract_text", + "description_html", + "claims_html", + "publication_date", + "application_number", + "filing_date", + ) + + df: pl.LazyFrame = ( + pl.scan_parquet(file_name) + .select(columns) + .filter( + ~pl.all_horizontal( + pl.col(["abstract_text", "description_html", "claims_html"]).is_null() + ) + ) + # we use app no. for the id and filing date for the date created + .rename({"application_number": "id", "filing_date": "created"}) + .with_columns( + # the data was scrapped approx at this date + pl.lit("2024-03-22", dtype=pl.String).alias("added"), + col("created").cast(pl.String, strict=False), + col("publication_date").cast(pl.String, strict=False), + pl.concat_str( + pl.lit(r"ABSTRACT", dtype=pl.String), + pl.lit("\n\n", dtype=pl.String), + col("abstract_text"), + ignore_nulls=False, + ).alias("abstract_text"), + ) + .with_columns_seq( + col("description_html").map_batches( + parallel_apply_desc, + return_dtype=pl.String, + ), + col("claims_html").map_batches( + parallel_apply_claims, + return_dtype=pl.String, + ), + ) + .with_columns( + pl.concat_str( + col("title_text"), + pl.lit("\n\n", dtype=pl.String), + col("abstract_text"), + pl.lit("\n\n", dtype=pl.String), + col("description_html"), + pl.lit("\n\n", dtype=pl.String), + col("claims_html"), + ignore_nulls=True, + ).alias("text"), + pl.struct( + pl.lit(str(PermissiveLicenses.CC_BY), dtype=pl.String).alias("license"), + col("title_language").alias("language"), + col("publication_date").alias("publication_date"), + ).alias("metadata"), + pl.lit("Google Patents Public Data").alias("source"), + ) + ).select(["id", "text", "added", "created", "source", "metadata"]) + if limit > 0: + df = df.fetch(limit).lazy() + return df.collect() + + +def create_args_parser() -> argparse.ArgumentParser: + parser = argparse.ArgumentParser() + parser.add_argument( + "--output-path", type=str, help="Output directory", default=r"uspto/outputs" + ) + parser.add_argument( + "--data-path", + type=str, + default=r"uspto/data", + help="Dataset directory where all parquet files to process are located ", + ) + + parser.add_argument( + "--limit", + type=int, + default=0, + help="Limit the number of rows to read for testing", + ) + parser.add_argument( + "--max-concurrency", + type=int, + default=int(os.cpu_count()) - 1, + help="Maximum number of multiprocessing for pandoc conversions", + ) + parser.add_argument( + "--to-parquet", + action="store_true", + help="Output to parquet file", + ) + + return parser + + +if __name__ == "__main__": + args = create_args_parser().parse_args() + logger.info( + f"""Processing USPTO with the following parameters: Output Dir: {args.output_path}, Data Dir: {args.data_path}, + Limit: {args.limit}, Max Concurrency: {args.max_concurrency}""" + ) + if args.to_parquet: + to_parquet(args.output_path, args.data_path, args.limit, args.max_concurrency) + else: + to_dolma( + process_datasets( + data_dir=args.data_path, + limit=args.limit, + max_concurrency=args.max_concurrency, + ), + args.output_path, + "uspto.jsonl.gz", + ) diff --git a/uspto/utils.py b/uspto/utils.py new file mode 100644 index 0000000..bc397df --- /dev/null +++ b/uspto/utils.py @@ -0,0 +1,42 @@ +import multiprocessing +import re +from functools import partial +from itertools import islice + +import polars as pl +import pypandoc +from rich.progress import track + + +def batched(iterable, n): + it = iter(iterable) + while batch := tuple(islice(it, n)): + yield batch + + +def parse_html(claims: bool, html_string: str) -> str: + if not html_string: + return "" + text = pypandoc.convert_text(html_string, "plain", "html", extra_args=["--quiet"]) + # remove single newlines that are not surrounded by other newlines as those are likely line length formatting. + new_line_pattern = r"(? for claims (as they are all numbered). + list_pattern = r"(\s\d+\.\s)" + text = re.sub(new_line_pattern, " ", text) + if claims: + text = re.sub(list_pattern, r"\n\1", text) + return text + + +# from: https://stackoverflow.com/a/74749075/19355181 +def parallel_apply(claims: bool, max_concurrency: int, column: pl.Series) -> pl.Series: + if claims: + fn = partial(parse_html, True) + else: + fn = partial(parse_html, False) + if max_concurrency == 0: + max_concurrency = None + # polars mainly handles the concurrency but the pandoc calls add as a blocker. This is a workaround to + # increase the concurrency of the pandoc calls. + with multiprocessing.get_context("spawn").Pool(max_concurrency) as pool: + return pl.Series(pool.imap(fn, track(column, description="Processing column")))