From 2e59fc67d465510179155973d2b959e50a440e47 Mon Sep 17 00:00:00 2001
From: rhythm <31589689+rhythm16@users.noreply.github.com>
Date: Mon, 5 Jul 2021 20:19:29 +0800
Subject: [PATCH] armstub8: Initialize CPTR_EL3 with zeros (#123)

In both Cortex A53 and A72, every bit of CPTR_EL3 is RES0 except bit 10
and bit 31. We need bit 10 to be 0, also bit 31 is 0 previously, so
zero the entire register in initialization.
---
 armstubs/armstub8.S | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/armstubs/armstub8.S b/armstubs/armstub8.S
index c675e3e9..30eb238e 100644
--- a/armstubs/armstub8.S
+++ b/armstubs/armstub8.S
@@ -115,9 +115,8 @@ _start:
 	msr CNTVOFF_EL2, xzr
 
 	/* Enable FP/SIMD */
-	/* All set bits below are res1; bit 10 (TFP) is set to 0 */
-	mov x0, #0x33ff
-	msr CPTR_EL3, x0
+	/* Bit 10 (TFP) is set to 0 */
+	msr CPTR_EL3, xzr
 
 	/* Set up SCR */
 	mov x0, #SCR_VAL