ordered Index load to a weak-order memory region

[dangerblue]

In version 1.0, section 7.2.
“To provide ordered vector accesses to a strongly ordered IO region, the ordered indexed instructions should be used”
it is stated that in order to access a strongly ordered IO region in an ordered manner, the use of ordered indexed instructions is recommended. However, in cases where a processor does not support vector load store to a strongly ordered IO region, the behavior of this instruction is unclear.
While the instruction and memory attributes are defined separately, it is possible to define order index load/store to a weak order memory. However, it is important to note that there is no ordered requirement for the weak order memory. Therefore, it is possible that the implementation may choose not to keep the order, is it acceptable in spec?

[aswaterman]

I agree this could be expressed more clearly, but the idea is that ordered indexed accesses are roughly equivalent to a sequence of scalar accesses executed on a uniprocessor. So, if the region is strongly ordered, the accesses will be strongly ordered; and if the region is weakly ordered, the accesses will be weakly ordered.

However, recall that even weakly ordered regions require that same-address accesses from a given hart be kept in order. So, ordered indexed accesses are guaranteed to preserve same-address ordering, even if the region is weakly ordered.