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qmtech_wukong-rocket.dts
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qmtech_wukong-rocket.dts
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/dts-v1/;
/ {
#address-cells = <1>;
#size-cells = <1>;
chosen {
//bootargs = "console=liteuart earlycon=liteuart,0x12006800 rootwait root=/dev/mmcblk0p3";
bootargs = "console=hvc0 earlycon=sbi swiotlb=noforce root=/dev/mmcblk0p3 rw rootwait ";
linux,initrd-start = <0x82000000>;
linux,initrd-end = <0x83000000>;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <100000000>;
CPU0: cpu@0 {
device_type = "cpu";
compatible = "riscv";
riscv,isa = "rv64i2p0_mafdc";
mmu-type = "riscv,sv39";
reg = <0>;
clock-frequency = <100000000>;
status = "okay";
d-cache-size = <4096>;
d-cache-sets = <2>;
d-cache-block-size = <64>;
i-cache-size = <4096>;
i-cache-sets = <2>;
i-cache-block-size = <64>;
d-tlb-size = <4>;
d-tlb-sets = <1>;
i-tlb-size = <4>;
i-tlb-sets = <1>;
L0: interrupt-controller {
#interrupt-cells = <0x00000001>;
interrupt-controller;
compatible = "riscv,cpu-intc";
};
};
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x10000000>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
opensbi@80000000 {
reg = <0x80000000 0x200000>;
};
};
clocks {
sys_clk: litex_sys_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <100000000>;
};
};
vreg_mmc: vreg_mmc {
compatible = "regulator-fixed";
regulator-name = "vreg_mmc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "freechips,rocketchip-unknown-soc", "simple-bus";
interrupt-parent = <&intc0>;
ranges;
soc_ctrl0: soc_controller@12000000 {
compatible = "litex,soc-controller";
reg = <0x12000000 0xc>;
status = "okay";
};
lintc0: clint@2000000 {
compatible = "riscv,clint0";
interrupts-extended = <&L0 3 &L0 7>;
reg = <0x2000000 0x10000>;
reg-names = "control";
};
debug0: debug-controller@0 {
compatible = "sifive,debug-013", "riscv,debug-013";
interrupts-extended = <&L0 0x3F>;
reg = <0x0 0x1000>;
reg-names = "control";
};
error0: error-device@3000 {
compatible = "sifive,error0";
reg = <0x3000 0x1000>;
};
extirq0: external-interrupts {
interrupt-parent = <&intc0>;
interrupts = <1 2 3 4 5 6 7 8>;
};
intc0: interrupt-controller@c000000 {
compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
reg = <0xc000000 0x400000>;
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
interrupts-extended = < &L0 11 &L0 9>;
reg-names = "control";
riscv,max-priority = <7>;
riscv,ndev = <32>;
};
rom0: rom@10000 {
compatible = "sifive,rom0";
reg = <0x10000 0x10000>;
reg-names = "mem";
};
liteuart0: serial@12006800 {
compatible = "litex,liteuart";
reg = <0x12006800 0x100>;
interrupts = <1>;
status = "okay";
};
mac0: mac@12001000 {
compatible = "litex,liteeth";
reg = <0x12001000 0x7c>,
<0x12001800 0x0a>,
<0x30000000 0x2000>;
reg-names = "mac", "mdio", "buffer";
litex,rx-slots = <2>;
litex,tx-slots = <2>;
litex,slot-size = <2048>;
interrupts = <3>;
status = "okay";
};
mmc0: mmc@12005000 {
compatible = "litex,mmc";
reg = <0x12005000 0x100>,
<0x12003800 0x100>,
<0x12003000 0x100>,
<0x12004800 0x100>,
<0x12004000 0x100>;
reg-names = "phy", "core", "reader", "writer", "irq";
clocks = <&sys_clk>;
vmmc-supply = <&vreg_mmc>;
bus-width = <0x04>;
interrupts = <4>;
status = "okay";
};
leds: gpio@12002800 {
compatible = "litex,gpio";
reg = <0x12002800 0x4>;
gpio-controller;
#gpio-cells = <2>;
litex,direction = "out";
status = "disabled";
};
};
aliases {
serial0 = &liteuart0;
};
};
&leds {
litex,ngpio = <4>;
status = "okay";
};