diff --git a/compiler/rustc_target/src/spec/mod.rs b/compiler/rustc_target/src/spec/mod.rs index adea2caabbe75..16b7e148ba71d 100644 --- a/compiler/rustc_target/src/spec/mod.rs +++ b/compiler/rustc_target/src/spec/mod.rs @@ -1767,8 +1767,11 @@ supported_targets! { ("nvptx64-nvidia-cuda", nvptx64_nvidia_cuda), ("xtensa-esp32-none-elf", xtensa_esp32_none_elf), + ("xtensa-esp32-espidf", xtensa_esp32_espidf), ("xtensa-esp32s2-none-elf", xtensa_esp32s2_none_elf), + ("xtensa-esp32s2-espidf", xtensa_esp32s2_espidf), ("xtensa-esp32s3-none-elf", xtensa_esp32s3_none_elf), + ("xtensa-esp32s3-espidf", xtensa_esp32s3_espidf), ("i686-wrs-vxworks", i686_wrs_vxworks), ("x86_64-wrs-vxworks", x86_64_wrs_vxworks), diff --git a/compiler/rustc_target/src/spec/targets/xtensa_esp32_espidf.rs b/compiler/rustc_target/src/spec/targets/xtensa_esp32_espidf.rs new file mode 100644 index 0000000000000..1b66fdbd2afd6 --- /dev/null +++ b/compiler/rustc_target/src/spec/targets/xtensa_esp32_espidf.rs @@ -0,0 +1,36 @@ +use crate::abi::Endian; +use crate::spec::{base::xtensa, cvs, Target, TargetOptions}; + +pub fn target() -> Target { + Target { + llvm_target: "xtensa-none-elf".into(), + pointer_width: 32, + data_layout: "e-m:e-p:32:32-v1:8:8-i64:64-i128:128-n32".into(), + arch: "xtensa".into(), + metadata: crate::spec::TargetMetadata { + description: None, + tier: None, + host_tools: None, + std: None, + }, + + options: TargetOptions { + endian: Endian::Little, + c_int_width: "32".into(), + families: cvs!["unix"], + os: "espidf".into(), + env: "newlib".into(), + vendor: "espressif".into(), + + executables: true, + cpu: "esp32".into(), + linker: Some("xtensa-esp32-elf-gcc".into()), + + // The esp32 only supports native 32bit atomics. + max_atomic_width: Some(32), + atomic_cas: true, + + ..xtensa::opts() + }, + } +} diff --git a/compiler/rustc_target/src/spec/targets/xtensa_esp32s2_espidf.rs b/compiler/rustc_target/src/spec/targets/xtensa_esp32s2_espidf.rs new file mode 100644 index 0000000000000..ad5fda8a4ae14 --- /dev/null +++ b/compiler/rustc_target/src/spec/targets/xtensa_esp32s2_espidf.rs @@ -0,0 +1,43 @@ +use crate::abi::Endian; +use crate::spec::{base::xtensa, cvs, Target, TargetOptions}; + +pub fn target() -> Target { + Target { + llvm_target: "xtensa-none-elf".into(), + pointer_width: 32, + data_layout: "e-m:e-p:32:32-v1:8:8-i64:64-i128:128-n32".into(), + arch: "xtensa".into(), + metadata: crate::spec::TargetMetadata { + description: None, + tier: None, + host_tools: None, + std: None, + }, + + options: TargetOptions { + endian: Endian::Little, + c_int_width: "32".into(), + families: cvs!["unix"], + os: "espidf".into(), + env: "newlib".into(), + vendor: "espressif".into(), + + executables: true, + cpu: "esp32-s2".into(), + linker: Some("xtensa-esp32s2-elf-gcc".into()), + + // See https://github.com/espressif/rust-esp32-example/issues/3#issuecomment-861054477 + // + // While the ESP32-S2 chip does not natively support atomics, ESP-IDF does support + // the __atomic* and __sync* compiler builtins. Setting `max_atomic_width` and `atomic_cas` + // and `atomic_cas: true` will cause the compiler to emit libcalls to these builtins. On the + // ESP32-S2, these are guaranteed to be lock-free. + // + // Support for atomics is necessary for the Rust STD library, which is supported by ESP-IDF. + max_atomic_width: Some(32), + atomic_cas: true, + + ..xtensa::opts() + }, + } +} diff --git a/compiler/rustc_target/src/spec/targets/xtensa_esp32s3_espidf.rs b/compiler/rustc_target/src/spec/targets/xtensa_esp32s3_espidf.rs new file mode 100644 index 0000000000000..ab1d1df43dd99 --- /dev/null +++ b/compiler/rustc_target/src/spec/targets/xtensa_esp32s3_espidf.rs @@ -0,0 +1,36 @@ +use crate::abi::Endian; +use crate::spec::{base::xtensa, cvs, Target, TargetOptions}; + +pub fn target() -> Target { + Target { + llvm_target: "xtensa-none-elf".into(), + pointer_width: 32, + data_layout: "e-m:e-p:32:32-v1:8:8-i64:64-i128:128-n32".into(), + arch: "xtensa".into(), + metadata: crate::spec::TargetMetadata { + description: None, + tier: None, + host_tools: None, + std: None, + }, + + options: TargetOptions { + endian: Endian::Little, + c_int_width: "32".into(), + families: cvs!["unix"], + os: "espidf".into(), + env: "newlib".into(), + vendor: "espressif".into(), + + executables: true, + cpu: "esp32-s3".into(), + linker: Some("xtensa-esp32s3-elf-gcc".into()), + + // The esp32s3 only supports native 32bit atomics. + max_atomic_width: Some(32), + atomic_cas: true, + + ..xtensa::opts() + }, + } +} diff --git a/src/doc/rustc/src/platform-support.md b/src/doc/rustc/src/platform-support.md index c672cff74526e..e0ace5db2aacd 100644 --- a/src/doc/rustc/src/platform-support.md +++ b/src/doc/rustc/src/platform-support.md @@ -384,7 +384,10 @@ target | std | host | notes [`x86_64h-apple-darwin`](platform-support/x86_64h-apple-darwin.md) | ✓ | ✓ | macOS with late-gen Intel (at least Haswell) [`x86_64-unknown-linux-none`](platform-support/x86_64-unknown-linux-none.md) | * | | 64-bit Linux with no libc `xtensa-esp32-none-elf` | | | Xtensa ESP32 +`xtensa-esp32-espidf` | | | Xtensa ESP32 `xtensa-esp32s2-none-elf` | | | Xtensa ESP32-S2 +`xtensa-esp32s2-espidf` | | | Xtensa ESP32-S2 `xtensa-esp32s3-none-elf` | | | Xtensa ESP32-S3 +`xtensa-esp32s3-espidf` | | | Xtensa ESP32-S3 [runs on NVIDIA GPUs]: https://github.com/japaric-archived/nvptx#targets diff --git a/src/doc/rustc/src/platform-support/xtensa.md b/src/doc/rustc/src/platform-support/xtensa.md index 7785977466e4b..050ffcc8a41bb 100644 --- a/src/doc/rustc/src/platform-support/xtensa.md +++ b/src/doc/rustc/src/platform-support/xtensa.md @@ -13,13 +13,23 @@ Targets for Xtensa CPUs. The target names follow this format: `xtensa-$CPU`, where `$CPU` specifies the target chip. The following targets are currently defined: + +### `no_std` + | Target name | Target CPU(s) | | ------------------------- | --------------------------------------------------------------- | | `xtensa-esp32-none-elf` | [ESP32](https://www.espressif.com/en/products/socs/esp32) | | `xtensa-esp32s2-none-elf` | [ESP32-S2](https://www.espressif.com/en/products/socs/esp32-s2) | | `xtensa-esp32s3-none-elf` | [ESP32-S3](https://www.espressif.com/en/products/socs/esp32-s3) | +### `std` + +| Target name | Target CPU(s) | +| ----------------------- | --------------------------------------------------------------- | +| `xtensa-esp32-espidf` | [ESP32](https://www.espressif.com/en/products/socs/esp32) | +| `xtensa-esp32s2-espidf` | [ESP32-S2](https://www.espressif.com/en/products/socs/esp32-s2) | +| `xtensa-esp32s3-espidf` | [ESP32-S3](https://www.espressif.com/en/products/socs/esp32-s3) | -## Building the target +## Building the targets The targets can be built by installing the [Xtensa enabled Rust channel](https://github.com/esp-rs/rust/). See instructions in the [RISC-V and Xtensa Targets section of the The Rust on ESP Book](https://docs.esp-rs.org/book/installation/riscv-and-xtensa.html). diff --git a/src/tools/tidy/src/target_policy.rs b/src/tools/tidy/src/target_policy.rs index 06210c8cdb20f..cb9a0c1c7f4e2 100644 --- a/src/tools/tidy/src/target_policy.rs +++ b/src/tools/tidy/src/target_policy.rs @@ -14,8 +14,11 @@ const EXCEPTIONS: &[&str] = &[ "csky_unknown_linux_gnuabiv2hf", // FIXME: disabled since it requires a custom LLVM until the upstream LLVM adds support for the target (https://github.com/espressif/llvm-project/issues/4) "xtensa_esp32_none_elf", + "xtensa_esp32_espidf", "xtensa_esp32s2_none_elf", + "xtensa_esp32s2_espidf", "xtensa_esp32s3_none_elf", + "xtensa_esp32s3_espidf", ]; pub fn check(root_path: &Path, bad: &mut bool) { diff --git a/tests/assembly/targets/targets-elf.rs b/tests/assembly/targets/targets-elf.rs index 4c54fe639e3e6..6c96ece5568d7 100644 --- a/tests/assembly/targets/targets-elf.rs +++ b/tests/assembly/targets/targets-elf.rs @@ -578,12 +578,21 @@ revisions: xtensa_esp32_none_elf [xtensa_esp32_none_elf] compile-flags: --target xtensa-esp32-none-elf [xtensa_esp32_none_elf] needs-llvm-components: xtensa + revisions: xtensa_esp32_espidf + [xtensa_esp32_espidf] compile-flags: --target xtensa-esp32s2-espidf + [xtensa_esp32_espidf] needs-llvm-components: xtensa revisions: xtensa_esp32s2_none_elf [xtensa_esp32s2_none_elf] compile-flags: --target xtensa-esp32s2-none-elf [xtensa_esp32s2_none_elf] needs-llvm-components: xtensa + revisions: xtensa_esp32s2_espidf + [xtensa_esp32s2_espidf] compile-flags: --target xtensa-esp32s2-espidf + [xtensa_esp32s2_espidf] needs-llvm-components: xtensa revisions: xtensa_esp32s3_none_elf [xtensa_esp32s3_none_elf] compile-flags: --target xtensa-esp32s3-none-elf [xtensa_esp32s3_none_elf] needs-llvm-components: xtensa + revisions: xtensa_esp32s3_espidf + [xtensa_esp32s3_espidf] compile-flags: --target xtensa-esp32s3-espidf + [xtensa_esp32s3_espidf] needs-llvm-components: xtensa */ // Sanity-check that each target can produce assembly code.