From 9020b83b6ee17dae0ffc580cf1a1c9d311e4760c Mon Sep 17 00:00:00 2001
From: "Heinz N. Gies" <heinz@licenser.net>
Date: Fri, 31 Jan 2020 22:38:39 +0100
Subject: [PATCH] Fix mul intrinsics

---
 crates/core_arch/src/aarch64/neon/generated.rs |  8 ++++----
 crates/core_arch/src/arm/neon/generated.rs     | 16 ++++++++--------
 2 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs
index e579339259..3c2b16d4c0 100644
--- a/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/crates/core_arch/src/aarch64/neon/generated.rs
@@ -261,7 +261,7 @@ pub unsafe fn vcgeq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t {
 /// Multiply
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mul))]
+#[cfg_attr(test, assert_instr(fmul))]
 pub unsafe fn vmul_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
     simd_mul(a, b)
 }
@@ -269,7 +269,7 @@ pub unsafe fn vmul_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
 /// Multiply
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(mul))]
+#[cfg_attr(test, assert_instr(fmul))]
 pub unsafe fn vmulq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
     simd_mul(a, b)
 }
@@ -277,7 +277,7 @@ pub unsafe fn vmulq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 /// Subtract
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(sub))]
+#[cfg_attr(test, assert_instr(fsub))]
 pub unsafe fn vsub_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
     simd_sub(a, b)
 }
@@ -285,7 +285,7 @@ pub unsafe fn vsub_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
 /// Subtract
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(sub))]
+#[cfg_attr(test, assert_instr(fsub))]
 pub unsafe fn vsubq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
     simd_sub(a, b)
 }
diff --git a/crates/core_arch/src/arm/neon/generated.rs b/crates/core_arch/src/arm/neon/generated.rs
index d780985c30..87626f39a5 100644
--- a/crates/core_arch/src/arm/neon/generated.rs
+++ b/crates/core_arch/src/arm/neon/generated.rs
@@ -2074,8 +2074,8 @@ pub unsafe fn vmulq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(mul))]
-#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(mul))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(fmul))]
+#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(fmul))]
 pub unsafe fn vmul_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
     simd_mul(a, b)
 }
@@ -2084,8 +2084,8 @@ pub unsafe fn vmul_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(mul))]
-#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(mul))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(fmul))]
+#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(fmul))]
 pub unsafe fn vmulq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
     simd_mul(a, b)
 }
@@ -2254,8 +2254,8 @@ pub unsafe fn vsubq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(sub))]
-#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(sub))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(fsub))]
+#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(fsub))]
 pub unsafe fn vsub_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
     simd_sub(a, b)
 }
@@ -2264,8 +2264,8 @@ pub unsafe fn vsub_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
-#[cfg_attr(all(test, target_arch = "arm"), assert_instr(sub))]
-#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(sub))]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(fsub))]
+#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(fsub))]
 pub unsafe fn vsubq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
     simd_sub(a, b)
 }