diff --git a/orchagent/portsorch.cpp b/orchagent/portsorch.cpp
index ce6f117f7d..694644e94e 100755
--- a/orchagent/portsorch.cpp
+++ b/orchagent/portsorch.cpp
@@ -457,6 +457,7 @@ PortsOrch::PortsOrch(DBConnector *db, DBConnector *stateDb, vector<table_name_wi
         for (j = 0; j < attr.value.u32list.count; j++)
         {
             tmp_lane_set.insert(attr.value.u32list.list[j]);
+            m_availableLanes.insert(attr.value.u32list.list[j]);
         }
 
         string tmp_lane_str = "";
@@ -468,7 +469,6 @@ PortsOrch::PortsOrch(DBConnector *db, DBConnector *stateDb, vector<table_name_wi
 
         SWSS_LOG_NOTICE("Get port with lanes pid:%" PRIx64 " lanes:%s", port_list[i], tmp_lane_str.c_str());
         m_portListLaneMap[tmp_lane_set] = port_list[i];
-        m_availablePortSet.insert(tmp_lane_set);
     }
 
     /* Get default 1Q bridge and default VLAN */
@@ -2738,7 +2738,16 @@ void PortsOrch::doPortTask(Consumer &consumer)
 
                 for (auto it = m_lanesAliasSpeedMap.begin(); it != m_lanesAliasSpeedMap.end();)
                 {
-                    if (m_availablePortSet.find(it->first) == m_availablePortSet.end())
+                    bool lane_set_is_available = true;
+                    for (auto lane: it->first)
+                    {
+                        if (m_availableLanes.find(lane) == m_availableLanes.end())
+                        {
+                            lane_set_is_available = false;
+                            break;
+                        }
+                    }
+                    if (!lane_set_is_available)
                     {
                         string tmp_lane_str = "";
                         for (auto s : it->first)
diff --git a/orchagent/portsorch.h b/orchagent/portsorch.h
index 60dbc381a8..f0eb64953f 100755
--- a/orchagent/portsorch.h
+++ b/orchagent/portsorch.h
@@ -213,11 +213,9 @@ class PortsOrch : public Orch, public Subject
 
     port_config_state_t m_portConfigState = PORT_CONFIG_MISSING;
     sai_uint32_t m_portCount;
-    // m_portListLaneMap is the current enabled port list
     map<set<int>, sai_object_id_t> m_portListLaneMap;
     map<set<int>, tuple<string, uint32_t, int, string, int, string>> m_lanesAliasSpeedMap;
-    // m_availablePortSet is the available port list read from ASIC by SAI
-    set<set<int>> m_availablePortSet;
+    set<int> m_availableLanes;
     map<string, Port> m_portList;
     unordered_map<sai_object_id_t, int> m_portOidToIndex;
     map<string, uint32_t> m_port_ref_count;