Parse LiteX config file instead of generated headers

timvideos · Feb 19, 2020 · 07140bc · 07140bc
1 parent fee8231
commit 07140bc
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Showing 2 changed files with 6 additions and 9 deletions.
diff --git a/scripts/build-linux.sh b/scripts/build-linux.sh
@@ -154,17 +154,14 @@ if [ ${CPU} = vexriscv ]; then
 	(
 		cd $TOP_DIR
 
-		GENERATED_MEM_HEADERS="$TARGET_BUILD_DIR/software/include/generated/mem.h"
-		if [ ! -f "$GENERATED_MEM_HEADERS" ]; then
+		LITEX_RENODE="$TOP_DIR/third_party/litex-renode"
+		LITEX_CONFIG_FILE="$TARGET_BUILD_DIR/test/csr.csv"
+		if [ ! -f "$LITEX_CONFIG_FILE" ]; then
 			make firmware
 		fi
 
-		source $SCRIPT_DIR/build-common.sh
-		EMULATOR_RAM_BASE_ADDRESS=$(parse_generated_header "mem.h" EMULATOR_RAM_BASE)
-		RAM_BASE_ADDRESS=$(parse_generated_header "mem.h" MAIN_RAM_BASE)
-		# get rid of 'L' suffix
-		RAM_BASE_ADDRESS=${RAM_BASE_ADDRESS::-1}
-	 	EMULATOR_RAM_BASE_ADDRESS=${EMULATOR_RAM_BASE_ADDRESS::-1}
+		EMULATOR_RAM_BASE_ADDRESS=`python $LITEX_RENODE/litex-config-parser.py $LITEX_CONFIG_FILE --memory_base emulator_ram || true`
+		RAM_BASE_ADDRESS=`python $LITEX_RENODE/litex-config-parser.py $LITEX_CONFIG_FILE --memory_base main_ram || true`
 
 		cd $TOP_DIR/third_party/litex/litex/soc/cores/cpu/vexriscv/verilog/ext/VexRiscv/src/main/c/emulator
 

diff --git a/scripts/build-renode.sh b/scripts/build-renode.sh
@@ -45,7 +45,7 @@ if [ ! -f "$LITEX_CONFIG_FILE" ]; then
 fi
 
 # Ethernet
-ETH_BASE_ADDRESS=$(parse_generated_header "csr.h" CSR_ETHMAC_BASE)
+ETH_BASE_ADDRESS=`python $LITEX_RENODE/litex-config-parser.py $LITEX_CONFIG_FILE --csr_base ethmac || true`
 if [ ! -z "$ETH_BASE_ADDRESS" ]; then
 	RENODE_NETWORK=${RENODE_NETWORK:-tap}
 	case $RENODE_NETWORK in