Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Random collection of fixes. #15

Merged
merged 10 commits into from
Jan 21, 2018
Merged

Random collection of fixes. #15

merged 10 commits into from
Jan 21, 2018

Conversation

mithro
Copy link
Member

@mithro mithro commented Jan 20, 2018 •
edited
Loading

Bunch of fixes both extracted from @jimmo temporary commits and added while getting LiteEth to boot in QEMU for @shenki.

Fixes #14.

@mithro mithro requested a review from jimmo January 20, 2018 12:26
@mithro mithro mentioned this pull request Jan 20, 2018
Closed
ewenmcneill
ewenmcneill reviewed Jan 20, 2018
View reviewed changes
scripts/build-qemu.sh Outdated
# Get any new data
git fetch $CURRENT_QEMU_REMOTE_NAME

# Checkout or1k-linux branch it not already on it
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

From context it looks like this comment needs updating for scripts/build-qemu.sh: it appears to be checking out "master" branch here, not or1k-linux. Rest of the change looks plausible though.

@mithro mithro merged commit e423776 into timvideos:master Jan 21, 2018
futaris added a commit to futaris/litex-buildenv that referenced this pull request Feb 10, 2018
@futaris
Updating submodules.
457f145 
 * litedram changed from 13d41f6 to 5838953
    * 5838953 - modules: add MT47H64M16 <Florent Kermarrec>
    * 57c63c1 - phy/a7ddrphy: make reset_n optional <Florent Kermarrec>
    * ec9ad2f - frontend/dma: add description of fifo_buffered parameter <Florent Kermarrec>

 * litepcie changed from 945963d to 98a2c77
    * 98a2c77 - core/tlp/packetizer: typo <Florent Kermarrec>
    * d8bc19c - phy/s7pciephy: add x4 support (untested) <Florent Kermarrec>
    * 4609a88 - test/model/phy: fix typo <Florent Kermarrec>
    * a058223 - test/test_dma: remove converter parameter <Florent Kermarrec>
    * 525b843 - core/tlp/depacketizer: add 128 bits support (untested) <Florent Kermarrec>
    * 6210998 - core/tlp/packetizer: add 128 bits support (untested) <Florent Kermarrec>
    * 45227fe - example_designs/targets: fix dma target <Florent Kermarrec>
    * 7b5b806 - core/tlp/depacketizer: simplify using NextValue <Florent Kermarrec>

 * litevideo changed from 8d940dc to 78274ed
    * 78274ed - input/clocking: fix pix_o issue with spartan6 (will need cleaner fix) <Florent Kermarrec>
    *   61fa158 - Merge pull request timvideos#16 from MaZderMind/fix_hdmi_phy_cls_variable_name <Tim Ansell>
    |\
    | * 9907975 - fix variable name <MaZderMind>
    * |   96fdbec - Merge pull request timvideos#15 from bunnie/try_florent_720p <enjoy-digital>
    |\ \
    | |/
    |/|
    | * a44b5d7 - tweak clocking parameters -- maybe marginally better? <bunnie>
    | * 2d81c5b - fix phase relationship between master/slave MMCM <bunnie>
    | * 9d99716 - these mods add a second MMCM, to fix the BUFG/BUFIO issue <bunnie>
    * | 416ec42 - output/vga: shift datas when pads don't have 8 bits dynamic <Florent Kermarrec>
    * | 1ff01f2 - output: fix vga <Florent Kermarrec>
    |/
    * a385c73 - output: add vga phy <Florent Kermarrec>
    * c058946 - output/hdmi/s6: fix phy <Florent Kermarrec>
    * ad882a7 - output/hdmi/s6: fix missing mode to phy_layout <Florent Kermarrec>
    * c868806 - input/clocking: remove check on clock_polarity (obsolete) <Florent Kermarrec>

 * litex changed from 4f272580 to c1450280
    * c1450280 - board/targets/nexys4ddr: use MT47H64M16 <Florent Kermarrec>
    * 95ebba42 - boards/platforms/nexys4ddr: add user_sw, user_btn, fix ddr3 <Florent Kermarrec>
    * ee4fa597 - boards: add nexys4ddr <Florent Kermarrec>
    *   2ecd1b06 - Merge pull request timvideos#61 from PaulSchulz/master <enjoy-digital>
    |\
    | * 0ac35300 - Merge branch 'master' of https://github.com/enjoy-digital/litex into upstream <Paul Schulz>
    | * 3ac28ed6 - platform/arty.py: Move Pmod definitions to 'connectors' section. <Paul Schulz>
    * c83ae98b - Merge pull request timvideos#63 from cr1901/arty_s7 <enjoy-digital>
    * 4607e532 - boards/platforms: Add Arty S7 Board. <William D. Jones>

Full submodule status
--
-f56f329ed23a25d002352dedba1e8f092a47286f edid-decode
-c5064269868396b2c7a78bff28f8e3cf421d1f6e flash_proxies
 58389534e6c4716c75cbabdae23518c8befe36cd litedram (heads/master)
 8fc716103670e703c7fe98c9bdf653b9b53ca12a liteeth (heads/master)
 98a2c779ca38410445e066041db3faa021751662 litepcie (heads/master)
 af00fa613f1b6921e14788dd0ebf301e51009e74 litesata (heads/master)
 aa44da35c6a232a9e39c43987a3afc9b025ab614 litescope (heads/master)
 0b05b6c8f9279bb7e476b2c8ae4f39ea88534f08 liteusb (heads/master)
 78274ed1d6ddff4efe1bc7f74b3b4e9beb7dfc53 litevideo (heads/master)
 c14502807e4d4cf62fabf73f678d5ee328717909 litex (heads/master)
mithro pushed a commit to cr1901/litex-buildenv that referenced this pull request Mar 4, 2018
@cr1901 @mithro
Update litex submodules; imports changed, does not compile.
4415ccc 
 * flash_proxies changed from c506426 to a628956
    * a628956 - Merge pull request timvideos#4 from cr1901/more-series7 <Robert Jördens>
    * 8be7e2d - Add new bitstream proxies for devices available as of Vivado 2017.4.1. <William D. Jones>
    * 29d9124 - Add new packages for missing Series 7 family members. <William D. Jones>
    * c1d8007 - Add missing Series 7 family members. <William D. Jones>

 * litedram changed from 13d41f6 to 48bc3cb
    * 48bc3cb - README: add migen dependency <Florent Kermarrec>
    * 697f46a - replace litex.gen imports with migen imports <Florent Kermarrec>
    * bd43fd6 - bump to 0.2.dev <Florent Kermarrec>
    * 45a948d - uniformize litex cores <Florent Kermarrec>
    * 5838953 - modules: add MT47H64M16 <Florent Kermarrec>
    * 57c63c1 - phy/a7ddrphy: make reset_n optional <Florent Kermarrec>
    * ec9ad2f - frontend/dma: add description of fifo_buffered parameter <Florent Kermarrec>

 * liteeth changed from 8fc7161 to 33afda7
    * 33afda7 - README: add migen dependency <Florent Kermarrec>
    * 79a6ba7 - replace litex.gen imports with migen imports <Florent Kermarrec>
    * c15f089 - bump to 0.2.dev <Florent Kermarrec>
    * c42aa09 - uniformize litex cores <Florent Kermarrec>
    * 4e08d6e - Merge pull request timvideos#13 from felixheld/crc_pythonize <enjoy-digital>
    * 9dcc7bc - mac/crc.py: make crc calculation more pythonic <Felix Held>
    * 2ceaa74 - clarify the comments in mac/crc.py code <Felix Held>

 * litepcie changed from 945963d to 6b147e1
    * 6b147e1 - frontend/dma: add 16 bits control field to descriptors <Florent Kermarrec>
    * 08a4501 - README: add migen dependency <Florent Kermarrec>
    * 6afbd1c - frontend/dma/LitePCIeDMAWriter: switch to next decriptor when sink.last is asserted <Florent Kermarrec>
    * ed0b8a4 - phy/xilinx/7-series: integrate v3.3 files (working for x2) <Florent Kermarrec>
    * d9b8b2a - core/tlp/packetizer: add 128 bits support <Florent Kermarrec>
    * 686da6b - core/tlp/depacketizer: add 128 bits support <Florent Kermarrec>
    * 0724533 - replace litex.gen imports with migen imports <Florent Kermarrec>
    * 3e38b54 - bump to 0.2.dev <Florent Kermarrec>
    * 96cdfe6 - revert phy to 3.0 and tlp packetizer/depacketizer to fixed 64 bit version (until we investigate the regression) <Florent Kermarrec>
    * d7d9e5f - uniformize litex cores <Florent Kermarrec>
    * 058c493 - phy/xilinx/7-series: update to 3.3 <Florent Kermarrec>
    * 98a2c77 - core/tlp/packetizer: typo <Florent Kermarrec>
    * d8bc19c - phy/s7pciephy: add x4 support (untested) <Florent Kermarrec>
    * 4609a88 - test/model/phy: fix typo <Florent Kermarrec>
    * a058223 - test/test_dma: remove converter parameter <Florent Kermarrec>
    * 525b843 - core/tlp/depacketizer: add 128 bits support (untested) <Florent Kermarrec>
    * 6210998 - core/tlp/packetizer: add 128 bits support (untested) <Florent Kermarrec>
    * 45227fe - example_designs/targets: fix dma target <Florent Kermarrec>
    * 7b5b806 - core/tlp/depacketizer: simplify using NextValue <Florent Kermarrec>

 * litesata changed from af00fa6 to a559afb
    * a559afb - README: add migen dependency <Florent Kermarrec>
    * c1e1341 - replace litex.gen imports with migen imports <Florent Kermarrec>
    * eafaf16 - bump to 0.2.dev <Florent Kermarrec>
    * a6c08ce - uniformize litex cores <Florent Kermarrec>

 * litescope changed from aa44da3 to 9d5e605
    * 9d5e605 - replace litex.gen imports with migen imports <Florent Kermarrec>
    * 302a484 - bump to 0.2.dev <Florent Kermarrec>
    * 62c4bdd - uniformize litex cores <Florent Kermarrec>
    * 985585f - __init__: add LiteScopeIODriver and LiteScopeAnalyzerDriver imports <Florent Kermarrec>

 * liteusb changed from 0b05b6c to 23d6a68
    * 23d6a68 - README: add migen dependency <Florent Kermarrec>
    * 102a751 - replace litex.gen imports with migen imports <Florent Kermarrec>
    * 3faa9ae - bump to 0.2.dev <Florent Kermarrec>
    * d52cf32 - uniformize litex cores <Florent Kermarrec>

 * litevideo changed from 9907975 to 18b88df
    * 18b88df - input/edid: fix scl polarity <Florent Kermarrec>
    * a3c1984 - README: add migen dependency <Florent Kermarrec>
    * 152b6d7 - replace litex.gen imports with migen imports <Florent Kermarrec>
    * c96ef9c - bump to 0.2.dev <Florent Kermarrec>
    * 2274b01 - uniformize litex cores <Florent Kermarrec>
    * 50e8ac9 - output/VGAPHY: add missing self.sink.ready.eq(1) <Florent Kermarrec>
    * a7e289a - make split-clocking optional, also make output stage PLLE2 + BUFG <bunnie>
    * 78274ed - input/clocking: fix pix_o issue with spartan6 (will need cleaner fix) <Florent Kermarrec>
    * 61fa158 - Merge pull request timvideos#16 from MaZderMind/fix_hdmi_phy_cls_variable_name <Tim Ansell>
    * 96fdbec - Merge pull request timvideos#15 from bunnie/try_florent_720p <enjoy-digital>
    * a44b5d7 - tweak clocking parameters -- maybe marginally better? <bunnie>
    * 2d81c5b - fix phase relationship between master/slave MMCM <bunnie>
    * 9d99716 - these mods add a second MMCM, to fix the BUFG/BUFIO issue <bunnie>

 * litex changed from 4f272580 to 3e7cc255
    *   3e7cc255 - Merge pull request timvideos#69 from mithro/conda-support <enjoy-digital>
    |\
    | * 3bf50479 - travis: Adding some color. <Tim 'mithro' Ansell>
    | * 083c2613 - travis: Move the conda install into script so it can be folded. <Tim 'mithro' Ansell>
    | * da3189c8 - travis: Making the output more readable. <Tim 'mithro' Ansell>
    | * 12bb3ebf - travis: Build all the SoCs (without gateware). <Tim 'mithro' Ansell>
    | * e65c121a - Adding a travis config which tests the conda environment still works. <Tim 'mithro' Ansell>
    | * 795e8285 - Adding conda environment example. <Tim 'mithro' Ansell>
    |/
    *   ab2a3277 - Merge pull request timvideos#67 from cr1901/vivado-paths <enjoy-digital>
    |\
    | * 2b00b7eb - xilinx/vivado: Provide a fallback mechanism for using the same root for Vivado and ISE toolchains. <William D. Jones>
    * |   db20df49 - Merge pull request timvideos#65 from cr1901/tinyfpga-serial <enjoy-digital>
    |\ \
    | * | e71593d6 - platforms/tinyfpga_b: Move serial peripheral out of default I/O, make it optional via `add_extension`. <William D. Jones>
    * | | fa6b2561 - build/xilinx/platform: fix merge <Florent Kermarrec>
    * | |   87d4af0b - Merge pull request timvideos#66 from cr1901/arty_s7 <Tim Ansell>
    |\ \ \
    | * | | d40c5773 - boards/arty_s7: Fix IOStandard on System Clock. <William D. Jones>
    |/ / /
    * | | 7bd718eb - README: add migen installation to quick start guide <Florent Kermarrec>
    | |/
    |/|
    * | 0332f73a - build/xilinx/vivado: revert toolchain_path <Florent Kermarrec>
    * | 2ff50a88 - build: fix merge <Florent Kermarrec>
    * | 64e4e1ce - build: merge with migen.build 27beffe7 <Florent Kermarrec>
    * | 0edfd9b9 - boards/kcu105: regroup sfp tx and rx <Florent Kermarrec>
    |/
    * c5be6e26 - README: add section for newcomers <Florent Kermarrec>
    * f372e8c8 - README: cleanup <Florent Kermarrec>
    * fb088b79 - README: update, migen is no longer forked <Florent Kermarrec>
    * 1925ba17 - replace litex.gen imports with migen imports <Florent Kermarrec>
    * 43164b9a - remove migen fork from litex <Florent Kermarrec>
    * 212e1a70 - bump to 0.2.dev <Florent Kermarrec>
    * 64aa4ae4 - uniformize with litex cores and make things more clear about what LiteX vs Migen/MiSoC <Florent Kermarrec>
    *   aaf09705 - Merge pull request timvideos#64 from q3k/q3k/axi4lite <enjoy-digital>
    |\
    | * 688f26cc - Change AXI interface and tidy code <Sergiusz Bazanski>
    | * 512ed2b3 - Preliminary AXI4Lite CSR bridge support <Sergiusz Bazanski>
    |/
    *   55fc9d2d - Merge pull request timvideos#60 from q3k/for-upstream/top-level-module-selection <enjoy-digital>
    |\
    | * ef511e7e - Specify top-level module in Lattice Diemond build script. <Sergiusz Bazanski>
    | * ef6c517d - Build top module as 'dut' in Verilator and set it as top-level. <Sergiusz Bazanski>
    *   7b5bd404 - Merge pull request timvideos#57 from rohitk-singh/master <enjoy-digital>
    |\
    | * 75e7f950 - BIOS: Flashboot without main ram <Ewen McNeill>
    * c1450280 - board/targets/nexys4ddr: use MT47H64M16 <Florent Kermarrec>
    * 95ebba42 - boards/platforms/nexys4ddr: add user_sw, user_btn, fix ddr3 <Florent Kermarrec>
    * ee4fa597 - boards: add nexys4ddr <Florent Kermarrec>
    *   2ecd1b06 - Merge pull request timvideos#61 from PaulSchulz/master <enjoy-digital>
    |\
    | * 0ac35300 - Merge branch 'master' of https://github.com/enjoy-digital/litex into upstream <Paul Schulz>
    | * 3ac28ed6 - platform/arty.py: Move Pmod definitions to 'connectors' section. <Paul Schulz>
    * c83ae98b - Merge pull request timvideos#63 from cr1901/arty_s7 <enjoy-digital>
    * 4607e532 - boards/platforms: Add Arty S7 Board. <William D. Jones>

Full submodule status
--
 f56f329ed23a25d002352dedba1e8f092a47286f edid-decode (heads/master)
 a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD)
 48bc3cb15d17202a19e621acd83d2733190285b2 litedram (remotes/origin/HEAD)
 33afda74f77f7bafa3e4e19641b9043320c47e4e liteeth (remotes/origin/HEAD)
 6b147e1d120a3a062cf2c85e950d358b39edb8eb litepcie (remotes/origin/HEAD)
 a559afb2c53932f29ecc4cec8aa394d1004377c1 litesata (remotes/origin/HEAD)
 9d5e605df3e5f1d54609acc5a2f10764045127e9 litescope (remotes/origin/HEAD)
 23d6a6840d4276f8d1a7f31bafb8d0aaaecff6d1 liteusb (remotes/origin/HEAD)
 18b88dfee6bf6f4ab55d196747ca00c6c84c2ef2 litevideo (remotes/origin/HEAD)
 3e7cc2554b7dcc578ca86fd881d3523625b888f8 litex (remotes/origin/HEAD)
mithro pushed a commit that referenced this pull request Mar 19, 2018
@cr1901 @mithro
Update litex submodules; imports changed, does not compile.
15a01e4 
 * flash_proxies changed from c506426 to a628956
    * a628956 - Merge pull request #4 from cr1901/more-series7 <Robert Jördens>
    * 8be7e2d - Add new bitstream proxies for devices available as of Vivado 2017.4.1. <William D. Jones>
    * 29d9124 - Add new packages for missing Series 7 family members. <William D. Jones>
    * c1d8007 - Add missing Series 7 family members. <William D. Jones>

 * litedram changed from 13d41f6 to 48bc3cb
    * 48bc3cb - README: add migen dependency <Florent Kermarrec>
    * 697f46a - replace litex.gen imports with migen imports <Florent Kermarrec>
    * bd43fd6 - bump to 0.2.dev <Florent Kermarrec>
    * 45a948d - uniformize litex cores <Florent Kermarrec>
    * 5838953 - modules: add MT47H64M16 <Florent Kermarrec>
    * 57c63c1 - phy/a7ddrphy: make reset_n optional <Florent Kermarrec>
    * ec9ad2f - frontend/dma: add description of fifo_buffered parameter <Florent Kermarrec>

 * liteeth changed from 8fc7161 to 33afda7
    * 33afda7 - README: add migen dependency <Florent Kermarrec>
    * 79a6ba7 - replace litex.gen imports with migen imports <Florent Kermarrec>
    * c15f089 - bump to 0.2.dev <Florent Kermarrec>
    * c42aa09 - uniformize litex cores <Florent Kermarrec>
    * 4e08d6e - Merge pull request #13 from felixheld/crc_pythonize <enjoy-digital>
    * 9dcc7bc - mac/crc.py: make crc calculation more pythonic <Felix Held>
    * 2ceaa74 - clarify the comments in mac/crc.py code <Felix Held>

 * litepcie changed from 945963d to 6b147e1
    * 6b147e1 - frontend/dma: add 16 bits control field to descriptors <Florent Kermarrec>
    * 08a4501 - README: add migen dependency <Florent Kermarrec>
    * 6afbd1c - frontend/dma/LitePCIeDMAWriter: switch to next decriptor when sink.last is asserted <Florent Kermarrec>
    * ed0b8a4 - phy/xilinx/7-series: integrate v3.3 files (working for x2) <Florent Kermarrec>
    * d9b8b2a - core/tlp/packetizer: add 128 bits support <Florent Kermarrec>
    * 686da6b - core/tlp/depacketizer: add 128 bits support <Florent Kermarrec>
    * 0724533 - replace litex.gen imports with migen imports <Florent Kermarrec>
    * 3e38b54 - bump to 0.2.dev <Florent Kermarrec>
    * 96cdfe6 - revert phy to 3.0 and tlp packetizer/depacketizer to fixed 64 bit version (until we investigate the regression) <Florent Kermarrec>
    * d7d9e5f - uniformize litex cores <Florent Kermarrec>
    * 058c493 - phy/xilinx/7-series: update to 3.3 <Florent Kermarrec>
    * 98a2c77 - core/tlp/packetizer: typo <Florent Kermarrec>
    * d8bc19c - phy/s7pciephy: add x4 support (untested) <Florent Kermarrec>
    * 4609a88 - test/model/phy: fix typo <Florent Kermarrec>
    * a058223 - test/test_dma: remove converter parameter <Florent Kermarrec>
    * 525b843 - core/tlp/depacketizer: add 128 bits support (untested) <Florent Kermarrec>
    * 6210998 - core/tlp/packetizer: add 128 bits support (untested) <Florent Kermarrec>
    * 45227fe - example_designs/targets: fix dma target <Florent Kermarrec>
    * 7b5b806 - core/tlp/depacketizer: simplify using NextValue <Florent Kermarrec>

 * litesata changed from af00fa6 to a559afb
    * a559afb - README: add migen dependency <Florent Kermarrec>
    * c1e1341 - replace litex.gen imports with migen imports <Florent Kermarrec>
    * eafaf16 - bump to 0.2.dev <Florent Kermarrec>
    * a6c08ce - uniformize litex cores <Florent Kermarrec>

 * litescope changed from aa44da3 to 9d5e605
    * 9d5e605 - replace litex.gen imports with migen imports <Florent Kermarrec>
    * 302a484 - bump to 0.2.dev <Florent Kermarrec>
    * 62c4bdd - uniformize litex cores <Florent Kermarrec>
    * 985585f - __init__: add LiteScopeIODriver and LiteScopeAnalyzerDriver imports <Florent Kermarrec>

 * liteusb changed from 0b05b6c to 23d6a68
    * 23d6a68 - README: add migen dependency <Florent Kermarrec>
    * 102a751 - replace litex.gen imports with migen imports <Florent Kermarrec>
    * 3faa9ae - bump to 0.2.dev <Florent Kermarrec>
    * d52cf32 - uniformize litex cores <Florent Kermarrec>

 * litevideo changed from 9907975 to 18b88df
    * 18b88df - input/edid: fix scl polarity <Florent Kermarrec>
    * a3c1984 - README: add migen dependency <Florent Kermarrec>
    * 152b6d7 - replace litex.gen imports with migen imports <Florent Kermarrec>
    * c96ef9c - bump to 0.2.dev <Florent Kermarrec>
    * 2274b01 - uniformize litex cores <Florent Kermarrec>
    * 50e8ac9 - output/VGAPHY: add missing self.sink.ready.eq(1) <Florent Kermarrec>
    * a7e289a - make split-clocking optional, also make output stage PLLE2 + BUFG <bunnie>
    * 78274ed - input/clocking: fix pix_o issue with spartan6 (will need cleaner fix) <Florent Kermarrec>
    * 61fa158 - Merge pull request #16 from MaZderMind/fix_hdmi_phy_cls_variable_name <Tim Ansell>
    * 96fdbec - Merge pull request #15 from bunnie/try_florent_720p <enjoy-digital>
    * a44b5d7 - tweak clocking parameters -- maybe marginally better? <bunnie>
    * 2d81c5b - fix phase relationship between master/slave MMCM <bunnie>
    * 9d99716 - these mods add a second MMCM, to fix the BUFG/BUFIO issue <bunnie>

 * litex changed from 4f272580 to 3e7cc255
    *   3e7cc255 - Merge pull request #69 from mithro/conda-support <enjoy-digital>
    |\
    | * 3bf50479 - travis: Adding some color. <Tim 'mithro' Ansell>
    | * 083c2613 - travis: Move the conda install into script so it can be folded. <Tim 'mithro' Ansell>
    | * da3189c8 - travis: Making the output more readable. <Tim 'mithro' Ansell>
    | * 12bb3ebf - travis: Build all the SoCs (without gateware). <Tim 'mithro' Ansell>
    | * e65c121a - Adding a travis config which tests the conda environment still works. <Tim 'mithro' Ansell>
    | * 795e8285 - Adding conda environment example. <Tim 'mithro' Ansell>
    |/
    *   ab2a3277 - Merge pull request #67 from cr1901/vivado-paths <enjoy-digital>
    |\
    | * 2b00b7eb - xilinx/vivado: Provide a fallback mechanism for using the same root for Vivado and ISE toolchains. <William D. Jones>
    * |   db20df49 - Merge pull request #65 from cr1901/tinyfpga-serial <enjoy-digital>
    |\ \
    | * | e71593d6 - platforms/tinyfpga_b: Move serial peripheral out of default I/O, make it optional via `add_extension`. <William D. Jones>
    * | | fa6b2561 - build/xilinx/platform: fix merge <Florent Kermarrec>
    * | |   87d4af0b - Merge pull request #66 from cr1901/arty_s7 <Tim Ansell>
    |\ \ \
    | * | | d40c5773 - boards/arty_s7: Fix IOStandard on System Clock. <William D. Jones>
    |/ / /
    * | | 7bd718eb - README: add migen installation to quick start guide <Florent Kermarrec>
    | |/
    |/|
    * | 0332f73a - build/xilinx/vivado: revert toolchain_path <Florent Kermarrec>
    * | 2ff50a88 - build: fix merge <Florent Kermarrec>
    * | 64e4e1ce - build: merge with migen.build 27beffe7 <Florent Kermarrec>
    * | 0edfd9b9 - boards/kcu105: regroup sfp tx and rx <Florent Kermarrec>
    |/
    * c5be6e26 - README: add section for newcomers <Florent Kermarrec>
    * f372e8c8 - README: cleanup <Florent Kermarrec>
    * fb088b79 - README: update, migen is no longer forked <Florent Kermarrec>
    * 1925ba17 - replace litex.gen imports with migen imports <Florent Kermarrec>
    * 43164b9a - remove migen fork from litex <Florent Kermarrec>
    * 212e1a70 - bump to 0.2.dev <Florent Kermarrec>
    * 64aa4ae4 - uniformize with litex cores and make things more clear about what LiteX vs Migen/MiSoC <Florent Kermarrec>
    *   aaf09705 - Merge pull request #64 from q3k/q3k/axi4lite <enjoy-digital>
    |\
    | * 688f26cc - Change AXI interface and tidy code <Sergiusz Bazanski>
    | * 512ed2b3 - Preliminary AXI4Lite CSR bridge support <Sergiusz Bazanski>
    |/
    *   55fc9d2d - Merge pull request #60 from q3k/for-upstream/top-level-module-selection <enjoy-digital>
    |\
    | * ef511e7e - Specify top-level module in Lattice Diemond build script. <Sergiusz Bazanski>
    | * ef6c517d - Build top module as 'dut' in Verilator and set it as top-level. <Sergiusz Bazanski>
    *   7b5bd404 - Merge pull request #57 from rohitk-singh/master <enjoy-digital>
    |\
    | * 75e7f950 - BIOS: Flashboot without main ram <Ewen McNeill>
    * c1450280 - board/targets/nexys4ddr: use MT47H64M16 <Florent Kermarrec>
    * 95ebba42 - boards/platforms/nexys4ddr: add user_sw, user_btn, fix ddr3 <Florent Kermarrec>
    * ee4fa597 - boards: add nexys4ddr <Florent Kermarrec>
    *   2ecd1b06 - Merge pull request #61 from PaulSchulz/master <enjoy-digital>
    |\
    | * 0ac35300 - Merge branch 'master' of https://github.com/enjoy-digital/litex into upstream <Paul Schulz>
    | * 3ac28ed6 - platform/arty.py: Move Pmod definitions to 'connectors' section. <Paul Schulz>
    * c83ae98b - Merge pull request #63 from cr1901/arty_s7 <enjoy-digital>
    * 4607e532 - boards/platforms: Add Arty S7 Board. <William D. Jones>

Full submodule status
--
 f56f329ed23a25d002352dedba1e8f092a47286f edid-decode (heads/master)
 a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD)
 48bc3cb15d17202a19e621acd83d2733190285b2 litedram (remotes/origin/HEAD)
 33afda74f77f7bafa3e4e19641b9043320c47e4e liteeth (remotes/origin/HEAD)
 6b147e1d120a3a062cf2c85e950d358b39edb8eb litepcie (remotes/origin/HEAD)
 a559afb2c53932f29ecc4cec8aa394d1004377c1 litesata (remotes/origin/HEAD)
 9d5e605df3e5f1d54609acc5a2f10764045127e9 litescope (remotes/origin/HEAD)
 23d6a6840d4276f8d1a7f31bafb8d0aaaecff6d1 liteusb (remotes/origin/HEAD)
 18b88dfee6bf6f4ab55d196747ca00c6c84c2ef2 litevideo (remotes/origin/HEAD)
 3e7cc2554b7dcc578ca86fd881d3523625b888f8 litex (remotes/origin/HEAD)
mateusz-holenko added a commit to antmicro/litex-buildenv that referenced this pull request Jun 12, 2019
@mateusz-holenko
Updating submodules.
16577a9 
 * edid-decode changed from 6def7bc to dc763d7
    * dc763d7 - Update email addresses <Hans Verkuil>
    * 726576d - edid-decode: add CTA-861.4/5 support <Hans Verkuil>

 * flash_proxies changed from a628956 to 1c21ee4
    * 1c21ee4 - README: update <Robert Jördens>

 * litedram changed from d89b171 to 7fbe0b7
    *   7fbe0b7 - Merge pull request timvideos#84 from open-design/is42s16320 <enjoy-digital>
    |\
    | * 5c66547 - modules: SDRAM: add IS42S16320 support <Antony Pavlov>
    |/
    * 8e2df17 - modules: fix tRFC change on MT16KTF1G64HZ <Florent Kermarrec>
    * bc88cfa - modules: allow tRFC to be defined in ck or ns, fix some DDR3/DDR4 definitions (thanks @ambrop72 for the review) <Florent Kermarrec>
    * fbd7ae3 - modules: make IS43TR16128B consistent with others SDRAMModules <Florent Kermarrec>
    *   02448a3 - Merge pull request timvideos#83 from ambrop72/IS43TR16128B_125K <enjoy-digital>
    |\
    | * d108970 - modules/ddr3: add IS43TR16128B_125K <Ambroz Bizjak>
    |/
    *   da68e21 - Merge pull request timvideos#82 from gsomlo/gls-expose-csr <enjoy-digital>
    |\
    | * 65451f4 - examples/litedram_gen: allow direct access to CSR (I/O) registers <Gabriel L. Somlo>
    |/
    * 50e1d47 - PhySettings: add databits to allow SoC to compute memory size more easily <Florent Kermarrec>
    * b93412b - examples: remove verilog simulation <Florent Kermarrec>
    * a7e46bb - example/litedram_gen: reserve_nmi_interrupt no longer exists <Florent Kermarrec>
    *   094fc2e - Merge pull request timvideos#79 from gsomlo/gls-ulong-addr <enjoy-digital>
    |\
    | * 54d3312 - sdram_init: use "unsigned long" for address values <Gabriel L. Somlo>
    |/
    * 3caaa2e - common/tXXDController: revert Yosys workarounds <Florent Kermarrec>
    * 44bbb93 - phy: add copyrights <Florent Kermarrec>
    * 6ddc2c8 - README: update <Florent Kermarrec>
    * 9190a76 - travis: simplify and add RISC-V toolchain to run examples <Florent Kermarrec>
    * e824288 - frontend/axi: move AXIBurst2Beat to LiteX <Florent Kermarrec>
    * be269da - frontend/axi: use definitions from LiteX <Florent Kermarrec>
    * e81b5a1 - sdram_init: set __attribute__((unused)) on command_px to avoid compilation warning <Florent Kermarrec>
    * c4161cf - examples: update sim <Florent Kermarrec>
    * 201a0e2 - test/test_examples: add nexys4ddr <Florent Kermarrec>
    * 69afaf5 - common: add separators, reorganize a bit <Florent Kermarrec>
    * 0bc241c - phy/ecp5ddrphy: use inline comments on ECP5DDRPHYInit <Florent Kermarrec>
    * c65ff97 - phy/ecp5ddrphy: simplify ECP5DDRPHYInit, integrate it in the PHY, add burstdet registers <Florent Kermarrec>
    * 4274db8 - common/TXXDcontroller: fix for compatibility with Yosys and vendor tools <Florent Kermarrec>
    * a74d5c9 - common/TXXDcontroller: set ready default value to 1 with self.comb instead of reset value <Florent Kermarrec>
    *   cec35f3 - Merge pull request timvideos#77 from daveshah1/ecp5_75MHz <enjoy-digital>
    |\
    | * fa26dcd - ecp5ddrphy: Shift read position forwards to fix higher frequencies <David Shah>
    |/
    *   6715c1b - Merge pull request timvideos#76 from daveshah1/trellis_io <enjoy-digital>
    |\
    | * 691d930 - ecp5ddrphy: Use triples for inputs to fix build with TRELLIS_IOs <David Shah>
    |/
    * 9057f51 - phy: add ECP5 imports <Florent Kermarrec>
    * f660618 - phy: add initial ECP5DDRPHY <Florent Kermarrec>
    * 640194a - examples: add nexys4ddr_config <Florent Kermarrec>
    * 0ac1af3 - examples/litedram_gen: add DDR2 support <Florent Kermarrec>
    * f4184ec - example/litedram_gen: update, add descriptions of config parameters <Florent Kermarrec>
    * 79806aa - modules/ddr3: add MT41K64M16 <Florent Kermarrec>
    * ea6b841 - phy/s7ddrphy and usddrphy: add cmd_latency parameter <Florent Kermarrec>
    * fd3e9af - phy/s7ddrphy: fix cmd delays <Florent Kermarrec>
    * f61c8d9 - phy/s7ddrphy: make clk/cmd odelaye2s configurable <Florent Kermarrec>
    * e0224f4 - phy/usddrphy: make clk/cmd odelaye3s configurable <Florent Kermarrec>

 * liteeth changed from 77fa4bf to 2424e62
    * 2424e62 - software: also include generated/mem.h <Florent Kermarrec>
    * e88fc50 - software: remote ethmac_mem.h dependency (no longer exists in LiteX) <Florent Kermarrec>
    * b318300 - phy/ku_1000basex: keep tx/rx in reset until pll is fully reseted and locked <Florent Kermarrec>
    * e6c35cd - phy/ku_1000basex: incease pll_reset <Florent Kermarrec>
    * 816f592 - phy: add initial ECP5RGMII PHY <Florent Kermarrec>
    * b4c1cfe - core/icmp: fix reply checksum when request checksum >= 0xf800 <Florent Kermarrec>

 * litepcie changed from 3804c49 to de6cd01
    * de6cd01 - frontend/dma: ensure we finish LitePCIeDMAWriter transaction when DMA is disabled. <Florent Kermarrec>
    * 260c562 - frontend/wishbone: cleanup qword_aligned support <Florent Kermarrec>
    * 89b3920 - README: update <Florent Kermarrec>
    * 22310cc - phy: add initial Cyclone5 support <Florent Kermarrec>
    * 9cdb982 - phy/s7pciephy: rename external_phy to external_hard_ip <Florent Kermarrec>
    * 3b6cffd - frontend/wishbone: add qword_aligned parameter <Florent Kermarrec>
    * d191b1e - core: add endianness support <Florent Kermarrec>
    * 4df720a - examples/targets/dma: remove typo (dma connection is done internally in loopback mode) <Florent Kermarrec>
    * 14d852e - examples/targets/dma: remove soft reset, simplify crg, minor cleanups <Florent Kermarrec>
    * 64857af - phy/s7pciephy: improve presentation <Florent Kermarrec>
    * 55fa0d4 - phy/s7pciephy: remove pcie clk presence detection. <Florent Kermarrec>
    * f042273 - phy/s7pciephy: allow using external sources for the PHY. <Florent Kermarrec>
    * bd5d4dc - phy/s7pciephy: remove unnecessary reset on pcie clock domain <Florent Kermarrec>
    * ccfb201 - frontend/dma: update loop_status when request is sent <Florent Kermarrec>

 * litesata changed from b78a731 to 6fe4cce
    * 6fe4cce - examples/targets/bist: simplify analyzer <Florent Kermarrec>
    * 846bd62 - phy/a7sataphy: rework tx/rx_startup_fsm using liteiclink code <Florent Kermarrec>
    * 5e02ac9 - phy/a7sataphy: use proper transceiver name <Florent Kermarrec>
    * e63c8aa - examples/test/test_analyzer: use shorter import <Florent Kermarrec>
    * 319dd72 - examples/targets/bist: update <Florent Kermarrec>
    * df27cdf - examples/targets: add bist_nexys_video (still wip) <Florent Kermarrec>
    *   2ba5508 - Merge pull request timvideos#15 from enjoy-digital/artix7 <enjoy-digital>
    |\
    | * 0b254b0 - examples/make: remove platform option <Florent Kermarrec>
    | * e0fc55c - examples/targets/bist: revert kc705/genesys2 bist example <Florent Kermarrec>
    | * cabc908 - example: add led blinking on refclk, add startup fsm to analyzer <Florent Kermarrec>
    | * d16b495 - examples: add more debug, rx/tx leds not blinking (no clock? bad init?) <Florent Kermarrec>
    | * 1519dc3 - targets/bist: use 100 MHz clock, fix reset polarity <Florent Kermarrec>
    | * 1fe543f - phy/a7sataphy: integrate GTPQuadPLL <Florent Kermarrec>
    | * ca47e05 - examples/targets/bist: start artix7 testing with sata_gen1 <Florent Kermarrec>
    | * 1fc848e - examples: add nexys_video support <Florent Kermarrec>
    | * 9152729 - phy/a7sataphy: update parameters from wizard <Florent Kermarrec>
    | * ef5d0b9 - phy: add initial a7sataphy <Florent Kermarrec>
    | * 12b5085 - phy/k7sataphy: remove drp interface (not used) <Florent Kermarrec>
    | * 246487c - phy/k7sataphy: improve readibility <Florent Kermarrec>
    | * 41f4446 - phy/k7sataphy: make GTXE2_CHANNEL instance similar to gtx_7series in liteiclink <Florent Kermarrec>
    | * 27df062 - phy: replace trx_dw with data_width <Florent Kermarrec>
    | * d52c7b8 - phy/k7sataphy: remove ones <Florent Kermarrec>
    | * 1d1da98 - phy/k7sataphy: refactor gtxe2_channel instance <Florent Kermarrec>
    | * 10d6376 - phy: move k7 phy to a single k7sataphy file <Florent Kermarrec>
    * 7299fef - example/make.py: create the build directory when building the core if not existing <Florent Kermarrec>

 * litescope changed from c1d8bdf to 2474ce9
    * 2474ce9 - software/dump/common: change variable name for values2x loop (thanks keesj) <Florent Kermarrec>
    * 7f20aa4 - examples/make/build-core: create build directory if not existing <Florent Kermarrec>

 * litex changed from af52842f to ab1f5804
    * ab1f5804 - test/test_axi: remove litex.gen.sim import (was only useful for debug) <Florent Kermarrec>
    * 5318bcd3 - setup.py: add migen to install_requires <Florent Kermarrec>
    *   33d7cc5f - Merge pull request timvideos#198 from TomKeddie/tomk_20190610_artyspi <enjoy-digital>
    |\
    | * 5346c368 - boards/arty : Add directly connected spi clk pin to avoid need for STARTUPE2 <Tom Keddie>
    * | 38a2d89a - test/test_code8b10b: add test_coding <Florent Kermarrec>
    * | 8fdd5220 - test/test_prbs: add PRBSGenerator/Checker tests <Florent Kermarrec>
    * | 243d7c76 - soc/cores: add PRBS (Pseudo Random Binary Sequence) Generator/Checker <Florent Kermarrec>
    * | cfa952b0 - tools/litex_term: exit on 2 consecutive CTRL-C <Florent Kermarrec>
    * | 1c34b4a0 - cpu/vexriscv: update submodule <Florent Kermarrec>
    * | 79665873 - doc: add litex-hub logo <Florent Kermarrec>
    * | 442d7358 - doc: redesign new logo <Florent Kermarrec>
    * | 59118627 - doc: add new logo <Florent Kermarrec>
    * | 850b311d - cpu/vexriscv: update submodule <Florent Kermarrec>
    * | 755a2660 - build/sim: allow configuring verilator optimization level <Florent Kermarrec>
    * | 4b6ad8aa - build/sim: allow defining start/end cycles for tracing <Florent Kermarrec>
    * | ecb60f6e - build/sim: use -O0 for verilator compilation <Florent Kermarrec>
    * | c64129dc - soc/integration/soc_core: list rocket as supported CPU <Florent Kermarrec>
    * | ca4e7811 - software/bios: change prompt to "litex" in green. <Florent Kermarrec>
    * | 8d0f008a - integration/soc_core: improve readibility (add separators/comments) <Florent Kermarrec>
    * | 55ebcc00 - test/test_targets: add de10lite <Florent Kermarrec>
    * |   e545b15f - Merge pull request timvideos#196 from msloniewski/de10lite_support <enjoy-digital>
    |\ \
    | * | 04ce4790 - boards/targets: add target for de10lite platform <msloniewski>
    | * | f2a740d5 - boards/platforms: add de10lite Terasic platform support <msloniewski>
    | * | a826aaca - build/altera: Add possibility to turn off generation of .rbf file <msloniewski>
    * | |   77805a5e - Merge pull request timvideos#195 from antmicro/extend_generated_headers <enjoy-digital>
    |\ \ \
    | |/ /
    |/| |
    | * | 93b61a65 - integration/builder: generate flash_boot address to csv <Mateusz Holenko>
    | * | d0b019b1 - integration/builder: generate shadow_base address to mem.h and csv <Mateusz Holenko>
    |/ /
    * |   cb2d4372 - Merge pull request timvideos#193 from gsomlo/gls-memcpy-fix <enjoy-digital>
    |\ \
    | * | f88b85a3 - software/libbase: memcpy: simple, arch-width agnostic implementation <Gabriel L. Somlo>
    |/ /
    * |   42e9d097 - Merge pull request timvideos#192 from sutajiokousagi/pr_c99_types <Tim Ansell>
    |\ \
    | * | ab0b2cac - fix signed char type to be explicitly signed <bunnie>
    * | |   b0d35a49 - Merge pull request timvideos#191 from sergachev/master <Tim Ansell>
    |\ \ \
    | * | | db890736 - fix csr_name in add_csr() <Ilia Sergachev>
    | * | | 40cbe3a9 - fix interrupt_name <Ilia Sergachev>
    |/ / /
    * | | b300c321 - test/test_targets: add de2_115, de1soc <Florent Kermarrec>
    * | | 220e2bdc - boards/platform/arty: add Arty A7-100 variant <Florent Kermarrec>
    * | |   8e6ecfb9 - Merge pull request timvideos#189 from open-design/terasic-boards <enjoy-digital>
    |\ \ \
    | * | | 6cf1a814 - boards: add Terasic DE2-115 initial support <Antony Pavlov>
    | * | | 03725991 - boards: add Terasic DE1-SoC Board support <Antony Pavlov>
    * | | |   9682189b - Merge pull request timvideos#190 from sutajiokousagi/pr_c99_types <Tim Ansell>
    |\ \ \ \
    | |/ / /
    |/| / /
    | |/ /
    | * | 200d413d - update stdint.h to include c99 types <bunnie>
    |/ /
    * |   a48858f8 - Merge pull request timvideos#188 from gsomlo/gls-csr-cleanup <enjoy-digital>
    |\ \
    | * | 273a3ea1 - soc/integration/cpu_interface: improve code legibility <Gabriel L. Somlo>
    |/ /
    * | 08a811b1 - soc/interconnect/gearbox: add msb_first/lsb_first order <Florent Kermarrec>
    * | 675f7830 - boards/targets/arty: generate 25MHz ethernet clock with S7PLL <Florent Kermarrec>
    * |   d7b00c8c - Merge pull request timvideos#187 from open-design/indent <Tim Ansell>
    |\ \
    | * | 26e6355f - litex/boards/targets: don't use tab for indentation <Antony Pavlov>
    |/ /
    * | 51095112 - soc/interconnect/axi: add round/robin arbitration between writes/reads <Florent Kermarrec>
    * | 0fb6342f - travis: update RISC-V toolchain <Florent Kermarrec>
    * | 961101d8 - bios/irc: remove compilation workaround <Florent Kermarrec>
    * | cd543b29 - README: update RISC-V toolchain <Florent Kermarrec>
    * | 7e837bf1 - .gitmodules/rocket: switch to https://github.com/enjoy-digital/rocket-litex-verilog <Florent Kermarrec>
    * | 712977a0 - software/bios/isr.c: workaround compilation issue (need to be fixed) <Florent Kermarrec>
    * | 28ba8b32 - soc/integration/soc_core: revert default mem_map (do specific RocketChip remapping for now) <Florent Kermarrec>
    * | cf369c43 - boards/targets: revert default sys_clk_freq on nexys4ddr/versa_ecp5 (but add parameter to configure it) <Florent Kermarrec>
    * |   aa640f29 - Merge pull request timvideos#186 from gsomlo/gls-rocket <enjoy-digital>
    |\ \
    | * | 019fd940 - fixup: generated-verilog submodule for experimental Rocket support <Gabriel L. Somlo>
    | * | 1a530cf2 - soc/cores/cpu/rocket: Support for 64-bit RocketChip (experimental) <Gabriel L. Somlo>
    |/ /
    * |   3de49118 - Merge pull request timvideos#185 from gsomlo/gls-sim-sdram <enjoy-digital>
    |\ \
    | |/
    |/|
    | * e90caa86 - tools/litex_sim: restore functionality of '--with-sdram' option <Gabriel L. Somlo>
    |/
    *   3a72688b - Merge pull request timvideos#183 from xobs/usb-to-0x43 <enjoy-digital>
    |\
    | * 014c9505 - remote: usb: print "access denied" error <Sean Cross>
    | * faf6554c - remote: usb: use 0x43/0xc3 for packet header <Sean Cross>
    |/
    * 10670e22 - soc/cores/minerva: update to latest <Florent Kermarrec>
    *   a3134f13 - Merge pull request timvideos#182 from gsomlo/gls-nexys4-eth-fixup <enjoy-digital>
    |\
    | * 5707bdc0 - boards/nexys4ddr: ethernet support fix-up <Gabriel L. Somlo>
    |/
    *   0a8699f1 - Merge branch 'master' of http://github.com/enjoy-digital/litex <Florent Kermarrec>
    |\
    | * 1ea22d49 - software/include/base/csr-defs.h: add specific CSR_IRQ_MASK/PENDING for Minerva <Florent Kermarrec>
    * | 526ba1b1 - soc_core: remove csr_expose and add add_csr_master method <Florent Kermarrec>
    |/
    * f2570701 - software/bios/boot: remove specific linux commands (not needed with device tree) <Florent Kermarrec>
    * 938d00c2 - boards/targets/de0nano: reduce to 50MHz sys_clk, simplify CRG <Florent Kermarrec>
    * 11838bae - platforms/de0nano: change serial pins (put then next to the GND pin) <Florent Kermarrec>
    * eb6fa458 - cpu/vexriscv/core: update <Florent Kermarrec>
    * 0cad80e9 - cpu/vexriscv: update submodule (new linux variant) <Florent Kermarrec>
    * 5f6e7874 - boards/nexys4ddr: add ethernet support (RMII 100Mbps) <Florent Kermarrec>
    * 0ba1cb87 - boards/targets/netv2: +x <Florent Kermarrec>
    * 2f2b9b31 - soc/cores: remove cordic <Florent Kermarrec>
    * 6e4ac1c4 - LICENSE: clarify <Florent Kermarrec>
    * 67159349 - soc/interconnect: remove axi_lite <Florent Kermarrec>
    * 745d83a3 - boards: add initial NeTV2 support (clocks, leds, dram, ethernet) <Florent Kermarrec>
    * a49d170a - soc/integration/soc_sdram: simplify/fix main_ram_size computation using new databits value of the phy <Florent Kermarrec>
    * 7445b9e2 - soc/integration/soc_core: allow user to defined internal csr/interrupts <Florent Kermarrec>
    * f333abcf - boards/targets: use new add_csr method <Florent Kermarrec>
    * d76a2c7d - tools/litex_sim: add uart csr (required when with_uart=False with new add_csr method) <Florent Kermarrec>
    * b6be534c - soc/integration/soc_core: rework csr assignation/reservation <Florent Kermarrec>
    * 3f09af6d - boards/targets: declare ethmac interrupt with new add_interrupt method <Florent Kermarrec>
    *   2abb3e80 - Merge branch 'master' of http://github.com/enjoy-digital/litex <Florent Kermarrec>
    |\
    | *   c11eb4b5 - Merge pull request timvideos#179 from gsomlo/gls-xtra-addrlen <enjoy-digital>
    | |\
    | | * c264a009 - soc/integration/cpu_interface: more arch-specific address size fixes <Gabriel L. Somlo>
    | |/
    * | 47dc8758 - integration/soc_core: rework interrupt assignation/reservation <Florent Kermarrec>
    * | 3ee9ce05 - test/test_targets: fix test_ulx3s name <Florent Kermarrec>
    * | 435cdad0 - boards/targets: fix ulx3s/versa_ecp5 build <Florent Kermarrec>
    * | 8caa38bc - cpu: add `reserved_interrupts` property <Mateusz Holenko>
    * | ff517915 - boards/targets: make sys_clk_freq a parameter <Florent Kermarrec>
    |/
    * a8cbe4ad - boards/targets/minispartan6: for now revert experimental s6pll clocking <Florent Kermarrec>
    * 6fcbf10e - boards/plarforms/minispartan6: default to xc6slx25 <Florent Kermarrec>
    * b7e37133 - bios/boot/ update linux memory mapping <Florent Kermarrec>
    * 190ff89a - tools/litex_term: add json support to load images to memory, allow passing speed as float <Florent Kermarrec>
    *   a50aff2c - Merge pull request timvideos#178 from daveshah1/vexriscv_linux_yosys <enjoy-digital>
    |\
    | * a048ba47 - vexriscv: Fix some floating signals <David Shah>
    |/
    * fcd518b5 - bios/boot: add specific flash_boot for linux with vexriscv <Florent Kermarrec>
    * 1ba1ad9a - bios/boot: rename MM_RAM to EMULATOR_RAM <Florent Kermarrec>
    * fbb24720 - soc/get_mem_data: add direct support for regions <Florent Kermarrec>
    * 0714816f - soc/interconnect/axi: add AXI2AXILite converter and use it in  AXI2Wishbone <Florent Kermarrec>
    * c6d0d234 - soc/interconnect/axi: add AXI Lite definition <Florent Kermarrec>
    * 9fab4752 - soc/interconnect/axi: add comment on axi signas that are present but not used <Florent Kermarrec>
    * 59890763 - cores/cpu/vexriscv: add VexRiscvTimer and use it for the linux variant <Florent Kermarrec>
    * 21bf1038 - bios/boot: add liftoff banner just before booting <Florent Kermarrec>
    * 8f4685b3 - bios/boot/netboot: only get boot.bin as default, add linux_vexriscv netboot config <Florent Kermarrec>
    * 6cf1ff09 - soc/interconnect/axi: connect axi.ar/aw when selecting write or read <Florent Kermarrec>
    * 6affc56a - soc/interconnect/axi: wishbone address shift is not always 2, make it generic <Florent Kermarrec>
    * 698bc882 - soc/interconnect/wishbone: allow setting adr_width (default to 30) <Florent Kermarrec>
    * 4dccb8a9 - soc/interconnect/axi/AXI2Wishbone: add buffer on axi command to be sure command is accepted before response is sent <Florent Kermarrec>
    * 9f8f0eb1 - build/sim: update tapcfg <Florent Kermarrec>
    *   2515c7b0 - Merge pull request timvideos#176 from gsomlo/gls-ulong-addr <enjoy-digital>
    |\
    | * 5c2b8685 - software: use "unsigned long" for address values, also 8-byte alignment <Gabriel L. Somlo>
    |/
    * 74d37465 - test/test_targets: comment bad variant tests for now <Florent Kermarrec>
    * 5c1d9805 - soc/interconnect/axi: add burst support to AXI2Wishbone <Florent Kermarrec>
    * 6de27135 - soc/interconnect/axi: add capabilities to AXIBurst2Beat and simplify/optimize <Florent Kermarrec>
    * 305b8879 - integration/soc_core: use cpu name as cpu-type for all cpus (mor1kx was instanciated with or1k) <Florent Kermarrec>
    * 4e50f36b - build/tools: add deprecated_warning <Florent Kermarrec>
    * b40d1b73 - cpu_interface: default to gcc for all cpus unless told otherwise (mor1kx default was clang) <Florent Kermarrec>
    * dbb71af1 - cpu: use property methods to return name, endianness, gcc triple/flags, linker output format <Florent Kermarrec>
    * d828c3a5 - cpu: integrate nmigen version of Minerva, add submodule <Florent Kermarrec>
    * 2c3c6bdf - Updating documents from LiteX BuildEnv Wiki <Florent Kermarrec>
    * bf27869a - fix vexriscv build <Kurt Kiefer>
    *   2d5bae3d - Merge pull request timvideos#175 from mithro/cpu-docs <enjoy-digital>
    |\
    | * 5cbc5bc1 - Adding testing of cpu variants. <Tim 'mithro' Ansell>
    | * 71a83731 - Work with no `cpu_variant` provided. <Tim 'mithro' Ansell>
    | * 65650919 - Updating documents from LiteX BuildEnv Wiki <Tim 'mithro' Ansell>
    | * a43de819 - Updating documents from LiteX BuildEnv Wiki <Tim 'mithro' Ansell>
    | * 39c579ba - Standardize the `cpu_variant` strings. <Tim 'mithro' Ansell>
    | * e42de8fe - docs: Adding script to pull useful docs from LiteX BuildEnv's wiki. <Tim 'mithro' Ansell>
    * | 3a2e2836 - .gitmodules: use our VexRiscv-verilog <Florent Kermarrec>
    |/
    * 78c09125 - soc/integration/soc_core: fix get_mem_data when not file is not multiple of 4 bytes <Florent Kermarrec>
    * 0175f86c - soc/integration/soc_core: fix get_mem_data for json files <Florent Kermarrec>
    * 4443b507 - soc/integration/soc_core: add integrated_sram_init <Florent Kermarrec>
    * f27084c6 - soc/integration/cpu_interface: fix banner in get_mem_header <Florent Kermarrec>
    *   5ec99d94 - Merge pull request timvideos#173 from gsomlo/gls-git-revision <enjoy-digital>
    |\
    | * d21cba2f - build: handle exceptional case when litex/migen not deployed as git repo <Gabriel L. Somlo>
    |/
    * 27fbb814 - tools/remote/csr_builder: allow comments in csv file and cleanup <Florent Kermarrec>
    * e8f3c491 - software/libnet/microudp: rearrange send_packet, add comments and remove txlen padding <Florent Kermarrec>
    * 44e0cdda - software/libnet/microudp: speed-up ARP by changing timeout/tries <Florent Kermarrec>
    * 3ee78a5b - build/tools: fix typo <Florent Kermarrec>
    * f0fe9f3c - setup.py: add short names for tools <Florent Kermarrec>
    * 9ded2eb2 - tools/litex_term: change TERM prompt to LXTERM <Florent Kermarrec>
    * 475deb51 - build: add migen and litex git revision to generated file <Florent Kermarrec>
    * 8b5cf295 - build/tools: git_revision is not doing what we want, return "--------" for now <Florent Kermarrec>
    * 228f2867 - litex_setup: revert default install behaviour but add --user support <Florent Kermarrec>
    *   9fbbf928 - Merge pull request timvideos#171 from keesj/develop_as_user <enjoy-digital>
    |\
    | * 24bdb648 - Install development packages in the user directory <Kees Jongenburger>
    * | 0f60ec35 - tools/litex_server: fix comms import <Florent Kermarrec>
    * | 68f12495 - soc/integration: also add sha-1/date to generated software files <Florent Kermarrec>
    * | 42574122 - build: add sha-1/date to generated verilog, change git_version to git_revision <Florent Kermarrec>
    |/
    * f7c0b118 - test/test_targets: cover all platforms <Florent Kermarrec>
    * 818dfae1 - boards/platforms/ulx3s: fix default clock <Florent Kermarrec>
    * 17b6164c - boards/platforms/sp605: apply same simplifications than on others platforms <Florent Kermarrec>
    * 24bf0293 - boards/platforms: add SP605 <Michael Betz>
    * 10cf0fde - cores/cpu/vexriscv: fix wrong revert <Florent Kermarrec>
    * d2ad1441 - targets/ac701: cleanup and make it similar to others targets. <Florent Kermarrec>
    * a24bf72f - targets/xilinx: remove keep attribute on clock going to idelayctrl <Florent Kermarrec>
    * ea8dbff8 - boards/platform/ac701: add proper copyright, cleanup to be similar to others platforms <Florent Kermarrec>
    * 0122982e - boards/platforms/kc705: provide only one default programmer as others platforms <Florent Kermarrec>
    * 89a59026 - boards: Xilinx ac701 dev board support <Vamsi K Vytla>
    * 88b882c7 - build/xilinx/ise.py: write .v file for post synthesis sim <Michael Betz>
    * 7396ebbb - build/xilinx/programmer: cleanup XC3SProg position parameter <Florent Kermarrec>
    * f579cbc6 - build/xilinx/programmer: add position parameter to XC3SProg <Michael Betz>
    * fb4f8818 - .gitignore: ignore tilde files <Vamsi K Vytla>
    * 535d8672 - targets/minispartan6: use S6PLL in CRG <Florent Kermarrec>
    * 40342404 - cores/clock: add divclk_divide_range on S6PLL/S6DCM <Florent Kermarrec>
    * 0d282f38 - cores/clock: use common XilinxClocking class for all Xilinx clocking modules <Florent Kermarrec>
    * 83699ea0 - cores/clock: add initial Spartan6 PLL/DCM support <Michael Betz>
    * eff141da - build: add git version (sha-1) used to create the scripts <Florent Kermarrec>
    * cc141a64 - build: scripts are generated by LiteX <Florent Kermarrec>
    * 115c842e - build/xilinx/vivado: cleanup pull request timvideos#170 <Florent Kermarrec>
    *   3b24b8d5 - Merge pull request timvideos#170 from ldoolitt/master <enjoy-digital>
    |\
    | * fda18fd6 - build/xilinx/vivado: only try Xilinx setup if vivado is not already in the path <Larry Doolittle>
    |/
    * 7d278854 - global: switch to VexRiscv as the default CPU <Florent Kermarrec>
    * 28d80bd6 - ci: fix test_targets/test_simple <Florent Kermarrec>
    * b7f53fb9 - test: remove waveforms generation <Florent Kermarrec>
    * e98ac680 - travis: simplify, enable and add RISC-V toolchain to build targets <Florent Kermarrec>
    * 8c789970 - boards/platforms: add separators, cleanup imports <Florent Kermarrec>
    * cb8c26d1 - boards/platforms: provide only one default programmer per platform. <Florent Kermarrec>
    * e1d202df - boards/platforms/kc705: only keep Vivado support <Florent Kermarrec>
    * 53c7be6e - boards: always define timing constraints the same way (1e9/freq_mhz) <Florent Kermarrec>
    * 02ffbed5 - boards/targets/ulx3s: allow running test_targets on it <Florent Kermarrec>
    * 5a1925df - boards/targets: add keep attribute directly in crg <Florent Kermarrec>
    *   67a79d7c - Merge pull request timvideos#167 from xobs/network-flag-check <enjoy-digital>
    |\
    | * f71b8d4f - litex_server: check socket flags exist before using them <Sean Cross>
    |/
    * 9ee6c35b - tools: move from litex.soc.tools to litex.tools and fix usb.core import <Florent Kermarrec>
    *   49fd93ae - Merge pull request timvideos#165 from xobs/vexriscv-cpu-reset-address <enjoy-digital>
    |\
    | *   c780fb22 - Merge branch 'master' of https://github.com/enjoy-digital/litex <Sean Cross>
    | |\
    | * | e2cf45b8 - cpu: vexriscv: allow cpu_reset_address to be overridden <Sean Cross>
    * | |   ca6065a6 - Merge pull request timvideos#164 from xobs/litex-usb-server <enjoy-digital>
    |\ \ \
    | * | | c6918364 - utils: litex_server: add usb support <Sean Cross>
    | * | | 9dd59d63 - tools: remote: add usb communications protocol <Sean Cross>
    * | | | 9cbed91b - soc/interconnect/axi: add AXIBurst2Beat <Florent Kermarrec>
    * | | | 5a8115d9 - soc/interconnect/avalon: add description <Florent Kermarrec>
    | |_|/
    |/| |
    * | | fa956086 - soc/integration/soc_zynq: fix HP0 connections <Florent Kermarrec>
    * | | a78ca2de - build/xilinx/vivado: only set library for vhdl files (not supported for verilog/system-verilog) <Florent Kermarrec>
    |/ /
    * | a92e90b2 - soc/interconnect: add avalon with converters to/from native streams <Florent Kermarrec>
    * |   d860eeea - Merge pull request timvideos#162 from antmicro/full-conf-vexriscv <enjoy-digital>
    |\ \
    | * | 40de01bc - vexriscv: Add full and full_debug CPU variant <Joanna Brozek>
    * | |   ce81a39c - Merge pull request timvideos#163 from gsomlo/gls-verilated-cmdargs <enjoy-digital>
    |\ \ \
    | |/ /
    |/| |
    | * | e1683078 - build/sim/core: Initialize Verilator commandArgs <Gabriel L. Somlo>
    |/ /
    * | 017147c6 - build/altera: switch to sdc constraints, add add_false_path_constraints method <Florent Kermarrec>
    * | 1275e2f1 - build/xilinx/vivado: set quiet property on MultiReg/AsyncResetSynchronizer constraints <Florent Kermarrec>
    * | c252972b - soc/cores/clock: add divclk_divide/vco_margin support on S7/Ultrascale <Florent Kermarrec>
    * | f986974d - soc/cores/clock: improve presentation <Florent Kermarrec>
    * | 538ca59a - build/xilinx/vivado: round period constraints to lowest picosecond <Florent Kermarrec>
    * |   66a74b15 - Merge pull request timvideos#161 from enjoy-digital/litex_server_arguments <enjoy-digital>
    |\ \
    | * | a2bc4bb7 - litex_server: set socket.SO_REUSEPORT to avoid waiting 60s in case of unclean termination <Florent Kermarrec>
    | * | be99083e - litex_server: add message and exit when mandarory arguments are missing. <Florent Kermarrec>
    | * | db11aec9 - litex_server: allow setting bind port, remove auto-incrementing on bind_port <Florent Kermarrec>
    | * | 76bc5785 - litex_server: refactor parameters and to allow setting bind address <Florent Kermarrec>
    |/ /
    * | 13a76ec7 - software/libnet/microudp: simplify txbuffer managment <Florent Kermarrec>
    * | 3441eb05 - software/libnet/microudp: cleanup eth_init <Florent Kermarrec>
    * | 92a79c6d - software/libnet/microudp: simplify rxbuffer managment <Florent Kermarrec>
    * | fdeff7f6 - software/libnet/microudp: set raw frame size to ETHMAC_SLOT_SIZE <Florent Kermarrec>
    * | 1569e2e0 - software/libnet: remove use of ethmac_mem.h <Florent Kermarrec>
    * | c7ac9676 - bios/sdram: add __attribute__((unused)) on cdelay <Florent Kermarrec>
    * | 7e53bff3 - litex_setup: add litesata <Florent Kermarrec>
    * | 792245f1 - boards/targets/kcu105: add Ethernet (with 1Gbps SFP adapter) <Florent Kermarrec>
    * | f8dcdb70 - software/libnet: add #ifdef on eth_init <Florent Kermarrec>
    * |   e475cfbb - Merge pull request timvideos#158 from vbuitvydas/altera-contrib <enjoy-digital>
    |\ \
    | * | 04939990 - litex/build/altera/quartus: changes to make top level assigment in .qsf file with build name <vytautasb>
    | * | 8558065f - litex/build/altera/common: added reset synchronizer <vytautasb>
    |/ /
    * | 866fa344 - integration/soc_zynq: fix missing SoCCore.do_finalize <Florent Kermarrec>
    * | 794c3c58 - integration/soc_zynq: add add_hp0 method <Florent Kermarrec>
    * | 38d404c3 - integration/soc_zynq: use add methods to add optional peripherals <Florent Kermarrec>
    * | 7375856b - integration/soc_zynq: connect axi signals that were missing <Florent Kermarrec>
    * | b15fd9d8 - interconnect/axi: add missing axi signals <Florent Kermarrec>
    * |   f95748d1 - Merge pull request timvideos#157 from CBJamo/master <enjoy-digital>
    |\ \
    | * | 1f0b3f81 - Add ifdef check for MAIN_RAM_SIZE <Caleb Jamison>
    |/ /
    * | f452d3e9 - README: bump copyright year <Florent Kermarrec>
    * | dd214d2d - bios/main: align SoC info, show CPU speed on CPU line, show L2 <Florent Kermarrec>
    * | 6599f7bb - bios/main: move sdrinit <Florent Kermarrec>
    * | b92b89ab - bios/main: print boot sequence only if sdr_ok <Florent Kermarrec>
    * | f4369c8f - bios/main: remove csr functions (not used and only supported by lm32), improve help presentation <Florent Kermarrec>
    * | 66dffb70 - software/bios: improve readibility, add soc informations <Florent Kermarrec>
    * |   e8559990 - Merge pull request timvideos#156 from gsomlo/gls-axi-width <enjoy-digital>
    |\ \
    | * | 449632e4 - soc/interconnect/axi: data/address length cleanup <Gabriel L. Somlo>
    |/ /
    * | 552b0243 - soc/interconnect/axi: remove dead code (thanks gsomlo) <Florent Kermarrec>
    * |   b682dacd - Merge pull request timvideos#154 from daveshah1/yosys_xilinx_edif <enjoy-digital>
    |\ \
    | * | 57e1ccd5 - build/xilinx: Update Yosys write_edif parameters <David Shah>
    * | | fd7ed6c1 - utils/litex_sim: fix main_ram_size <Florent Kermarrec>
    * | | 3f386dad - soc_core/get_mem_data: add json support <Florent Kermarrec>
    * | | 7bc13ba8 - build/microsemi/libero_soc: add linux build script support <Florent Kermarrec>
    * | | 7b88980d - vexriscv: allow user to use an external variant <Florent Kermarrec>
    * | | b04a756a - vexriscv/core: fix min variant <Florent Kermarrec>
    * | | a549f094 - utils/litex_sim: handle cpu_endianness for rom-init/ram-init <Florent Kermarrec>
    * | | 411bca79 - utils/litex_sim: increase default integrated_main_ram_size to 256MB, automatically boot on main_ram when ram_init is specified <Florent Kermarrec>
    * | |   7ec3ed4d - Merge pull request timvideos#153 from railnova/fix_utils <enjoy-digital>
    |\ \ \
    | * | | aed2e9b4 - [fix] utils was not installed from pip <chmousset>
    | |/ /
    * | |   3543b567 - Merge pull request timvideos#152 from gsomlo/gls-trellis-svf <enjoy-digital>
    |\ \ \
    | |/ /
    |/| |
    | * | b014c719 - build/lattice/trellis: also generate bitstream in svf format <Gabriel L. Somlo>
    |/ /
    * | 317dba83 - software/bios/sdram: use specific ERR_DDRPHY_BITSLIP/NMODULES computation <Florent Kermarrec>
    * | 7de1fe51 - targets/versa_ecp5: update ECP5DDRPHY on BaseSoC, add EthernetSoC <Florent Kermarrec>
    * | ca63db40 - bios/sdram: use burstdet detection for ECP5DDRPHY init <Florent Kermarrec>
    |/
    *   2ebfab5e - Merge pull request timvideos#150 from daveshah1/trellis_bus_fixes <enjoy-digital>
    |\
    | * ebe8f600 - lattice/common: Fix tristate buses with Trellis <David Shah>
    |/
    * 935f3a53 - boards/ulx3s: add device selection parameter <Florent Kermarrec>
    * e6f97e08 - targets/ulx3s: use AsyncResetSynchronizer and derivate sys_clk/sys_clk_ps constraints from clk25 <Florent Kermarrec>
    * 5ef28bdf - build/lattice/trellis: add package support <Florent Kermarrec>
    * 1b34c07d - build/lattice/trellis: basecfg now integrated in nextpnr <Florent Kermarrec>
    * 7e995eb4 - boards/targets/ulx3s: allow building with diamond or trellis <Florent Kermarrec>
    * 4bf789ea - soc/software/bios/boot: add vexriscv workaround <Florent Kermarrec>
    * 1fd81c28 - soc/integration: add initial SoCZynq SoC <Florent Kermarrec>
    * 3c527dcb - soc/interconnect: add initial axi code with bus definition and AXI2Wishbone <Florent Kermarrec>
    * ed257879 - test: add test_axi_lite (with test code from soc/interconnect/axi_lite lightly modified) <Florent Kermarrec>
    * 4aa07f2a - soc/interconnect: rename axi to axi_lite <Florent Kermarrec>
    * 6a4c133c - test: add basic test_csr <Florent Kermarrec>
    *   c9f9e237 - Merge pull request timvideos#149 from daveshah1/versa_trellis <enjoy-digital>
    |\
    | * ff7e0fab - versa_ecp5: Add option to build with Trellis <David Shah>
    | * 024b41c5 - trellis: Add LPF frequency constraints and remove -nomux <David Shah>
    * | e38dfd99 - soc/software/sdram: fix compilation on ultrascale <Florent Kermarrec>
    |/
    * 5f29a12e - targets/versa_ecp5: integrate DDR3 <Florent Kermarrec>
    * 3dd529e4 - soc/software/bios/sdram: add ECP5 support <Florent Kermarrec>
    * 2fd6d0e7 - soc/software/bios/sdram: improve write_level robustness <Florent Kermarrec>
    * 36772b75 - soc/software/bios/sdram: improve sdrlevel readibility <Florent Kermarrec>
    * 6a980781 - soc/software/bios/sdram: add helpers for rst/inc of delays <Florent Kermarrec>
    *   dad7b292 - Merge pull request timvideos#148 from daveshah1/versa_remove_n <enjoy-digital>
    |\
    | * 321dd8fc - versa_ecp5: Remove negative diff IO pins <David Shah>
    |/
    * c03b1ad1 - platforms/versa_ecp5: add ddram pins <Florent Kermarrec>
    * ff155a47 - soc/tools/remote/comm_uart: be sure to flush in waiting bytes before read and write <Florent Kermarrec>
    * d3ecdd99 - soc/cores/clock: add actual clk_freqs to config <Florent Kermarrec>

 * migen changed from 0.6.dev-241-gafe4405 to 0.6.dev-283-g562c046
    * 562c046 - Correct URL of logo Signed-off-by: Chipmuenk <mail@chipmuenk.de> <Chipmuenk>
    * db7ce84 - updated packaging infos <Chipmuenk>
    * a9e5029 - platforms: add de10lite support <msloniewski>
    * a69e1fd - altera/quartus: fix generated build script <msloniewski>
    * 1b804d7 - platforms: add max1000 support <msloniewski>
    * bc90344 - metlino: v1.0rc5 <Sebastien Bourdeauducq>
    * 9031bfe - metlino: add VHDCI EEM carrier connector <Sebastien Bourdeauducq>
    * 83b209e - metlino: add LEDs, I2C, Si5324, transceivers <Sebastien Bourdeauducq>
    * 4289590 - metlino: set bitstream properties <Sebastien Bourdeauducq>
    * aea0841 - metlino: add gth_clk200 and port0 <Sebastien Bourdeauducq>
    * 7299f4e - metlino: add spiflash <Sebastien Bourdeauducq>
    * 6815691 - metlino: use same SDRAM constraints as Sayma <Sebastien Bourdeauducq>
    * 42fe506 - metlino: update pins to 1.0rc4 <Sebastien Bourdeauducq>
    * 54d666d - Lattice iCE40: add comment on the polarity of differential I/O pairs <airwoodix>
    * 090ece7 - Lattice iCE40: pass positive pin to SB_IO in DifferentialInput <airwoodix>
    * ee3508b - Revert e43cd74 <airwoodix>
    * e43cd74 - Lattice iCE40: fix DifferentialInput polarity <airwoodix>
    * e6d02be - humpback: fix serial pinouts (crossover cables) <airwoodix>
    * c8cae39 - Lattice iCE40: implement DifferentialInput <Etienne Wodey>
    * a6f9cbd - Add Sinara Humpback platform (timvideos#177) <Étienne Wodey>
    * 4e66a71 - Fix `-vlgincdir` for xst. <Tim 'mithro' Ansell>
    * edcadbc - sayma_rtm2: si5324_clkout -> cdr_clk_clean <Sebastien Bourdeauducq>
    * 49b9d8a - sayma_amc2: add rtm_amc_link <Sebastien Bourdeauducq>
    * 0080bed - sayma_rtm2: add AFE test pins <Sebastien Bourdeauducq>
    * 032340d - sayma_rtm2: add rtm_amc_link <Sebastien Bourdeauducq>
    * 8bf0ab8 - sayma_rtm2: fix clk50 IOStandard <Sebastien Bourdeauducq>
    * 5dc0b23 - sayma_rtm: select correct speed grade and IDCODE for v2 <Sebastien Bourdeauducq>
    * 98a075c - sayma_rtm: update for v2.0rc4 <Sebastien Bourdeauducq>
    * cd71a2a - fix permissions <Sebastien Bourdeauducq>
    * 5a843a1 - sayma_amc: update gth_clk200, add DDMTD signals <Sebastien Bourdeauducq>
    * 2154882 - sayma_amc: OVERTEMPPOWERDOWN is called OVERTEMPSHUTDOWN on Ultrascale <Sebastien Bourdeauducq>
    * 3773947 - sayma_amc: si5324_clkout -> cdr_clk_clean <Sebastien Bourdeauducq>
    * 383512b - sayma_amc2: update to v2.0rc4 <Sebastien Bourdeauducq>
    * 936732f - add sayma_rtm2 <Sebastien Bourdeauducq>
    * d482b93 - sayma_amc2: add ddrXX_clk <Sebastien Bourdeauducq>
    * 25646d4 - sayma_amc2: enable OVERTEMPPOWERDOWN <Sebastien Bourdeauducq>
    * 9fd7a48 - remove Roach <Sebastien Bourdeauducq>
    * 9d90900 - sayma_amc: use LVDS for serwb <Sebastien Bourdeauducq>
    * 3da7113 - sayma_amc: fix aux_clk I/O standard <Sebastien Bourdeauducq>
    * 9a25f90 - sayma_amc: fix v2 platform name <Sebastien Bourdeauducq>
    * 7765238 - add Sayma AMC v2 platform <Sebastien Bourdeauducq>
    * ae42105 - migen: replace `collections` with `collections.abc` as necessary (timvideos#176) <Sean Cross>

Full submodule status
--
 dc763d7b1a95a74c6d109a03e34ba45315212195 edid-decode (heads/master)
 1c21ee44a2b3936f62e4b43f2bcbf63ce9404691 flash_proxies (heads/master)
 7fbe0b712ceda5bcc526a55a5c9c071eb21eb90e litedram (heads/master)
 2424e62bf9637c2623b627a56aca7a3f90349e92 liteeth (heads/master)
 de6cd01d3f158387337bf4f47fd5a351ec2c3267 litepcie (heads/master)
 6fe4cceaab77d6a117fa539f461b3ae9ca7e668e litesata (heads/master)
 2474ce9db23e4d06bff4bbeacf0051efa3042f37 litescope (heads/master)
 0a9110f901182a1233cc4e64b6e39175f6784621 liteusb (heads/master)
 98e145fba8c25394e9958bad67e2a457d145127e litevideo (heads/master)
 ab1f58047064c459475970d11e540c6e0e5367a8 litex (heads/master)
 562c0466443f859d6cf0c87a0bb50db094d27cf4 migen (0.6.dev-283-g562c046)
mateusz-holenko added a commit to antmicro/litex-buildenv that referenced this pull request Jun 14, 2019
@mateusz-holenko
Updating submodules.
403f459 
 * edid-decode changed from 6def7bc to 15df4ae
    * 15df4ae - Makefile: add CPPFLAGS <Hans Verkuil>
    * dc763d7 - Update email addresses <Hans Verkuil>
    * 726576d - edid-decode: add CTA-861.4/5 support <Hans Verkuil>

 * flash_proxies changed from a628956 to 1c21ee4
    * 1c21ee4 - README: update <Robert Jördens>

 * litedram changed from d89b171 to 67de3ce
    *   67de3ce - Merge pull request timvideos#85 from antmicro/fix_databits <enjoy-digital>
    |\
    | * 24851c9 - PhySettings: set missing databits parameter for S6QuarterRateDDRPHY <Mateusz Holenko>
    * | fef5303 - test: clean test_downconverter/test_upconverter (thanks sb0) <Florent Kermarrec>
    |/
    *   7fbe0b7 - Merge pull request timvideos#84 from open-design/is42s16320 <enjoy-digital>
    |\
    | * 5c66547 - modules: SDRAM: add IS42S16320 support <Antony Pavlov>
    |/
    * 8e2df17 - modules: fix tRFC change on MT16KTF1G64HZ <Florent Kermarrec>
    * bc88cfa - modules: allow tRFC to be defined in ck or ns, fix some DDR3/DDR4 definitions (thanks @ambrop72 for the review) <Florent Kermarrec>
    * fbd7ae3 - modules: make IS43TR16128B consistent with others SDRAMModules <Florent Kermarrec>
    *   02448a3 - Merge pull request timvideos#83 from ambrop72/IS43TR16128B_125K <enjoy-digital>
    |\
    | * d108970 - modules/ddr3: add IS43TR16128B_125K <Ambroz Bizjak>
    |/
    *   da68e21 - Merge pull request timvideos#82 from gsomlo/gls-expose-csr <enjoy-digital>
    |\
    | * 65451f4 - examples/litedram_gen: allow direct access to CSR (I/O) registers <Gabriel L. Somlo>
    |/
    * 50e1d47 - PhySettings: add databits to allow SoC to compute memory size more easily <Florent Kermarrec>
    * b93412b - examples: remove verilog simulation <Florent Kermarrec>
    * a7e46bb - example/litedram_gen: reserve_nmi_interrupt no longer exists <Florent Kermarrec>
    *   094fc2e - Merge pull request timvideos#79 from gsomlo/gls-ulong-addr <enjoy-digital>
    |\
    | * 54d3312 - sdram_init: use "unsigned long" for address values <Gabriel L. Somlo>
    |/
    * 3caaa2e - common/tXXDController: revert Yosys workarounds <Florent Kermarrec>
    * 44bbb93 - phy: add copyrights <Florent Kermarrec>
    * 6ddc2c8 - README: update <Florent Kermarrec>
    * 9190a76 - travis: simplify and add RISC-V toolchain to run examples <Florent Kermarrec>
    * e824288 - frontend/axi: move AXIBurst2Beat to LiteX <Florent Kermarrec>
    * be269da - frontend/axi: use definitions from LiteX <Florent Kermarrec>
    * e81b5a1 - sdram_init: set __attribute__((unused)) on command_px to avoid compilation warning <Florent Kermarrec>
    * c4161cf - examples: update sim <Florent Kermarrec>
    * 201a0e2 - test/test_examples: add nexys4ddr <Florent Kermarrec>
    * 69afaf5 - common: add separators, reorganize a bit <Florent Kermarrec>
    * 0bc241c - phy/ecp5ddrphy: use inline comments on ECP5DDRPHYInit <Florent Kermarrec>
    * c65ff97 - phy/ecp5ddrphy: simplify ECP5DDRPHYInit, integrate it in the PHY, add burstdet registers <Florent Kermarrec>
    * 4274db8 - common/TXXDcontroller: fix for compatibility with Yosys and vendor tools <Florent Kermarrec>
    * a74d5c9 - common/TXXDcontroller: set ready default value to 1 with self.comb instead of reset value <Florent Kermarrec>
    *   cec35f3 - Merge pull request timvideos#77 from daveshah1/ecp5_75MHz <enjoy-digital>
    |\
    | * fa26dcd - ecp5ddrphy: Shift read position forwards to fix higher frequencies <David Shah>
    |/
    *   6715c1b - Merge pull request timvideos#76 from daveshah1/trellis_io <enjoy-digital>
    |\
    | * 691d930 - ecp5ddrphy: Use triples for inputs to fix build with TRELLIS_IOs <David Shah>
    |/
    * 9057f51 - phy: add ECP5 imports <Florent Kermarrec>
    * f660618 - phy: add initial ECP5DDRPHY <Florent Kermarrec>
    * 640194a - examples: add nexys4ddr_config <Florent Kermarrec>
    * 0ac1af3 - examples/litedram_gen: add DDR2 support <Florent Kermarrec>
    * f4184ec - example/litedram_gen: update, add descriptions of config parameters <Florent Kermarrec>
    * 79806aa - modules/ddr3: add MT41K64M16 <Florent Kermarrec>
    * ea6b841 - phy/s7ddrphy and usddrphy: add cmd_latency parameter <Florent Kermarrec>
    * fd3e9af - phy/s7ddrphy: fix cmd delays <Florent Kermarrec>
    * f61c8d9 - phy/s7ddrphy: make clk/cmd odelaye2s configurable <Florent Kermarrec>
    * e0224f4 - phy/usddrphy: make clk/cmd odelaye3s configurable <Florent Kermarrec>

 * liteeth changed from 77fa4bf to 2424e62
    * 2424e62 - software: also include generated/mem.h <Florent Kermarrec>
    * e88fc50 - software: remote ethmac_mem.h dependency (no longer exists in LiteX) <Florent Kermarrec>
    * b318300 - phy/ku_1000basex: keep tx/rx in reset until pll is fully reseted and locked <Florent Kermarrec>
    * e6c35cd - phy/ku_1000basex: incease pll_reset <Florent Kermarrec>
    * 816f592 - phy: add initial ECP5RGMII PHY <Florent Kermarrec>
    * b4c1cfe - core/icmp: fix reply checksum when request checksum >= 0xf800 <Florent Kermarrec>

 * litepcie changed from 3804c49 to de6cd01
    * de6cd01 - frontend/dma: ensure we finish LitePCIeDMAWriter transaction when DMA is disabled. <Florent Kermarrec>
    * 260c562 - frontend/wishbone: cleanup qword_aligned support <Florent Kermarrec>
    * 89b3920 - README: update <Florent Kermarrec>
    * 22310cc - phy: add initial Cyclone5 support <Florent Kermarrec>
    * 9cdb982 - phy/s7pciephy: rename external_phy to external_hard_ip <Florent Kermarrec>
    * 3b6cffd - frontend/wishbone: add qword_aligned parameter <Florent Kermarrec>
    * d191b1e - core: add endianness support <Florent Kermarrec>
    * 4df720a - examples/targets/dma: remove typo (dma connection is done internally in loopback mode) <Florent Kermarrec>
    * 14d852e - examples/targets/dma: remove soft reset, simplify crg, minor cleanups <Florent Kermarrec>
    * 64857af - phy/s7pciephy: improve presentation <Florent Kermarrec>
    * 55fa0d4 - phy/s7pciephy: remove pcie clk presence detection. <Florent Kermarrec>
    * f042273 - phy/s7pciephy: allow using external sources for the PHY. <Florent Kermarrec>
    * bd5d4dc - phy/s7pciephy: remove unnecessary reset on pcie clock domain <Florent Kermarrec>
    * ccfb201 - frontend/dma: update loop_status when request is sent <Florent Kermarrec>

 * litesata changed from b78a731 to 6fe4cce
    * 6fe4cce - examples/targets/bist: simplify analyzer <Florent Kermarrec>
    * 846bd62 - phy/a7sataphy: rework tx/rx_startup_fsm using liteiclink code <Florent Kermarrec>
    * 5e02ac9 - phy/a7sataphy: use proper transceiver name <Florent Kermarrec>
    * e63c8aa - examples/test/test_analyzer: use shorter import <Florent Kermarrec>
    * 319dd72 - examples/targets/bist: update <Florent Kermarrec>
    * df27cdf - examples/targets: add bist_nexys_video (still wip) <Florent Kermarrec>
    *   2ba5508 - Merge pull request timvideos#15 from enjoy-digital/artix7 <enjoy-digital>
    |\
    | * 0b254b0 - examples/make: remove platform option <Florent Kermarrec>
    | * e0fc55c - examples/targets/bist: revert kc705/genesys2 bist example <Florent Kermarrec>
    | * cabc908 - example: add led blinking on refclk, add startup fsm to analyzer <Florent Kermarrec>
    | * d16b495 - examples: add more debug, rx/tx leds not blinking (no clock? bad init?) <Florent Kermarrec>
    | * 1519dc3 - targets/bist: use 100 MHz clock, fix reset polarity <Florent Kermarrec>
    | * 1fe543f - phy/a7sataphy: integrate GTPQuadPLL <Florent Kermarrec>
    | * ca47e05 - examples/targets/bist: start artix7 testing with sata_gen1 <Florent Kermarrec>
    | * 1fc848e - examples: add nexys_video support <Florent Kermarrec>
    | * 9152729 - phy/a7sataphy: update parameters from wizard <Florent Kermarrec>
    | * ef5d0b9 - phy: add initial a7sataphy <Florent Kermarrec>
    | * 12b5085 - phy/k7sataphy: remove drp interface (not used) <Florent Kermarrec>
    | * 246487c - phy/k7sataphy: improve readibility <Florent Kermarrec>
    | * 41f4446 - phy/k7sataphy: make GTXE2_CHANNEL instance similar to gtx_7series in liteiclink <Florent Kermarrec>
    | * 27df062 - phy: replace trx_dw with data_width <Florent Kermarrec>
    | * d52c7b8 - phy/k7sataphy: remove ones <Florent Kermarrec>
    | * 1d1da98 - phy/k7sataphy: refactor gtxe2_channel instance <Florent Kermarrec>
    | * 10d6376 - phy: move k7 phy to a single k7sataphy file <Florent Kermarrec>
    * 7299fef - example/make.py: create the build directory when building the core if not existing <Florent Kermarrec>

 * litescope changed from c1d8bdf to 2474ce9
    * 2474ce9 - software/dump/common: change variable name for values2x loop (thanks keesj) <Florent Kermarrec>
    * 7f20aa4 - examples/make/build-core: create build directory if not existing <Florent Kermarrec>

 * litex changed from af52842f to 113f7f40
    *   113f7f40 - Merge pull request timvideos#199 from ambrop72/no-ethmac-fix <enjoy-digital>
    |\
    | * ca70ea91 - bios: Fix build when ethphy is present but ethmac is not. <Ambroz Bizjak>
    |/
    * ab1f5804 - test/test_axi: remove litex.gen.sim import (was only useful for debug) <Florent Kermarrec>
    * 5318bcd3 - setup.py: add migen to install_requires <Florent Kermarrec>
    *   33d7cc5f - Merge pull request timvideos#198 from TomKeddie/tomk_20190610_artyspi <enjoy-digital>
    |\
    | * 5346c368 - boards/arty : Add directly connected spi clk pin to avoid need for STARTUPE2 <Tom Keddie>
    * | 38a2d89a - test/test_code8b10b: add test_coding <Florent Kermarrec>
    * | 8fdd5220 - test/test_prbs: add PRBSGenerator/Checker tests <Florent Kermarrec>
    * | 243d7c76 - soc/cores: add PRBS (Pseudo Random Binary Sequence) Generator/Checker <Florent Kermarrec>
    * | cfa952b0 - tools/litex_term: exit on 2 consecutive CTRL-C <Florent Kermarrec>
    * | 1c34b4a0 - cpu/vexriscv: update submodule <Florent Kermarrec>
    * | 79665873 - doc: add litex-hub logo <Florent Kermarrec>
    * | 442d7358 - doc: redesign new logo <Florent Kermarrec>
    * | 59118627 - doc: add new logo <Florent Kermarrec>
    * | 850b311d - cpu/vexriscv: update submodule <Florent Kermarrec>
    * | 755a2660 - build/sim: allow configuring verilator optimization level <Florent Kermarrec>
    * | 4b6ad8aa - build/sim: allow defining start/end cycles for tracing <Florent Kermarrec>
    * | ecb60f6e - build/sim: use -O0 for verilator compilation <Florent Kermarrec>
    * | c64129dc - soc/integration/soc_core: list rocket as supported CPU <Florent Kermarrec>
    * | ca4e7811 - software/bios: change prompt to "litex" in green. <Florent Kermarrec>
    * | 8d0f008a - integration/soc_core: improve readibility (add separators/comments) <Florent Kermarrec>
    * | 55ebcc00 - test/test_targets: add de10lite <Florent Kermarrec>
    * |   e545b15f - Merge pull request timvideos#196 from msloniewski/de10lite_support <enjoy-digital>
    |\ \
    | * | 04ce4790 - boards/targets: add target for de10lite platform <msloniewski>
    | * | f2a740d5 - boards/platforms: add de10lite Terasic platform support <msloniewski>
    | * | a826aaca - build/altera: Add possibility to turn off generation of .rbf file <msloniewski>
    * | |   77805a5e - Merge pull request timvideos#195 from antmicro/extend_generated_headers <enjoy-digital>
    |\ \ \
    | |/ /
    |/| |
    | * | 93b61a65 - integration/builder: generate flash_boot address to csv <Mateusz Holenko>
    | * | d0b019b1 - integration/builder: generate shadow_base address to mem.h and csv <Mateusz Holenko>
    |/ /
    * |   cb2d4372 - Merge pull request timvideos#193 from gsomlo/gls-memcpy-fix <enjoy-digital>
    |\ \
    | * | f88b85a3 - software/libbase: memcpy: simple, arch-width agnostic implementation <Gabriel L. Somlo>
    |/ /
    * |   42e9d097 - Merge pull request timvideos#192 from sutajiokousagi/pr_c99_types <Tim Ansell>
    |\ \
    | * | ab0b2cac - fix signed char type to be explicitly signed <bunnie>
    * | |   b0d35a49 - Merge pull request timvideos#191 from sergachev/master <Tim Ansell>
    |\ \ \
    | * | | db890736 - fix csr_name in add_csr() <Ilia Sergachev>
    | * | | 40cbe3a9 - fix interrupt_name <Ilia Sergachev>
    |/ / /
    * | | b300c321 - test/test_targets: add de2_115, de1soc <Florent Kermarrec>
    * | | 220e2bdc - boards/platform/arty: add Arty A7-100 variant <Florent Kermarrec>
    * | |   8e6ecfb9 - Merge pull request timvideos#189 from open-design/terasic-boards <enjoy-digital>
    |\ \ \
    | * | | 6cf1a814 - boards: add Terasic DE2-115 initial support <Antony Pavlov>
    | * | | 03725991 - boards: add Terasic DE1-SoC Board support <Antony Pavlov>
    * | | |   9682189b - Merge pull request timvideos#190 from sutajiokousagi/pr_c99_types <Tim Ansell>
    |\ \ \ \
    | |/ / /
    |/| / /
    | |/ /
    | * | 200d413d - update stdint.h to include c99 types <bunnie>
    |/ /
    * |   a48858f8 - Merge pull request timvideos#188 from gsomlo/gls-csr-cleanup <enjoy-digital>
    |\ \
    | * | 273a3ea1 - soc/integration/cpu_interface: improve code legibility <Gabriel L. Somlo>
    |/ /
    * | 08a811b1 - soc/interconnect/gearbox: add msb_first/lsb_first order <Florent Kermarrec>
    * | 675f7830 - boards/targets/arty: generate 25MHz ethernet clock with S7PLL <Florent Kermarrec>
    * |   d7b00c8c - Merge pull request timvideos#187 from open-design/indent <Tim Ansell>
    |\ \
    | * | 26e6355f - litex/boards/targets: don't use tab for indentation <Antony Pavlov>
    |/ /
    * | 51095112 - soc/interconnect/axi: add round/robin arbitration between writes/reads <Florent Kermarrec>
    * | 0fb6342f - travis: update RISC-V toolchain <Florent Kermarrec>
    * | 961101d8 - bios/irc: remove compilation workaround <Florent Kermarrec>
    * | cd543b29 - README: update RISC-V toolchain <Florent Kermarrec>
    * | 7e837bf1 - .gitmodules/rocket: switch to https://github.com/enjoy-digital/rocket-litex-verilog <Florent Kermarrec>
    * | 712977a0 - software/bios/isr.c: workaround compilation issue (need to be fixed) <Florent Kermarrec>
    * | 28ba8b32 - soc/integration/soc_core: revert default mem_map (do specific RocketChip remapping for now) <Florent Kermarrec>
    * | cf369c43 - boards/targets: revert default sys_clk_freq on nexys4ddr/versa_ecp5 (but add parameter to configure it) <Florent Kermarrec>
    * |   aa640f29 - Merge pull request timvideos#186 from gsomlo/gls-rocket <enjoy-digital>
    |\ \
    | * | 019fd940 - fixup: generated-verilog submodule for experimental Rocket support <Gabriel L. Somlo>
    | * | 1a530cf2 - soc/cores/cpu/rocket: Support for 64-bit RocketChip (experimental) <Gabriel L. Somlo>
    |/ /
    * |   3de49118 - Merge pull request timvideos#185 from gsomlo/gls-sim-sdram <enjoy-digital>
    |\ \
    | |/
    |/|
    | * e90caa86 - tools/litex_sim: restore functionality of '--with-sdram' option <Gabriel L. Somlo>
    |/
    *   3a72688b - Merge pull request timvideos#183 from xobs/usb-to-0x43 <enjoy-digital>
    |\
    | * 014c9505 - remote: usb: print "access denied" error <Sean Cross>
    | * faf6554c - remote: usb: use 0x43/0xc3 for packet header <Sean Cross>
    |/
    * 10670e22 - soc/cores/minerva: update to latest <Florent Kermarrec>
    *   a3134f13 - Merge pull request timvideos#182 from gsomlo/gls-nexys4-eth-fixup <enjoy-digital>
    |\
    | * 5707bdc0 - boards/nexys4ddr: ethernet support fix-up <Gabriel L. Somlo>
    |/
    *   0a8699f1 - Merge branch 'master' of http://github.com/enjoy-digital/litex <Florent Kermarrec>
    |\
    | * 1ea22d49 - software/include/base/csr-defs.h: add specific CSR_IRQ_MASK/PENDING for Minerva <Florent Kermarrec>
    * | 526ba1b1 - soc_core: remove csr_expose and add add_csr_master method <Florent Kermarrec>
    |/
    * f2570701 - software/bios/boot: remove specific linux commands (not needed with device tree) <Florent Kermarrec>
    * 938d00c2 - boards/targets/de0nano: reduce to 50MHz sys_clk, simplify CRG <Florent Kermarrec>
    * 11838bae - platforms/de0nano: change serial pins (put then next to the GND pin) <Florent Kermarrec>
    * eb6fa458 - cpu/vexriscv/core: update <Florent Kermarrec>
    * 0cad80e9 - cpu/vexriscv: update submodule (new linux variant) <Florent Kermarrec>
    * 5f6e7874 - boards/nexys4ddr: add ethernet support (RMII 100Mbps) <Florent Kermarrec>
    * 0ba1cb87 - boards/targets/netv2: +x <Florent Kermarrec>
    * 2f2b9b31 - soc/cores: remove cordic <Florent Kermarrec>
    * 6e4ac1c4 - LICENSE: clarify <Florent Kermarrec>
    * 67159349 - soc/interconnect: remove axi_lite <Florent Kermarrec>
    * 745d83a3 - boards: add initial NeTV2 support (clocks, leds, dram, ethernet) <Florent Kermarrec>
    * a49d170a - soc/integration/soc_sdram: simplify/fix main_ram_size computation using new databits value of the phy <Florent Kermarrec>
    * 7445b9e2 - soc/integration/soc_core: allow user to defined internal csr/interrupts <Florent Kermarrec>
    * f333abcf - boards/targets: use new add_csr method <Florent Kermarrec>
    * d76a2c7d - tools/litex_sim: add uart csr (required when with_uart=False with new add_csr method) <Florent Kermarrec>
    * b6be534c - soc/integration/soc_core: rework csr assignation/reservation <Florent Kermarrec>
    * 3f09af6d - boards/targets: declare ethmac interrupt with new add_interrupt method <Florent Kermarrec>
    *   2abb3e80 - Merge branch 'master' of http://github.com/enjoy-digital/litex <Florent Kermarrec>
    |\
    | *   c11eb4b5 - Merge pull request timvideos#179 from gsomlo/gls-xtra-addrlen <enjoy-digital>
    | |\
    | | * c264a009 - soc/integration/cpu_interface: more arch-specific address size fixes <Gabriel L. Somlo>
    | |/
    * | 47dc8758 - integration/soc_core: rework interrupt assignation/reservation <Florent Kermarrec>
    * | 3ee9ce05 - test/test_targets: fix test_ulx3s name <Florent Kermarrec>
    * | 435cdad0 - boards/targets: fix ulx3s/versa_ecp5 build <Florent Kermarrec>
    * | 8caa38bc - cpu: add `reserved_interrupts` property <Mateusz Holenko>
    * | ff517915 - boards/targets: make sys_clk_freq a parameter <Florent Kermarrec>
    |/
    * a8cbe4ad - boards/targets/minispartan6: for now revert experimental s6pll clocking <Florent Kermarrec>
    * 6fcbf10e - boards/plarforms/minispartan6: default to xc6slx25 <Florent Kermarrec>
    * b7e37133 - bios/boot/ update linux memory mapping <Florent Kermarrec>
    * 190ff89a - tools/litex_term: add json support to load images to memory, allow passing speed as float <Florent Kermarrec>
    *   a50aff2c - Merge pull request timvideos#178 from daveshah1/vexriscv_linux_yosys <enjoy-digital>
    |\
    | * a048ba47 - vexriscv: Fix some floating signals <David Shah>
    |/
    * fcd518b5 - bios/boot: add specific flash_boot for linux with vexriscv <Florent Kermarrec>
    * 1ba1ad9a - bios/boot: rename MM_RAM to EMULATOR_RAM <Florent Kermarrec>
    * fbb24720 - soc/get_mem_data: add direct support for regions <Florent Kermarrec>
    * 0714816f - soc/interconnect/axi: add AXI2AXILite converter and use it in  AXI2Wishbone <Florent Kermarrec>
    * c6d0d234 - soc/interconnect/axi: add AXI Lite definition <Florent Kermarrec>
    * 9fab4752 - soc/interconnect/axi: add comment on axi signas that are present but not used <Florent Kermarrec>
    * 59890763 - cores/cpu/vexriscv: add VexRiscvTimer and use it for the linux variant <Florent Kermarrec>
    * 21bf1038 - bios/boot: add liftoff banner just before booting <Florent Kermarrec>
    * 8f4685b3 - bios/boot/netboot: only get boot.bin as default, add linux_vexriscv netboot config <Florent Kermarrec>
    * 6cf1ff09 - soc/interconnect/axi: connect axi.ar/aw when selecting write or read <Florent Kermarrec>
    * 6affc56a - soc/interconnect/axi: wishbone address shift is not always 2, make it generic <Florent Kermarrec>
    * 698bc882 - soc/interconnect/wishbone: allow setting adr_width (default to 30) <Florent Kermarrec>
    * 4dccb8a9 - soc/interconnect/axi/AXI2Wishbone: add buffer on axi command to be sure command is accepted before response is sent <Florent Kermarrec>
    * 9f8f0eb1 - build/sim: update tapcfg <Florent Kermarrec>
    *   2515c7b0 - Merge pull request timvideos#176 from gsomlo/gls-ulong-addr <enjoy-digital>
    |\
    | * 5c2b8685 - software: use "unsigned long" for address values, also 8-byte alignment <Gabriel L. Somlo>
    |/
    * 74d37465 - test/test_targets: comment bad variant tests for now <Florent Kermarrec>
    * 5c1d9805 - soc/interconnect/axi: add burst support to AXI2Wishbone <Florent Kermarrec>
    * 6de27135 - soc/interconnect/axi: add capabilities to AXIBurst2Beat and simplify/optimize <Florent Kermarrec>
    * 305b8879 - integration/soc_core: use cpu name as cpu-type for all cpus (mor1kx was instanciated with or1k) <Florent Kermarrec>
    * 4e50f36b - build/tools: add deprecated_warning <Florent Kermarrec>
    * b40d1b73 - cpu_interface: default to gcc for all cpus unless told otherwise (mor1kx default was clang) <Florent Kermarrec>
    * dbb71af1 - cpu: use property methods to return name, endianness, gcc triple/flags, linker output format <Florent Kermarrec>
    * d828c3a5 - cpu: integrate nmigen version of Minerva, add submodule <Florent Kermarrec>
    * 2c3c6bdf - Updating documents from LiteX BuildEnv Wiki <Florent Kermarrec>
    * bf27869a - fix vexriscv build <Kurt Kiefer>
    *   2d5bae3d - Merge pull request timvideos#175 from mithro/cpu-docs <enjoy-digital>
    |\
    | * 5cbc5bc1 - Adding testing of cpu variants. <Tim 'mithro' Ansell>
    | * 71a83731 - Work with no `cpu_variant` provided. <Tim 'mithro' Ansell>
    | * 65650919 - Updating documents from LiteX BuildEnv Wiki <Tim 'mithro' Ansell>
    | * a43de819 - Updating documents from LiteX BuildEnv Wiki <Tim 'mithro' Ansell>
    | * 39c579ba - Standardize the `cpu_variant` strings. <Tim 'mithro' Ansell>
    | * e42de8fe - docs: Adding script to pull useful docs from LiteX BuildEnv's wiki. <Tim 'mithro' Ansell>
    * | 3a2e2836 - .gitmodules: use our VexRiscv-verilog <Florent Kermarrec>
    |/
    * 78c09125 - soc/integration/soc_core: fix get_mem_data when not file is not multiple of 4 bytes <Florent Kermarrec>
    * 0175f86c - soc/integration/soc_core: fix get_mem_data for json files <Florent Kermarrec>
    * 4443b507 - soc/integration/soc_core: add integrated_sram_init <Florent Kermarrec>
    * f27084c6 - soc/integration/cpu_interface: fix banner in get_mem_header <Florent Kermarrec>
    *   5ec99d94 - Merge pull request timvideos#173 from gsomlo/gls-git-revision <enjoy-digital>
    |\
    | * d21cba2f - build: handle exceptional case when litex/migen not deployed as git repo <Gabriel L. Somlo>
    |/
    * 27fbb814 - tools/remote/csr_builder: allow comments in csv file and cleanup <Florent Kermarrec>
    * e8f3c491 - software/libnet/microudp: rearrange send_packet, add comments and remove txlen padding <Florent Kermarrec>
    * 44e0cdda - software/libnet/microudp: speed-up ARP by changing timeout/tries <Florent Kermarrec>
    * 3ee78a5b - build/tools: fix typo <Florent Kermarrec>
    * f0fe9f3c - setup.py: add short names for tools <Florent Kermarrec>
    * 9ded2eb2 - tools/litex_term: change TERM prompt to LXTERM <Florent Kermarrec>
    * 475deb51 - build: add migen and litex git revision to generated file <Florent Kermarrec>
    * 8b5cf295 - build/tools: git_revision is not doing what we want, return "--------" for now <Florent Kermarrec>
    * 228f2867 - litex_setup: revert default install behaviour but add --user support <Florent Kermarrec>
    *   9fbbf928 - Merge pull request timvideos#171 from keesj/develop_as_user <enjoy-digital>
    |\
    | * 24bdb648 - Install development packages in the user directory <Kees Jongenburger>
    * | 0f60ec35 - tools/litex_server: fix comms import <Florent Kermarrec>
    * | 68f12495 - soc/integration: also add sha-1/date to generated software files <Florent Kermarrec>
    * | 42574122 - build: add sha-1/date to generated verilog, change git_version to git_revision <Florent Kermarrec>
    |/
    * f7c0b118 - test/test_targets: cover all platforms <Florent Kermarrec>
    * 818dfae1 - boards/platforms/ulx3s: fix default clock <Florent Kermarrec>
    * 17b6164c - boards/platforms/sp605: apply same simplifications than on others platforms <Florent Kermarrec>
    * 24bf0293 - boards/platforms: add SP605 <Michael Betz>
    * 10cf0fde - cores/cpu/vexriscv: fix wrong revert <Florent Kermarrec>
    * d2ad1441 - targets/ac701: cleanup and make it similar to others targets. <Florent Kermarrec>
    * a24bf72f - targets/xilinx: remove keep attribute on clock going to idelayctrl <Florent Kermarrec>
    * ea8dbff8 - boards/platform/ac701: add proper copyright, cleanup to be similar to others platforms <Florent Kermarrec>
    * 0122982e - boards/platforms/kc705: provide only one default programmer as others platforms <Florent Kermarrec>
    * 89a59026 - boards: Xilinx ac701 dev board support <Vamsi K Vytla>
    * 88b882c7 - build/xilinx/ise.py: write .v file for post synthesis sim <Michael Betz>
    * 7396ebbb - build/xilinx/programmer: cleanup XC3SProg position parameter <Florent Kermarrec>
    * f579cbc6 - build/xilinx/programmer: add position parameter to XC3SProg <Michael Betz>
    * fb4f8818 - .gitignore: ignore tilde files <Vamsi K Vytla>
    * 535d8672 - targets/minispartan6: use S6PLL in CRG <Florent Kermarrec>
    * 40342404 - cores/clock: add divclk_divide_range on S6PLL/S6DCM <Florent Kermarrec>
    * 0d282f38 - cores/clock: use common XilinxClocking class for all Xilinx clocking modules <Florent Kermarrec>
    * 83699ea0 - cores/clock: add initial Spartan6 PLL/DCM support <Michael Betz>
    * eff141da - build: add git version (sha-1) used to create the scripts <Florent Kermarrec>
    * cc141a64 - build: scripts are generated by LiteX <Florent Kermarrec>
    * 115c842e - build/xilinx/vivado: cleanup pull request timvideos#170 <Florent Kermarrec>
    *   3b24b8d5 - Merge pull request timvideos#170 from ldoolitt/master <enjoy-digital>
    |\
    | * fda18fd6 - build/xilinx/vivado: only try Xilinx setup if vivado is not already in the path <Larry Doolittle>
    |/
    * 7d278854 - global: switch to VexRiscv as the default CPU <Florent Kermarrec>
    * 28d80bd6 - ci: fix test_targets/test_simple <Florent Kermarrec>
    * b7f53fb9 - test: remove waveforms generation <Florent Kermarrec>
    * e98ac680 - travis: simplify, enable and add RISC-V toolchain to build targets <Florent Kermarrec>
    * 8c789970 - boards/platforms: add separators, cleanup imports <Florent Kermarrec>
    * cb8c26d1 - boards/platforms: provide only one default programmer per platform. <Florent Kermarrec>
    * e1d202df - boards/platforms/kc705: only keep Vivado support <Florent Kermarrec>
    * 53c7be6e - boards: always define timing constraints the same way (1e9/freq_mhz) <Florent Kermarrec>
    * 02ffbed5 - boards/targets/ulx3s: allow running test_targets on it <Florent Kermarrec>
    * 5a1925df - boards/targets: add keep attribute directly in crg <Florent Kermarrec>
    *   67a79d7c - Merge pull request timvideos#167 from xobs/network-flag-check <enjoy-digital>
    |\
    | * f71b8d4f - litex_server: check socket flags exist before using them <Sean Cross>
    |/
    * 9ee6c35b - tools: move from litex.soc.tools to litex.tools and fix usb.core import <Florent Kermarrec>
    *   49fd93ae - Merge pull request timvideos#165 from xobs/vexriscv-cpu-reset-address <enjoy-digital>
    |\
    | *   c780fb22 - Merge branch 'master' of https://github.com/enjoy-digital/litex <Sean Cross>
    | |\
    | * | e2cf45b8 - cpu: vexriscv: allow cpu_reset_address to be overridden <Sean Cross>
    * | |   ca6065a6 - Merge pull request timvideos#164 from xobs/litex-usb-server <enjoy-digital>
    |\ \ \
    | * | | c6918364 - utils: litex_server: add usb support <Sean Cross>
    | * | | 9dd59d63 - tools: remote: add usb communications protocol <Sean Cross>
    * | | | 9cbed91b - soc/interconnect/axi: add AXIBurst2Beat <Florent Kermarrec>
    * | | | 5a8115d9 - soc/interconnect/avalon: add description <Florent Kermarrec>
    | |_|/
    |/| |
    * | | fa956086 - soc/integration/soc_zynq: fix HP0 connections <Florent Kermarrec>
    * | | a78ca2de - build/xilinx/vivado: only set library for vhdl files (not supported for verilog/system-verilog) <Florent Kermarrec>
    |/ /
    * | a92e90b2 - soc/interconnect: add avalon with converters to/from native streams <Florent Kermarrec>
    * |   d860eeea - Merge pull request timvideos#162 from antmicro/full-conf-vexriscv <enjoy-digital>
    |\ \
    | * | 40de01bc - vexriscv: Add full and full_debug CPU variant <Joanna Brozek>
    * | |   ce81a39c - Merge pull request timvideos#163 from gsomlo/gls-verilated-cmdargs <enjoy-digital>
    |\ \ \
    | |/ /
    |/| |
    | * | e1683078 - build/sim/core: Initialize Verilator commandArgs <Gabriel L. Somlo>
    |/ /
    * | 017147c6 - build/altera: switch to sdc constraints, add add_false_path_constraints method <Florent Kermarrec>
    * | 1275e2f1 - build/xilinx/vivado: set quiet property on MultiReg/AsyncResetSynchronizer constraints <Florent Kermarrec>
    * | c252972b - soc/cores/clock: add divclk_divide/vco_margin support on S7/Ultrascale <Florent Kermarrec>
    * | f986974d - soc/cores/clock: improve presentation <Florent Kermarrec>
    * | 538ca59a - build/xilinx/vivado: round period constraints to lowest picosecond <Florent Kermarrec>
    * |   66a74b15 - Merge pull request timvideos#161 from enjoy-digital/litex_server_arguments <enjoy-digital>
    |\ \
    | * | a2bc4bb7 - litex_server: set socket.SO_REUSEPORT to avoid waiting 60s in case of unclean termination <Florent Kermarrec>
    | * | be99083e - litex_server: add message and exit when mandarory arguments are missing. <Florent Kermarrec>
    | * | db11aec9 - litex_server: allow setting bind port, remove auto-incrementing on bind_port <Florent Kermarrec>
    | * | 76bc5785 - litex_server: refactor parameters and to allow setting bind address <Florent Kermarrec>
    |/ /
    * | 13a76ec7 - software/libnet/microudp: simplify txbuffer managment <Florent Kermarrec>
    * | 3441eb05 - software/libnet/microudp: cleanup eth_init <Florent Kermarrec>
    * | 92a79c6d - software/libnet/microudp: simplify rxbuffer managment <Florent Kermarrec>
    * | fdeff7f6 - software/libnet/microudp: set raw frame size to ETHMAC_SLOT_SIZE <Florent Kermarrec>
    * | 1569e2e0 - software/libnet: remove use of ethmac_mem.h <Florent Kermarrec>
    * | c7ac9676 - bios/sdram: add __attribute__((unused)) on cdelay <Florent Kermarrec>
    * | 7e53bff3 - litex_setup: add litesata <Florent Kermarrec>
    * | 792245f1 - boards/targets/kcu105: add Ethernet (with 1Gbps SFP adapter) <Florent Kermarrec>
    * | f8dcdb70 - software/libnet: add #ifdef on eth_init <Florent Kermarrec>
    * |   e475cfbb - Merge pull request timvideos#158 from vbuitvydas/altera-contrib <enjoy-digital>
    |\ \
    | * | 04939990 - litex/build/altera/quartus: changes to make top level assigment in .qsf file with build name <vytautasb>
    | * | 8558065f - litex/build/altera/common: added reset synchronizer <vytautasb>
    |/ /
    * | 866fa344 - integration/soc_zynq: fix missing SoCCore.do_finalize <Florent Kermarrec>
    * | 794c3c58 - integration/soc_zynq: add add_hp0 method <Florent Kermarrec>
    * | 38d404c3 - integration/soc_zynq: use add methods to add optional peripherals <Florent Kermarrec>
    * | 7375856b - integration/soc_zynq: connect axi signals that were missing <Florent Kermarrec>
    * | b15fd9d8 - interconnect/axi: add missing axi signals <Florent Kermarrec>
    * |   f95748d1 - Merge pull request timvideos#157 from CBJamo/master <enjoy-digital>
    |\ \
    | * | 1f0b3f81 - Add ifdef check for MAIN_RAM_SIZE <Caleb Jamison>
    |/ /
    * | f452d3e9 - README: bump copyright year <Florent Kermarrec>
    * | dd214d2d - bios/main: align SoC info, show CPU speed on CPU line, show L2 <Florent Kermarrec>
    * | 6599f7bb - bios/main: move sdrinit <Florent Kermarrec>
    * | b92b89ab - bios/main: print boot sequence only if sdr_ok <Florent Kermarrec>
    * | f4369c8f - bios/main: remove csr functions (not used and only supported by lm32), improve help presentation <Florent Kermarrec>
    * | 66dffb70 - software/bios: improve readibility, add soc informations <Florent Kermarrec>
    * |   e8559990 - Merge pull request timvideos#156 from gsomlo/gls-axi-width <enjoy-digital>
    |\ \
    | * | 449632e4 - soc/interconnect/axi: data/address length cleanup <Gabriel L. Somlo>
    |/ /
    * | 552b0243 - soc/interconnect/axi: remove dead code (thanks gsomlo) <Florent Kermarrec>
    * |   b682dacd - Merge pull request timvideos#154 from daveshah1/yosys_xilinx_edif <enjoy-digital>
    |\ \
    | * | 57e1ccd5 - build/xilinx: Update Yosys write_edif parameters <David Shah>
    * | | fd7ed6c1 - utils/litex_sim: fix main_ram_size <Florent Kermarrec>
    * | | 3f386dad - soc_core/get_mem_data: add json support <Florent Kermarrec>
    * | | 7bc13ba8 - build/microsemi/libero_soc: add linux build script support <Florent Kermarrec>
    * | | 7b88980d - vexriscv: allow user to use an external variant <Florent Kermarrec>
    * | | b04a756a - vexriscv/core: fix min variant <Florent Kermarrec>
    * | | a549f094 - utils/litex_sim: handle cpu_endianness for rom-init/ram-init <Florent Kermarrec>
    * | | 411bca79 - utils/litex_sim: increase default integrated_main_ram_size to 256MB, automatically boot on main_ram when ram_init is specified <Florent Kermarrec>
    * | |   7ec3ed4d - Merge pull request timvideos#153 from railnova/fix_utils <enjoy-digital>
    |\ \ \
    | * | | aed2e9b4 - [fix] utils was not installed from pip <chmousset>
    | |/ /
    * | |   3543b567 - Merge pull request timvideos#152 from gsomlo/gls-trellis-svf <enjoy-digital>
    |\ \ \
    | |/ /
    |/| |
    | * | b014c719 - build/lattice/trellis: also generate bitstream in svf format <Gabriel L. Somlo>
    |/ /
    * | 317dba83 - software/bios/sdram: use specific ERR_DDRPHY_BITSLIP/NMODULES computation <Florent Kermarrec>
    * | 7de1fe51 - targets/versa_ecp5: update ECP5DDRPHY on BaseSoC, add EthernetSoC <Florent Kermarrec>
    * | ca63db40 - bios/sdram: use burstdet detection for ECP5DDRPHY init <Florent Kermarrec>
    |/
    *   2ebfab5e - Merge pull request timvideos#150 from daveshah1/trellis_bus_fixes <enjoy-digital>
    |\
    | * ebe8f600 - lattice/common: Fix tristate buses with Trellis <David Shah>
    |/
    * 935f3a53 - boards/ulx3s: add device selection parameter <Florent Kermarrec>
    * e6f97e08 - targets/ulx3s: use AsyncResetSynchronizer and derivate sys_clk/sys_clk_ps constraints from clk25 <Florent Kermarrec>
    * 5ef28bdf - build/lattice/trellis: add package support <Florent Kermarrec>
    * 1b34c07d - build/lattice/trellis: basecfg now integrated in nextpnr <Florent Kermarrec>
    * 7e995eb4 - boards/targets/ulx3s: allow building with diamond or trellis <Florent Kermarrec>
    * 4bf789ea - soc/software/bios/boot: add vexriscv workaround <Florent Kermarrec>
    * 1fd81c28 - soc/integration: add initial SoCZynq SoC <Florent Kermarrec>
    * 3c527dcb - soc/interconnect: add initial axi code with bus definition and AXI2Wishbone <Florent Kermarrec>
    * ed257879 - test: add test_axi_lite (with test code from soc/interconnect/axi_lite lightly modified) <Florent Kermarrec>
    * 4aa07f2a - soc/interconnect: rename axi to axi_lite <Florent Kermarrec>
    * 6a4c133c - test: add basic test_csr <Florent Kermarrec>
    *   c9f9e237 - Merge pull request timvideos#149 from daveshah1/versa_trellis <enjoy-digital>
    |\
    | * ff7e0fab - versa_ecp5: Add option to build with Trellis <David Shah>
    | * 024b41c5 - trellis: Add LPF frequency constraints and remove -nomux <David Shah>
    * | e38dfd99 - soc/software/sdram: fix compilation on ultrascale <Florent Kermarrec>
    |/
    * 5f29a12e - targets/versa_ecp5: integrate DDR3 <Florent Kermarrec>
    * 3dd529e4 - soc/software/bios/sdram: add ECP5 support <Florent Kermarrec>
    * 2fd6d0e7 - soc/software/bios/sdram: improve write_level robustness <Florent Kermarrec>
    * 36772b75 - soc/software/bios/sdram: improve sdrlevel readibility <Florent Kermarrec>
    * 6a980781 - soc/software/bios/sdram: add helpers for rst/inc of delays <Florent Kermarrec>
    *   dad7b292 - Merge pull request timvideos#148 from daveshah1/versa_remove_n <enjoy-digital>
    |\
    | * 321dd8fc - versa_ecp5: Remove negative diff IO pins <David Shah>
    |/
    * c03b1ad1 - platforms/versa_ecp5: add ddram pins <Florent Kermarrec>
    * ff155a47 - soc/tools/remote/comm_uart: be sure to flush in waiting bytes before read and write <Florent Kermarrec>
    * d3ecdd99 - soc/cores/clock: add actual clk_freqs to config <Florent Kermarrec>

 * migen changed from 0.6.dev-241-gafe4405 to 0.6.dev-283-g562c046
    * 562c046 - Correct URL of logo Signed-off-by: Chipmuenk <mail@chipmuenk.de> <Chipmuenk>
    * db7ce84 - updated packaging infos <Chipmuenk>
    * a9e5029 - platforms: add de10lite support <msloniewski>
    * a69e1fd - altera/quartus: fix generated build script <msloniewski>
    * 1b804d7 - platforms: add max1000 support <msloniewski>
    * bc90344 - metlino: v1.0rc5 <Sebastien Bourdeauducq>
    * 9031bfe - metlino: add VHDCI EEM carrier connector <Sebastien Bourdeauducq>
    * 83b209e - metlino: add LEDs, I2C, Si5324, transceivers <Sebastien Bourdeauducq>
    * 4289590 - metlino: set bitstream properties <Sebastien Bourdeauducq>
    * aea0841 - metlino: add gth_clk200 and port0 <Sebastien Bourdeauducq>
    * 7299f4e - metlino: add spiflash <Sebastien Bourdeauducq>
    * 6815691 - metlino: use same SDRAM constraints as Sayma <Sebastien Bourdeauducq>
    * 42fe506 - metlino: update pins to 1.0rc4 <Sebastien Bourdeauducq>
    * 54d666d - Lattice iCE40: add comment on the polarity of differential I/O pairs <airwoodix>
    * 090ece7 - Lattice iCE40: pass positive pin to SB_IO in DifferentialInput <airwoodix>
    * ee3508b - Revert e43cd74 <airwoodix>
    * e43cd74 - Lattice iCE40: fix DifferentialInput polarity <airwoodix>
    * e6d02be - humpback: fix serial pinouts (crossover cables) <airwoodix>
    * c8cae39 - Lattice iCE40: implement DifferentialInput <Etienne Wodey>
    * a6f9cbd - Add Sinara Humpback platform (timvideos#177) <Étienne Wodey>
    * 4e66a71 - Fix `-vlgincdir` for xst. <Tim 'mithro' Ansell>
    * edcadbc - sayma_rtm2: si5324_clkout -> cdr_clk_clean <Sebastien Bourdeauducq>
    * 49b9d8a - sayma_amc2: add rtm_amc_link <Sebastien Bourdeauducq>
    * 0080bed - sayma_rtm2: add AFE test pins <Sebastien Bourdeauducq>
    * 032340d - sayma_rtm2: add rtm_amc_link <Sebastien Bourdeauducq>
    * 8bf0ab8 - sayma_rtm2: fix clk50 IOStandard <Sebastien Bourdeauducq>
    * 5dc0b23 - sayma_rtm: select correct speed grade and IDCODE for v2 <Sebastien Bourdeauducq>
    * 98a075c - sayma_rtm: update for v2.0rc4 <Sebastien Bourdeauducq>
    * cd71a2a - fix permissions <Sebastien Bourdeauducq>
    * 5a843a1 - sayma_amc: update gth_clk200, add DDMTD signals <Sebastien Bourdeauducq>
    * 2154882 - sayma_amc: OVERTEMPPOWERDOWN is called OVERTEMPSHUTDOWN on Ultrascale <Sebastien Bourdeauducq>
    * 3773947 - sayma_amc: si5324_clkout -> cdr_clk_clean <Sebastien Bourdeauducq>
    * 383512b - sayma_amc2: update to v2.0rc4 <Sebastien Bourdeauducq>
    * 936732f - add sayma_rtm2 <Sebastien Bourdeauducq>
    * d482b93 - sayma_amc2: add ddrXX_clk <Sebastien Bourdeauducq>
    * 25646d4 - sayma_amc2: enable OVERTEMPPOWERDOWN <Sebastien Bourdeauducq>
    * 9fd7a48 - remove Roach <Sebastien Bourdeauducq>
    * 9d90900 - sayma_amc: use LVDS for serwb <Sebastien Bourdeauducq>
    * 3da7113 - sayma_amc: fix aux_clk I/O standard <Sebastien Bourdeauducq>
    * 9a25f90 - sayma_amc: fix v2 platform name <Sebastien Bourdeauducq>
    * 7765238 - add Sayma AMC v2 platform <Sebastien Bourdeauducq>
    * ae42105 - migen: replace `collections` with `collections.abc` as necessary (timvideos#176) <Sean Cross>

Full submodule status
--
 15df4aebf06da579241c58949493b866139d0e2b edid-decode (remotes/origin/HEAD)
 1c21ee44a2b3936f62e4b43f2bcbf63ce9404691 flash_proxies (heads/master)
 67de3cee14b13beabc90804e3b62c66e028fd951 litedram (heads/master)
 2424e62bf9637c2623b627a56aca7a3f90349e92 liteeth (heads/master)
 de6cd01d3f158387337bf4f47fd5a351ec2c3267 litepcie (heads/master)
 6fe4cceaab77d6a117fa539f461b3ae9ca7e668e litesata (heads/master)
 2474ce9db23e4d06bff4bbeacf0051efa3042f37 litescope (heads/master)
 0a9110f901182a1233cc4e64b6e39175f6784621 liteusb (heads/master)
 98e145fba8c25394e9958bad67e2a457d145127e litevideo (heads/master)
 113f7f408e7c95150011c55ca473f45befb7f9bb litex (remotes/origin/HEAD)
 562c0466443f859d6cf0c87a0bb50db094d27cf4 migen (0.6.dev-283-g562c046)
mithro added a commit to mithro/litex-buildenv that referenced this pull request Oct 30, 2019
@mithro
Updating submodules.
5133ed7 
 * litex changed from v0.1-1099-ge637aa65 to v0.1-1333-ga54b80b9
    * a54b80b9 - targets: use type="io" instead of io_region=True <Florent Kermarrec>
    * a0c0a6fd - integration/SoCMemRegion: use type instead of io_region/linker_region and export type to csv/json <Florent Kermarrec>
    * 9fcf2973 - soc_core: add check_regions_overlap method, add linker_region support (overlap is not checked on linker_regions) <Florent Kermarrec>
    * 4014fbff - soc_core/add_memory_region: fix memory overlap detection <Florent Kermarrec>
    * 650df0eb - test/test_targets: skip Minerva test on Travis-CI, remove commented tests <Florent Kermarrec>
    * ab8af282 - cpu/minerva: elaborate from nmigen sources during build, enable hardware multiplier <Florent Kermarrec>
    *   4cc40aad - Merge pull request timvideos#286 from gsomlo/gls-timingstrict <enjoy-digital>
    |\
    | * 49372852 - build/lattice/trellis: optionally allow failure if p&r timing not met <Gabriel Somlo>
    |/
    *   b6d35c92 - Merge pull request timvideos#283 from kbeckmann/kbeckmann/bios_increment_address <enjoy-digital>
    |\
    | * ef78ae95 - bios: Increment address when writing to flash <Konrad Beckmann>
    * | 683e0668 - build/lattice/trellis: use --timing-allow-fail to allow generating bistream when timings are not met <Florent Kermarrec>
    * | 4cf346a1 - soc/cores/icap/ICAPBitstream: always keep fifo.source.ready to 1 <Florent Kermarrec>
    * |   39862f06 - Merge pull request timvideos#282 from antmicro/icapbitstream_fixes <enjoy-digital>
    |\ \
    | * | 8b5da9c6 - cores/icap/ICAPBitstream: add source ready signal. <Jan Kowalewski>
    |/ /
    * | 626533ce - soc/integration/__init__: remove imports (not used and causing issues <Florent Kermarrec>
    * | 675b4552 - build: always use platform.add_source and avoid manipulate platform.sources directly <Florent Kermarrec>
    * | 43f5d1ef - build/generic_platform: replace set with list for sources/verilog_include_paths <Florent Kermarrec>
    * | 97a77b95 - cores/icap/ICAPBitstream: simplify, add icap_clk_div parameter, describe how to use it. <Florent Kermarrec>
    * | 98c224be - build/generic_platform: keep language to None if None after tools.language_by_filename <Florent Kermarrec>
    * | 14dae8bd - soc_core: fix default --uart_name <Florent Kermarrec>
    * | ba264418 - integration/soc_core: expose more SoC parameters <Florent Kermarrec>
    * |   23d83961 - Merge pull request timvideos#280 from kbeckmann/picorv32_typo <Tim Ansell>
    |\ \
    | |/
    |/|
    | * 0e467168 - picorv32: Fix minimal variant params <Konrad Beckmann>
    |/
    * ef504f62 - soc_core: fix soc_core_argdict <Florent Kermarrec>
    * cd8213b9 - cpu/lm32: add missing buses <Florent Kermarrec>
    * 5a035875 - soc_core/soc_core_argdict: use inspect to get all parameters and simplify <Florent Kermarrec>
    * 96c369f3 - integration: simplify cpu buses auto-conversion (always use Converter, thanks gsomlo) <Florent Kermarrec>
    * 29e51f5e - interconnect/wishbone: fix Converter case when buses are identical <Florent Kermarrec>
    * ae9c25b7 - platforms/versa_ecp5: add serdes refclk/sma <Florent Kermarrec>
    * 9a829338 - cpu/rocket: expose 64-bit buses (use automatic down-conversion of SoCCore) <Florent Kermarrec>
    * ca81cc20 - soc_core: add automatic down-conversion of CPU buses to 32-bit (if needed) <Florent Kermarrec>
    * 03faf06c - soc/interconnect/axi: re-align to improve readability <Florent Kermarrec>
    * 7dea9afd - software/bios: simplify banners <Florent Kermarrec>
    * 6bd18893 - cpu/picorv32: remove obsolete comment <Florent Kermarrec>
    * 28517d20 - cpu/picorv32: use a single idbus <Florent Kermarrec>
    * 5daf1a22 - cpu: cleanup/re-align <Florent Kermarrec>
    * 467d35ed - cpu/rocket: rename ibus/dbus to mem_wb/mmio_wb and add size suffix <Florent Kermarrec>
    * 1045cda3 - cpu: add buses list and use it in soc_core to add bus masters <Florent Kermarrec>
    * 42ccc91f - integration: move soc constants to soc.h of csr.h <Florent Kermarrec>
    * ed3c53d7 - build/generic_platform: only add sources if language is not None <Florent Kermarrec>
    * f3ba0788 - xilinx/vivado: replace "xy" == language with language == "xy" <Florent Kermarrec>
    *   17756f63 - Merge pull request timvideos#277 from railnova/feature/vivado_sysverilog_support <enjoy-digital>
    |\
    | * f2369a4c - Add system Verilog support for the Vivado builder <Martin Cornil>
    * | b2519482 - integration/soc_zynq: shadow_base no longer recommended (replace with io_regions) <Florent Kermarrec>
    * | 496ba7e5 - bios/main: use same banner than README (MiSoC cited in README/LICENSE) <Florent Kermarrec>
    * | 840f01b6 - software/bios: don't show peripherals init banner if nothing to init, add Ethernet init printf <Florent Kermarrec>
    |/
    *   37531cec - Merge pull request timvideos#276 from gsomlo/gls-rocket-map <enjoy-digital>
    |\
    | * f8f643a0 - cpu/rocket: swap main_mem and io regions <Gabriel Somlo>
    |/
    * b627a8fe - cpu: add default io_regions to CPUNone (all address range can be used as IO) <Florent Kermarrec>
    *   cc245fc8 - Merge pull request timvideos#275 from pcotret/patch-1 <enjoy-digital>
    |\
    | * e923a88d - Update README (related to issue timvideos#273) <Pascal Cotret>
    * | a6b3aa3c - soc_core: improve check_io_region error message <Florent Kermarrec>
    * | dc656d48 - targets/sim: switch from shadow_base to io_regions <Florent Kermarrec>
    * | 10146abf - cpu/rocket: move csr to IO region <Florent Kermarrec>
    * | 7f1d4623 - build/xilinx/vivado: fix default synth-mode <Florent Kermarrec>
    * | a4ef9b29 - soc_core/cpu: add io_regions and deprecate shadow_base (with API retro-compat) <Florent Kermarrec>
    |/
    *   e8b90e80 - Merge pull request timvideos#274 from gsomlo/gls-shadow-base <enjoy-digital>
    |\
    | * 53777391 - builder: use the SoC's existing shadow base with get_csr_header() <Gabriel Somlo>
    |/
    * 92975b13 - targets/arty: allow setting synth-mode to yosys with command line: --synth-mode=yosys <Florent Kermarrec>
    * 4a1cefe9 - build/xilinx/vivado: add vivado_build_args/vivado_build_argdict for yosys synthesis mode <Florent Kermarrec>
    * 3e22d4b9 - xilinx/common: be sure language is not vhdl when yosys synthesis is used <Florent Kermarrec>
    * 975bd9be - cpu/vexriscv: use specific mem_map for linux variant <Florent Kermarrec>
    *   2dfe7441 - Merge pull request timvideos#271 from gsomlo/gls-yosys-nowidelut <enjoy-digital>
    |\
    | * 6aa76b1d - trellis, versa_ecp5: optional '-nowidelut' flag for yosys synth_ecp5 <Gabriel L. Somlo>
    * |   c954ff0c - Merge pull request timvideos#272 from sergachev/fix-comments <enjoy-digital>
    |\ \
    | |/
    |/|
    | * 2f7bd971 - fix comments <Ilia Sergachev>
    * | ab4a5d1d - litex_setup: add litejesd204b <Florent Kermarrec>
    |/
    *   960b25a5 - Merge pull request timvideos#270 from gsomlo/gls-csr-upper <enjoy-digital>
    |\
    | * c8790d34 - soc/integration: ensure CSR constants are in uppercase <Gabriel Somlo>
    * | 41ad08e8 - soc/cores/icap: simplify ICAPBitstream (untested) <Florent Kermarrec>
    * | 0c299386 - soc/cores/icap: rename ICAP to ICAPBistream and revert old ICAP <Florent Kermarrec>
    * |   4bb2827e - Merge pull request timvideos#269 from antmicro/rework_icap <enjoy-digital>
    |\ \
    | |/
    |/|
    | * 4423a46b - soc: cores: support sending custom bitstream to ICAP <Jan Kowalewski>
    * | 427d7af7 - soc/interconnect: rename stream_packet to packet & cleanup (with retro-compat) <Florent Kermarrec>
    * | 59bf04d9 - soc/interconnect/stream: add separators, mode Actor modules just after Endpoint <Florent Kermarrec>
    * | 59995c53 - soc_zynq: update get_csr_header <Florent Kermarrec>
    * | 4d90058b - soc/integration: move cpu_interface retro-compatibility to litex/__init__ <Florent Kermarrec>
    * | 8be5824e - soc/integration: use dicts for constants/mem_regions/csr_regions to cleanup/simplify iterations on theses <Florent Kermarrec>
    * | 7b72148c - cpu: remove initial SERV support (we'll work in a branch to experiment with it) <Florent Kermarrec>
    * | 63a813af - soc_core: fix cpu_type=None case and add test for it <Florent Kermarrec>
    * | 3d257d72 - soc_sdram: remove axi usecase, this was only useful to do some preliminary axi tests. <Florent Kermarrec>
    * | e8e57b4f - soc_core: cleanup/re-align <Florent Kermarrec>
    * | 334ae336 - soc/integration: rename cpu_interface to export (with retro-compat), re-arrange a bit, add separators <Florent Kermarrec>
    * | 241c3c64 - test/test_targets: update cpu-type to mor1kx <Florent Kermarrec>
    * | 48e5a1d1 - soc/cores: uniformize (continue) <Florent Kermarrec>
    * | e9ed4761 - soc/cores/gpio: uniformize with others cores <Florent Kermarrec>
    * | 78cecbe3 - soc/cores: rename frequency_meter to freqmeter and uniformize with others cores <Florent Kermarrec>
    * | 7575ecc6 - soc/cores/ecc: improve readibility, uniformize with others cores <Florent Kermarrec>
    * | c6fe3f31 - soc/cores/clocks: improve readibility <Florent Kermarrec>
    * | 6fcb12a9 - soc_core: use cpu.data_width to compute csr_alignment (and remove Rocket workaround) <Florent Kermarrec>
    * | b826c170 - soc/cores/cpus: improve ident/align, uniformize between cpus <Florent Kermarrec>
    * | 355072c2 - soc/cores/cpu: add CPU class and make all CPU inheritate from it <Florent Kermarrec>
    * | 2c3ad3f9 - soc_sdram: move ControllerInjector to LiteDRAM (LiteDRAMCore) <Florent Kermarrec>
    * | 101f1b1c - soc/integration: add common.py and move helpers from soc_core to it <Florent Kermarrec>
    * | 68ba1c60 - soc_core: avoid manual listing of support CPUs, just use CPU.keys() <Florent Kermarrec>
    * | 9095b80e - soc_core: remove add_cpu_or_bridge retro-compatibility (most of the designs have been updated since the change) <Florent Kermarrec>
    * | 8dd2dc1c - integration/soc_core: remove csr_map_update (no longer used) <Florent Kermarrec>
    * | da91aa43 - soc_core/cpu: move memory map override to CPUs, select reset_address after eventual memory map has override been done <Florent Kermarrec>
    * | 8099b0be - soc/cores/cpu: add set_reset_address method and use it instead of passing reset_address as a parameter <Florent Kermarrec>
    * | 7660dc22 - soc/cores/cpu: do instance in do_finalize for all cpus (allow updating parameters until the design is generated) <Florent Kermarrec>
    * | a3816096 - cores/cpu: define CPUS and simplify instance <Florent Kermarrec>
    * | 9f6a2ae7 - soc_core/serv: use UART_POLLING (no interrupt support) <Florent Kermarrec>
    * | a4069fc8 - add SERV submodule <Florent Kermarrec>
    * | 49594ed7 - software/libbase/uart: add polling mode <Florent Kermarrec>
    * | 3f95b9c0 - add SERV CPU initial support (not working) <Florent Kermarrec>
    * | 015b65fe - targets/ulx3s: revert to cl=2 <Florent Kermarrec>
    * | a9d55b04 - boards/netv2: switch to MVP, add spiflashx4 and hdmi in/out <Florent Kermarrec>
    * | 1425a68d - wishbone2csr: refactor using FSM, reduce latency (make it asynchronous) and set csr.adr only when access is done (allow use of CSR/CSRBase we signal) <Florent Kermarrec>
    * | ffd2be2b - csr: add we signal to CSR, CSRStatus <Florent Kermarrec>
    * | 47dc3324 - build/xilinx/programmer: fix vivado_cmd <Florent Kermarrec>
    * | ed9bff2e - soc/integration/doc: replace "== None" by "is None" <Florent Kermarrec>
    * |   836d5b88 - Merge pull request timvideos#266 from xobs/add-moduledoc-autodoc <enjoy-digital>
    |\ \
    | * | 68cea8c3 - timer: inherit ModuleDoc <Sean Cross>
    | * | 13197198 - integration: add ModuleDoc and AutoDoc <Sean Cross>
    * | | 78fb0fb9 - tools/litex_read_verilog: also delete yosys_v2j.ys <Florent Kermarrec>
    * | | 0ea7a1fd - soc_core/sdram: Don't blow up if _wb_sdram_ifs or _csr_masters are empty <Benjamin Herrenschmidt>
    * | |   742da31b - Merge pull request timvideos#264 from antmicro/mor1kx_linux <enjoy-digital>
    |\ \ \
    | * | | 5844376d - soc_core: adapt memory map for mainline Linux with mor1kx <Filip Kokosinski>
    | * | | 201218b2 - boards/targets: increase integrated ROM size if EthernetSoC is used <Filip Kokosinski>
    * | | | 06d08064 - soc_core: set csr to 0x00000000 when there is no wishbone <Florent Kermarrec>
    * | | | ad8830d9 - soc_sdram: Don't add the L2 Cache when there's no wishbone bus <Florent Kermarrec>
    |/ / /
    * | | ae38fd42 - soc_core: revert wishbone2csr to __init__ but add with_wishbone parameter <Florent Kermarrec>
    * | | 8c979565 - soc_sdram: change l2_size checks order <Florent Kermarrec>
    * | | a9acab99 - soc_core: move CSR bridge to finalize (only generate it if there is a wishbone master), revert default parameter when cpu_type is None (we have systems with cpu_type=None but that are using these peripherals) <Florent Kermarrec>
    * | | dde6dd02 - integration/builder: avoid specific _generate_standalone_includes <Florent Kermarrec>
    * | | 735ea196 - This will allow it to be built for microwatt out of tree <Benjamin Herrenschmidt>
    * | | c28086cd - soc_core: When cpu_type is "None", let's not generate useless UART, timer, ROMs, wishbone to CSR bridge etc... <Benjamin Herrenschmidt>
    * | | f909e4d7 - integration/builder: When the CPU is "None", we used to not generate any code. <Benjamin Herrenschmidt>
    |/ /
    * |   8b7d8217 - Merge pull request timvideos#263 from xobs/spi-flash-csrfield <enjoy-digital>
    |\ \
    | * | 1a6dddd5 - spi_flash: document register fields <Sean Cross>
    |/ /
    * |   4f659ba4 - Merge pull request timvideos#262 from jersey99/master <enjoy-digital>
    |\ \
    | * | 9ea11cf5 - vivado just needs to be in the path for the programmer as well <Vamsi K Vytla>
    |/ /
    * |   430fee4d - Merge pull request timvideos#261 from xobs/event-documentation <enjoy-digital>
    |\ \
    | |/
    |/|
    | * 60d8572c - csr_eventmanager: add `name` and `description` args <Sean Cross>
    |/
    * e2c78572 - cores/timer: add general documentation on Timer implementation and behavior. <Florent Kermarrec>
    * e97c1e36 - soc_sdram: improve readibility and convert l2_size to minimal allowed if provided l2_size is lower <Florent Kermarrec>
    * 99ed0877 - csr: add description to CSRStorage/CSRStatus attributes (thanks xobs) <Florent Kermarrec>
    * f2e84a58 - soc/cores/timer: fix typo (thanks xobs) <Florent Kermarrec>
    * 28885064 - soc/cores/timer/doc: rewrite a little bit, avoid some redundancy, change ident. <Florent Kermarrec>
    *   f1139c36 - Merge pull request timvideos#259 from xobs/document-timer <enjoy-digital>
    |\
    | * cb7d941a - timer: add documentation <Sean Cross>
    |/
    * cca0478a - soc/cores/spi: use new CSRField (no functional change) <Florent Kermarrec>
    * 80b2bef3 - soc/cores/bitbang: use new CSRField (no functional change) <Florent Kermarrec>
    *   3dc8d294 - Merge pull request timvideos#257 from enjoy-digital/csr_fields <enjoy-digital>
    |\
    | * 9bda614a - csr: update copyrights <Florent Kermarrec>
    | * 29134cc6 - csr: more documentation <Florent Kermarrec>
    | * 74e756aa - csr/CSRStorage: remove storage_full (was only needed by alignment_bits) <Florent Kermarrec>
    | * 5dc440e8 - csr: use IntEnum for CSRAccess <Florent Kermarrec>
    | * d2646f13 - csr/CSRStorage: remove alignment_bits: complexify too much code for the few use-cases it's really useful <Florent Kermarrec>
    | * 8e14694e - csr/fields: document, add separators, 100 characters per line <Florent Kermarrec>
    | * 4e84729c - csr/fields: add access parameter <Florent Kermarrec>
    | * 23b01f8f - csr/fields: add pulse mode support <Florent Kermarrec>
    | * 8c080e5f - soc/interconnect/csr: add initial field support <Florent Kermarrec>
    |/
    * c120f6d4 - build/openocd: add set_qe parameter to flash <Florent Kermarrec>
    * 6a0a1c9d - tools/litex_term/upload: bufferize only chunks of the file instead of the entire file to speedup upload when used on embedded devices (RPI for example) <Florent Kermarrec>
    * 16b6b357 - soc/integration/cpu_interface: don't raise OSError if we are not going to compile software and compilation toolchain is not found <Florent Kermarrec>
    * 62f53d50 - soc/integration/builder: call do_exit with vns when build is done. <Florent Kermarrec>
    *   cb5f1467 - Merge branch 'master' of http://github.com/enjoy-digital/litex <Florent Kermarrec>
    |\
    | *   a7b5c185 - Merge pull request timvideos#255 from sergachev/fix-crc32 <enjoy-digital>
    | |\
    | | * 2400f0f4 - fix crc32 <Ilia Sergachev>
    | |/
    * | 004c96b5 - soc/itnegration: update litedram <Florent Kermarrec>
    |/
    * 19f58dd9 - interconnect/wishbone: add FlipFlop to allow UpConverter to be used <Florent Kermarrec>
    * bd6ec63b - build/openocd: add stream method for JTAG UART <Florent Kermarrec>
    * b356204f - soc_core: add JTAG UART support (uart_name="jtag_uart) <Florent Kermarrec>
    * d0ebbda4 - soc/cores/jtag: add Xilinx JTAG TAPs support and simple JTAG PHY (can be used for JTAG UART) <Florent Kermarrec>
    * 2638393b - soc_zynq: fix indent <Florent Kermarrec>
    * 9051cf97 - soc_zynq: fix typo <Florent Kermarrec>
    * 67a09aef - soc/interconnect/stream: add Monitor module <Florent Kermarrec>
    *   6f150a56 - Merge pull request timvideos#254 from mithro/crc-smaller <enjoy-digital>
    |\
    | * 2a41f0d2 - Use `SMALL_CRC` to enable smaller CRC versions. <Tim 'mithro' Ansell>
    | * 08333744 - Remove extra whitespace. <Tim 'mithro' Ansell>
    | * c0e72386 - libbase: crc16: commit smaller version of crc16 <Sean Cross>
    | * a59d0efc - libbase: crc32: add smaller version <Sean Cross>
    * |   27c334d4 - Merge pull request timvideos#252 from mithro/only-change-on-contents <Tim Ansell>
    |\ \
    | |/
    |/|
    | * 3ff6a18a - Only write file if contents will change. <Tim 'mithro' Ansell>
    |/
    * a2938a7a - soc/cores: simplify JTAGAtlantic (only keep alt_jtag_atlantic instance), move to jtag and allow selecting it as uart with uart_name"jtag_atlantic" <Florent Kermarrec>
    *   19d3acfc - Merge pull request timvideos#251 from micro-FPGA/master <enjoy-digital>
    |\
    | * fb00ee85 - Create atlantic.py <Antti Lukats>
    | *   92e5b4b2 - Merge pull request timvideos#2 from enjoy-digital/master <Antti Lukats>
    | |\
    | * | f47e4978 - libero enable enhanced constraints <Antti Lukats>
    * | | 41fe7cae - core/spi: add minimal SPISlave <Florent Kermarrec>
    * | | b8457559 - gen/fhdl/verilog: allow single element verilog inline attribute <Florent Kermarrec>
    * | | 5a7b4c34 - targets/nexys_video: generate clk100 <Florent Kermarrec>
    * | | c179741c - software/bios: switch to standard CRLF <Florent Kermarrec>
    * | | 0328ba7d - tools/litex_term: add automatic check to see if we need to insert LF or not <Florent Kermarrec>
    * | | ffebd207 - bios/tools: allow disabling CRC check on serialboot (to speedup debug/loading large images when only serial is available) <Florent Kermarrec>
    * | | 4842bdcf - tools/litex_term: add sdl_payload_length <Florent Kermarrec>
    * | | 3e30c648 - litex_setup: add litex-boards <Florent Kermarrec>
    * | |   d79cd87d - Merge pull request timvideos#246 from gsomlo/gls-native-rv64 <enjoy-digital>
    |\ \ \
    | * | | 6d844a03 - software: use native toolchain for same host, target architectures <Gabriel L. Somlo>
    |/ / /
    * | |   d36f1fb7 - Merge pull request timvideos#244 from atommann/master <enjoy-digital>
    |\ \ \
    | |_|/
    |/| |
    | * | a45dbee5 - changing http to https <atommann>
    | * | 1d957d7a - Update .gitmodules <atommann>
    * | | 4990bf33 - soc/core: simplify/cleanup HyperRAM core - rename core to hyperbus. - change layout (cs_n with variable length instead of cs0_n, cs1_n). - use DifferentialOutput when differential clock is used. - add test (python3 -m unittest test.test_hyperbus). <Florent Kermarrec>
    * | | d1502d41 - soc/cores: add initial simple hyperram core <Antti Lukats>
    | |/
    |/|
    * | 6e6fe83a - build/altera/quartus: add add_ip method to use Quartus QSYS files <Florent Kermarrec>
    * | 2899928a - cpu_interface: add json csr map export, simplify csv csr map export using json <Florent Kermarrec>
    * | 9d4b7cd5 - bios/sdram: set init done after memtest (for standalone LiteDRAM controllers) <Florent Kermarrec>
    * | 0cd4e45f - build/xilinx/vivado: use "" for strings <Florent Kermarrec>
    * | 8d161a47 - build/xilinx/vivado: remove with_phys_opt <Florent Kermarrec>
    * |   f6638ded - Merge pull request timvideos#243 from sergachev/master <enjoy-digital>
    |\ \
    | * | 861eea8a - build/xilinx/vivado: improve directive support <Ilia Sergachev>
    * | |   ccc2cbd9 - Merge pull request timvideos#241 from railnova/zynq <enjoy-digital>
    |\ \ \
    | |/ /
    |/| |
    | * | db4c609a - [fix] prevent Vivado from inferring DSP48 in AXIBurst2Beat <chmousset>
    |/ /
    * | 6d5fddc1 - cores/spi_flash/S7SPIFlash: make cs_n optional in pads (when driven externally) <Florent Kermarrec>
    * |   383c05e2 - Merge pull request timvideos#240 from danielkucera/patch-1 <enjoy-digital>
    |\ \
    | |/
    |/|
    | * a5eaf172 - more understandable error when missing a memory <Daniel Kucera>
    |/
    *   2b815f70 - Merge pull request timvideos#235 from gsomlo/gls-trellis-yosys-opt <enjoy-digital>
    |\
    | * 6c298cb7 - build/lattice/trellis: use abc9 techmapping pass with yosys <Gabriel L. Somlo>
    |/
    * 31bfb546 - software/libbase/mdio: set data before clock, revert two cycle turnaround and test with different phys <Florent Kermarrec>
    * e670cb91 - cores/cpu: add riscv-none-embed toolchain support to riscv32 cpus <Florent Kermarrec>
    * 6d94c07d - software/libase/mdio: cleanup and reduce raw_turnaround by 1 cycle <Florent Kermarrec>
    * 0c287b11 - cores/clock/S7PLL: fix -1/-3 speedgrade vco max freq swap <Florent Kermarrec>
    * 82cd557c - software/bios: add Ethernet PHY MDIO read/write/dump commands <Florent Kermarrec>
    * 0ba9ab92 - altera/common: fix AsyncResetSynchronizer polarity and simplify <Florent Kermarrec>
    * 124dff8f - build/xilinx/common: improve presentation <Florent Kermarrec>
    * 60873a5b - microsemi/common: improve presentation <Florent Kermarrec>
    * 36d9d78c - build/altera/common: improve presentation <Florent Kermarrec>
    * 95953d29 - platforms/default_clk_period: use 1e9/freq <Florent Kermarrec>
    * f1d8c70b - targets/minispartan6/crg: only keep S6PLL code <Florent Kermarrec>
    * d3d0a623 - cores/clock: juse use 1e9/freq instead of period_ns <Florent Kermarrec>
    * a881817f - cores/clock/s6pll: add phase support <Florent Kermarrec>
    * 6b7ca0cf - cores/clock/xilinx: change clkfbout_mult loop order to select highest vco_freq <Florent Kermarrec>
    * 1884649d - litex_term: make sure to unconfigure console when board is unplugged <Florent Kermarrec>
    * e052d7f6 - soc/integration/builder: -x <Florent Kermarrec>
    * 236070fd - cores: -x on spi.py <Florent Kermarrec>
    * a9fe2788 - wishbone/SRAM: make read_only emited verilog code compatible with all tools <Florent Kermarrec>
    * ce5c5859 - soc/cores/uart: add FT245 FIFO mode support (sync & async) <Florent Kermarrec>
    * a496760c - build/altera/quartus: use .bat on win32/cygwin <Florent Kermarrec>
    * 7e0ea070 - build/xilinx/vivado: change severity of Common 17-55 critical warning to warning <Florent Kermarrec>
    * 92d93ad2 - cores/pwm: remove default CSR reset values. <Florent Kermarrec>
    * 25ca0a8b - soc: generate git header and show migen/litex git sha1 in bios <Florent Kermarrec>
    * ae00482d - Merge pull request timvideos#223 from sergachev/master <enjoy-digital>
    * fdb119cb - support vivado incremental implementation <Ilia Sergachev>

 * litex-renode changed from b3fdb9b to 742360f
    *   742360f - Merge pull request timvideos#15 from antmicro/zephyr_dts <Tim Ansell>
    |\
    | * c9b9651 - Add script generating DTS overlay for Zephyr <Mateusz Holenko>
    * | b0ebee5 - Merge pull request timvideos#14 from antmicro/memory_regions_verification <Mateusz Hołenko>
    |/
    * ad52a03 - Verify memory sub-regions <Mateusz Holenko>
    * 2cb6886 - Rework handling address/size values in `Configuration` <Mateusz Holenko>
    * 462df23 - Simplify flash memory generation <Mateusz Holenko>
    * 3a1f7c8 - Generate memory regions size in hex <Mateusz Holenko>
    * f010339 - Print peripheral address in hex <Mateusz Holenko>
    * 0742996 - Fix a typo <Mateusz Holenko>

 * migen changed from 0.6.dev-289-g5585912 to 0.6.dev-306-g41922fd
    * 41922fd - sayma_amc2: amc_fpga_sysref* <Sebastien Bourdeauducq>
    * 3714470 - sayma_amc: fix dac_sync pin locations <Sebastien Bourdeauducq>
    * 4a6ef29 - sayma_amc2: DAC JESD links have been swapped <Sebastien Bourdeauducq>
    * 3012df6 - sayma_amc2: sma_io -> mcx_io <Sebastien Bourdeauducq>
    * ecf8412 - sayma2: remove serwb <Sebastien Bourdeauducq>
    * fc31a9e - sayma_rtm2: add HMC workaround signals <Sebastien Bourdeauducq>
    * 21b2fbd - sayma_rtm2: fix swapped scl/sda <Sebastien Bourdeauducq>
    * 0114468 - sayma_rtm2: cross UART <Sebastien Bourdeauducq>
    * 5a28590 - sayma_rtm2: clk50 is DNP, use GTP clock instead <Sebastien Bourdeauducq>
    * ef7dab2 - sayma_rtm2: always xc7a50t <Sebastien Bourdeauducq>
    * 63a5f55 - sayma_rtm2: add filtered_clk_sel signal <Sebastien Bourdeauducq>
    * 9211304 - sayma_amc2: add filtered_clk_sel signal <Sebastien Bourdeauducq>
    * 9e59e41 - sayma_amc2: fix typo in previous commit <Sebastien Bourdeauducq>
    * 58d9c82 - sayma_amc2: fix ddram_32 assignments <Sebastien Bourdeauducq>
    * 57a7311 - Added support for the Xilinx AC701 FPGA development board <Tobias Rosenkranz>
    * f4fcd10 - fix previous commit <Sebastien Bourdeauducq>
    * 34f24f3 - zedboard: use Vivado toolchain <Sebastien Bourdeauducq>

Full submodule status
--
 3a6108a75be356a3dc53760d22782f1323248b6b edid-decode (remotes/origin/HEAD)
 01d8f819f15baf9a8cc5d96945a51e4d267ff564 flash_proxies (remotes/origin/HEAD)
 401554f94c5fbfae1a4de98504c5c2994a6f714a litedram (remotes/origin/HEAD)
 4d9e74f10a3fe7bf71ba9bde50f49689c6458dc5 liteeth (remotes/origin/HEAD)
 47e76f447f6e3d97aac2638a98f967d44db5c349 litepcie (remotes/origin/HEAD)
 db5d2f7881161ce5b9a10a0ab42555f884b9d7c1 litesata (remotes/origin/HEAD)
 7a9fa9d3b18362bf707dff25a78661395ef9ee7a litescope (remotes/origin/HEAD)
 7457a29b1a47fe15e81fa37f3bbdd510788f1d53 liteusb (remotes/origin/HEAD)
 49bafa481075e0bfbaf067b63c351ec29e993894 litevideo (remotes/origin/HEAD)
 a54b80b9b4eaa6defca99b0749da8426535bbb62 litex (v0.1-1333-ga54b80b9)
 742360f2ba4c400c6164908f03c6ca3d965f168b litex-renode (remotes/origin/HEAD)
 41922fde2a8c36cd0f99d4b7ebb3ba9c37ce1489 migen (0.6.dev-306-g41922fd)
mithro added a commit to mithro/litex-buildenv that referenced this pull request Oct 30, 2019
@mithro
Updating submodules.
3a9127d 
 * edid-decode changed from 42f5fa4 to 3a6108a
    * 3a6108a - edid-decode: Add Dell UP3218K DP tiled edid <Clint Taylor>
    * ad20c30 - edid-decode: improve DisplayID 1.2/3 parsing <Hans Verkuil>
    * 31a3417 - edid-decode: add warn() function <Hans Verkuil>
    * 8752afd - edid-decode: improve some of the texts <Hans Verkuil>
    * 8f7bb1f - edid-decode: improve readability of output <Hans Verkuil>
    * dc8afbf - edid-decode: add new HDMI 2.1 Amendment A1 and HDR10+ support <Hans Verkuil>
    * 44d1587 - edid-decode: add more EDIDs <Hans Verkuil>
    * 7d26052 - edid-decode: improve "Invalid Detailed Timings" message <Hans Verkuil>
    * 0da30bd - edid-decode: Avoid division by zero <Breno Leitao>
    * ea15b91 - edid-decode: add ELO 4600L EDID <Hans Verkuil>
    * 7696439 - Add LG 32UD99-W edid from the DP (USB-C) input <Hans Verkuil>
    * 0932dee - Add LG 32UD99-W edid from the HDMI input <Hans Verkuil>
    * 3bd8bbe - Add EDID for LG OLED55E6V <Hans Verkuil>
    * d5fb521 - Add an EDID for the Samsung UE48JU7090 <Hans Verkuil>

 * flash_proxies changed from 1c21ee4 to 01d8f81
    * 01d8f81 - remove bscan_spi_xcku040-sayma <Sebastien Bourdeauducq>

 * litedram changed from 6c53996 to 401554f
    *   401554f - Merge pull request timvideos#92 from gsomlo/gls-assert-width <enjoy-digital>
    |\
    | * 7356d3b - frontend/wishbone: add base_address param. to LiteDRAMWishbone2Native <Gabriel Somlo>
    | * 24203cf - frontend/axi: add assertion on matching axi, native port data_width <Gabriel Somlo>
    |/
    * d84e1b4 - frontend/axi: add assert on axi.address_width and base_address <Florent Kermarrec>
    * 1d037d2 - frontend/axi: add base_address parameter to LiteDRAMAXI2Native <Florent Kermarrec>
    * 5d1a984 - core: add LiteDRAMCore (ControllerInjector from LiteX) <Florent Kermarrec>
    * d647abd - gen: fix with_wishbone <Florent Kermarrec>
    * db97203 - gen: use SoCCore with_wishbone parameter, do more replace in yml files before passing config to LiteDRAMCore <Florent Kermarrec>
    * adf481f - gen: disable peripherals that are not used when cpu_type is None <Florent Kermarrec>
    * 2331919 - gen: change CSR config names, switch to csr_expose/csr_align <Florent Kermarrec>
    * da408a3 - gen: fix default csr_port_align value <Florent Kermarrec>
    * bac66aa - gen: In conjunction with the corresponding changes in litex itself, this will allow us to generate a more useful standalone litedram core. <Benjamin Herrenschmidt>
    * afbf709 - We had the address and data bus sizes mixed up <Benjamin Herrenschmidt>
    * d93dded - frontend/wishbone: add data_width assertions <Florent Kermarrec>
    * f586aad - phys: improve presentation (add separators, better indent) <Florent Kermarrec>
    * 783258c - phys: use dfi instead if self.dfi internally <Florent Kermarrec>
    * 59c1289 - phy/usddrphy: move DDR4DFIMux to dfi.py <Florent Kermarrec>
    * f861d99 - core/refresher: improve naming/parameters of refresh postponing <Florent Kermarrec>
    * dc1bb53 - phys: move get_cl_cw/get_sys_latency/get_sys_phases helpers to common <Florent Kermarrec>
    * 509f606 - README: add periodic refresh/ZQ short calibration. <Florent Kermarrec>
    * 40b4c62 - test/test_init: fix <Florent Kermarrec>
    * 5b48eb2 - test/test_init: delete generated file <Florent Kermarrec>
    * 188b6a8 - add ZQ periodic short calibration support (default to 1s) <Florent Kermarrec>
    * 6e176d4 - init: split by memtype <Florent Kermarrec>
    * 0b24b81 - test: add test_init with sdr/ddr3/ddr4 references <Florent Kermarrec>
    * bf5883c - rename sdram_init to init <Florent Kermarrec>
    * 23ccdc9 - modules: add DDR3 MT8KTF51264 SO-DIMM <Florent Kermarrec>
    * d37a30e - litedram_gen: add wishbone user port support <Florent Kermarrec>
    * b6a0eff - frontend/wishbone: split control/data paths (to avoid data muxes) <Florent Kermarrec>
    * 6497343 - frontend/wishbone: remove IDLE fsm state <Florent Kermarrec>
    * 00ecb87 - gen: add separators <Florent Kermarrec>
    * a782eb5 - test/test_examples: adapt for travis <Florent Kermarrec>
    * f678efa - travis: add pyyaml <Florent Kermarrec>
    *   8861d80 - Merge pull request timvideos#91 from sd-fritze/master <enjoy-digital>
    |\
    | * fe2cc94 - modules: Add support for Micron MT47H32M16 DDR2 RAM <gruetzkopf>
    |/
    * a23b9e7 - core/refresher: set cmd.valid to 0 when sequencer done <Florent Kermarrec>
    * 12ddc13 - litedram/gen: add description and switch to argparse <Florent Kermarrec>
    * 2bdeda0 - move standalone core generation to litedram package and make it usable externally <Florent Kermarrec>
    * 0dde125 - examples/litedram_gen: fix #!/usr/bin/env python3 location <Florent Kermarrec>
    * 602ff8b - examples: switch to YAML config files <Florent Kermarrec>
    * fb28f79 - core/refresher: remove load/load_count on RefreshTimer (not used) <Florent Kermarrec>
    * 1c69f49 - core/controller: allow user provided Refresher <Florent Kermarrec>
    * b64daba - core/controller: add separators, ease readibility <Florent Kermarrec>
    * 338d18d - core/refresher: add capability to accumulate N refreshs and execute the N refreshs together <Florent Kermarrec>
    * 818c4ca - core/refresher: another cleanup pass <Florent Kermarrec>
    * 80c8ecf - core/multiplexer: rewrite arbiter comment <Florent Kermarrec>
    * 37db416 - core/refresher: another cleanup pass <Florent Kermarrec>
    * f0592ff - core/refresher: add comments <Florent Kermarrec>
    * de38b52 - core/refresher: rename RefreshGenerator to RefreshSequencer and simplify <Florent Kermarrec>
    * 8573c22 - phy/gensdrphy: add assertions on length of pads.dq/pads.dq <Florent Kermarrec>

 * liteeth changed from ad187d3 to 4d9e74f
    * 4d9e74f - phy/usrgmii: cleanup (style, indent) <Florent Kermarrec>
    * 4bc79ce - examples/targets/core: update <Florent Kermarrec>
    * cd0eaa9 - Merge pull request timvideos#19 from jersey99/master <enjoy-digital>
    * 59e0460 - Adds RGMII phy support for Xilinx Ultrascale Devices. Hardware tested on HTG-940 <Vamsi K Vytla>

 * litepcie changed from 71c9a3a to 47e76f4
    * 47e76f4 - example/dma: keep up to date with litex <Florent Kermarrec>
    * 7f9367c - example/make: keep up to date with litex <Florent Kermarrec>
    * c6a536a - frontend/dma: add optional underflows/overflows monitoring, rename tx_fifo/rx_fifo to reader_fifo/writer_fifo <Florent Kermarrec>
    * 6bb4a60 - frontend/dma/buffering: expose fifo levels to CSRs <Florent Kermarrec>

 * litescope changed from 9e3b9d8 to 7a9fa9d
    * 7a9fa9d - core: use new CSRStatus.we signal to speed-up Storage upload (>10x speedup over ethernet) <Florent Kermarrec>
    * 284253d - core: add csr_csv parameter and export csv_csv on do_exit <Florent Kermarrec>
    * 69a8df0 - Merge pull request timvideos#14 from DurandA/master <enjoy-digital>
    * 06cac3a - Use cpu instead of cpu_or_bridge in examples <Arnaud Durand>

 * litevideo changed from 98e145f to 49bafa4
    * 49bafa4 - input/dma: no longer use aligment_bits of CSRStorage <Florent Kermarrec>

 * litex changed from v0.1-1099-ge637aa65 to v0.1-1333-ga54b80b9
    * a54b80b9 - targets: use type="io" instead of io_region=True <Florent Kermarrec>
    * a0c0a6fd - integration/SoCMemRegion: use type instead of io_region/linker_region and export type to csv/json <Florent Kermarrec>
    * 9fcf2973 - soc_core: add check_regions_overlap method, add linker_region support (overlap is not checked on linker_regions) <Florent Kermarrec>
    * 4014fbff - soc_core/add_memory_region: fix memory overlap detection <Florent Kermarrec>
    * 650df0eb - test/test_targets: skip Minerva test on Travis-CI, remove commented tests <Florent Kermarrec>
    * ab8af282 - cpu/minerva: elaborate from nmigen sources during build, enable hardware multiplier <Florent Kermarrec>
    *   4cc40aad - Merge pull request timvideos#286 from gsomlo/gls-timingstrict <enjoy-digital>
    |\
    | * 49372852 - build/lattice/trellis: optionally allow failure if p&r timing not met <Gabriel Somlo>
    |/
    *   b6d35c92 - Merge pull request timvideos#283 from kbeckmann/kbeckmann/bios_increment_address <enjoy-digital>
    |\
    | * ef78ae95 - bios: Increment address when writing to flash <Konrad Beckmann>
    * | 683e0668 - build/lattice/trellis: use --timing-allow-fail to allow generating bistream when timings are not met <Florent Kermarrec>
    * | 4cf346a1 - soc/cores/icap/ICAPBitstream: always keep fifo.source.ready to 1 <Florent Kermarrec>
    * |   39862f06 - Merge pull request timvideos#282 from antmicro/icapbitstream_fixes <enjoy-digital>
    |\ \
    | * | 8b5da9c6 - cores/icap/ICAPBitstream: add source ready signal. <Jan Kowalewski>
    |/ /
    * | 626533ce - soc/integration/__init__: remove imports (not used and causing issues <Florent Kermarrec>
    * | 675b4552 - build: always use platform.add_source and avoid manipulate platform.sources directly <Florent Kermarrec>
    * | 43f5d1ef - build/generic_platform: replace set with list for sources/verilog_include_paths <Florent Kermarrec>
    * | 97a77b95 - cores/icap/ICAPBitstream: simplify, add icap_clk_div parameter, describe how to use it. <Florent Kermarrec>
    * | 98c224be - build/generic_platform: keep language to None if None after tools.language_by_filename <Florent Kermarrec>
    * | 14dae8bd - soc_core: fix default --uart_name <Florent Kermarrec>
    * | ba264418 - integration/soc_core: expose more SoC parameters <Florent Kermarrec>
    * |   23d83961 - Merge pull request timvideos#280 from kbeckmann/picorv32_typo <Tim Ansell>
    |\ \
    | |/
    |/|
    | * 0e467168 - picorv32: Fix minimal variant params <Konrad Beckmann>
    |/
    * ef504f62 - soc_core: fix soc_core_argdict <Florent Kermarrec>
    * cd8213b9 - cpu/lm32: add missing buses <Florent Kermarrec>
    * 5a035875 - soc_core/soc_core_argdict: use inspect to get all parameters and simplify <Florent Kermarrec>
    * 96c369f3 - integration: simplify cpu buses auto-conversion (always use Converter, thanks gsomlo) <Florent Kermarrec>
    * 29e51f5e - interconnect/wishbone: fix Converter case when buses are identical <Florent Kermarrec>
    * ae9c25b7 - platforms/versa_ecp5: add serdes refclk/sma <Florent Kermarrec>
    * 9a829338 - cpu/rocket: expose 64-bit buses (use automatic down-conversion of SoCCore) <Florent Kermarrec>
    * ca81cc20 - soc_core: add automatic down-conversion of CPU buses to 32-bit (if needed) <Florent Kermarrec>
    * 03faf06c - soc/interconnect/axi: re-align to improve readability <Florent Kermarrec>
    * 7dea9afd - software/bios: simplify banners <Florent Kermarrec>
    * 6bd18893 - cpu/picorv32: remove obsolete comment <Florent Kermarrec>
    * 28517d20 - cpu/picorv32: use a single idbus <Florent Kermarrec>
    * 5daf1a22 - cpu: cleanup/re-align <Florent Kermarrec>
    * 467d35ed - cpu/rocket: rename ibus/dbus to mem_wb/mmio_wb and add size suffix <Florent Kermarrec>
    * 1045cda3 - cpu: add buses list and use it in soc_core to add bus masters <Florent Kermarrec>
    * 42ccc91f - integration: move soc constants to soc.h of csr.h <Florent Kermarrec>
    * ed3c53d7 - build/generic_platform: only add sources if language is not None <Florent Kermarrec>
    * f3ba0788 - xilinx/vivado: replace "xy" == language with language == "xy" <Florent Kermarrec>
    *   17756f63 - Merge pull request timvideos#277 from railnova/feature/vivado_sysverilog_support <enjoy-digital>
    |\
    | * f2369a4c - Add system Verilog support for the Vivado builder <Martin Cornil>
    * | b2519482 - integration/soc_zynq: shadow_base no longer recommended (replace with io_regions) <Florent Kermarrec>
    * | 496ba7e5 - bios/main: use same banner than README (MiSoC cited in README/LICENSE) <Florent Kermarrec>
    * | 840f01b6 - software/bios: don't show peripherals init banner if nothing to init, add Ethernet init printf <Florent Kermarrec>
    |/
    *   37531cec - Merge pull request timvideos#276 from gsomlo/gls-rocket-map <enjoy-digital>
    |\
    | * f8f643a0 - cpu/rocket: swap main_mem and io regions <Gabriel Somlo>
    |/
    * b627a8fe - cpu: add default io_regions to CPUNone (all address range can be used as IO) <Florent Kermarrec>
    *   cc245fc8 - Merge pull request timvideos#275 from pcotret/patch-1 <enjoy-digital>
    |\
    | * e923a88d - Update README (related to issue timvideos#273) <Pascal Cotret>
    * | a6b3aa3c - soc_core: improve check_io_region error message <Florent Kermarrec>
    * | dc656d48 - targets/sim: switch from shadow_base to io_regions <Florent Kermarrec>
    * | 10146abf - cpu/rocket: move csr to IO region <Florent Kermarrec>
    * | 7f1d4623 - build/xilinx/vivado: fix default synth-mode <Florent Kermarrec>
    * | a4ef9b29 - soc_core/cpu: add io_regions and deprecate shadow_base (with API retro-compat) <Florent Kermarrec>
    |/
    *   e8b90e80 - Merge pull request timvideos#274 from gsomlo/gls-shadow-base <enjoy-digital>
    |\
    | * 53777391 - builder: use the SoC's existing shadow base with get_csr_header() <Gabriel Somlo>
    |/
    * 92975b13 - targets/arty: allow setting synth-mode to yosys with command line: --synth-mode=yosys <Florent Kermarrec>
    * 4a1cefe9 - build/xilinx/vivado: add vivado_build_args/vivado_build_argdict for yosys synthesis mode <Florent Kermarrec>
    * 3e22d4b9 - xilinx/common: be sure language is not vhdl when yosys synthesis is used <Florent Kermarrec>
    * 975bd9be - cpu/vexriscv: use specific mem_map for linux variant <Florent Kermarrec>
    *   2dfe7441 - Merge pull request timvideos#271 from gsomlo/gls-yosys-nowidelut <enjoy-digital>
    |\
    | * 6aa76b1d - trellis, versa_ecp5: optional '-nowidelut' flag for yosys synth_ecp5 <Gabriel L. Somlo>
    * |   c954ff0c - Merge pull request timvideos#272 from sergachev/fix-comments <enjoy-digital>
    |\ \
    | |/
    |/|
    | * 2f7bd971 - fix comments <Ilia Sergachev>
    * | ab4a5d1d - litex_setup: add litejesd204b <Florent Kermarrec>
    |/
    *   960b25a5 - Merge pull request timvideos#270 from gsomlo/gls-csr-upper <enjoy-digital>
    |\
    | * c8790d34 - soc/integration: ensure CSR constants are in uppercase <Gabriel Somlo>
    * | 41ad08e8 - soc/cores/icap: simplify ICAPBitstream (untested) <Florent Kermarrec>
    * | 0c299386 - soc/cores/icap: rename ICAP to ICAPBistream and revert old ICAP <Florent Kermarrec>
    * |   4bb2827e - Merge pull request timvideos#269 from antmicro/rework_icap <enjoy-digital>
    |\ \
    | |/
    |/|
    | * 4423a46b - soc: cores: support sending custom bitstream to ICAP <Jan Kowalewski>
    * | 427d7af7 - soc/interconnect: rename stream_packet to packet & cleanup (with retro-compat) <Florent Kermarrec>
    * | 59bf04d9 - soc/interconnect/stream: add separators, mode Actor modules just after Endpoint <Florent Kermarrec>
    * | 59995c53 - soc_zynq: update get_csr_header <Florent Kermarrec>
    * | 4d90058b - soc/integration: move cpu_interface retro-compatibility to litex/__init__ <Florent Kermarrec>
    * | 8be5824e - soc/integration: use dicts for constants/mem_regions/csr_regions to cleanup/simplify iterations on theses <Florent Kermarrec>
    * | 7b72148c - cpu: remove initial SERV support (we'll work in a branch to experiment with it) <Florent Kermarrec>
    * | 63a813af - soc_core: fix cpu_type=None case and add test for it <Florent Kermarrec>
    * | 3d257d72 - soc_sdram: remove axi usecase, this was only useful to do some preliminary axi tests. <Florent Kermarrec>
    * | e8e57b4f - soc_core: cleanup/re-align <Florent Kermarrec>
    * | 334ae336 - soc/integration: rename cpu_interface to export (with retro-compat), re-arrange a bit, add separators <Florent Kermarrec>
    * | 241c3c64 - test/test_targets: update cpu-type to mor1kx <Florent Kermarrec>
    * | 48e5a1d1 - soc/cores: uniformize (continue) <Florent Kermarrec>
    * | e9ed4761 - soc/cores/gpio: uniformize with others cores <Florent Kermarrec>
    * | 78cecbe3 - soc/cores: rename frequency_meter to freqmeter and uniformize with others cores <Florent Kermarrec>
    * | 7575ecc6 - soc/cores/ecc: improve readibility, uniformize with others cores <Florent Kermarrec>
    * | c6fe3f31 - soc/cores/clocks: improve readibility <Florent Kermarrec>
    * | 6fcb12a9 - soc_core: use cpu.data_width to compute csr_alignment (and remove Rocket workaround) <Florent Kermarrec>
    * | b826c170 - soc/cores/cpus: improve ident/align, uniformize between cpus <Florent Kermarrec>
    * | 355072c2 - soc/cores/cpu: add CPU class and make all CPU inheritate from it <Florent Kermarrec>
    * | 2c3ad3f9 - soc_sdram: move ControllerInjector to LiteDRAM (LiteDRAMCore) <Florent Kermarrec>
    * | 101f1b1c - soc/integration: add common.py and move helpers from soc_core to it <Florent Kermarrec>
    * | 68ba1c60 - soc_core: avoid manual listing of support CPUs, just use CPU.keys() <Florent Kermarrec>
    * | 9095b80e - soc_core: remove add_cpu_or_bridge retro-compatibility (most of the designs have been updated since the change) <Florent Kermarrec>
    * | 8dd2dc1c - integration/soc_core: remove csr_map_update (no longer used) <Florent Kermarrec>
    * | da91aa43 - soc_core/cpu: move memory map override to CPUs, select reset_address after eventual memory map has override been done <Florent Kermarrec>
    * | 8099b0be - soc/cores/cpu: add set_reset_address method and use it instead of passing reset_address as a parameter <Florent Kermarrec>
    * | 7660dc22 - soc/cores/cpu: do instance in do_finalize for all cpus (allow updating parameters until the design is generated) <Florent Kermarrec>
    * | a3816096 - cores/cpu: define CPUS and simplify instance <Florent Kermarrec>
    * | 9f6a2ae7 - soc_core/serv: use UART_POLLING (no interrupt support) <Florent Kermarrec>
    * | a4069fc8 - add SERV submodule <Florent Kermarrec>
    * | 49594ed7 - software/libbase/uart: add polling mode <Florent Kermarrec>
    * | 3f95b9c0 - add SERV CPU initial support (not working) <Florent Kermarrec>
    * | 015b65fe - targets/ulx3s: revert to cl=2 <Florent Kermarrec>
    * | a9d55b04 - boards/netv2: switch to MVP, add spiflashx4 and hdmi in/out <Florent Kermarrec>
    * | 1425a68d - wishbone2csr: refactor using FSM, reduce latency (make it asynchronous) and set csr.adr only when access is done (allow use of CSR/CSRBase we signal) <Florent Kermarrec>
    * | ffd2be2b - csr: add we signal to CSR, CSRStatus <Florent Kermarrec>
    * | 47dc3324 - build/xilinx/programmer: fix vivado_cmd <Florent Kermarrec>
    * | ed9bff2e - soc/integration/doc: replace "== None" by "is None" <Florent Kermarrec>
    * |   836d5b88 - Merge pull request timvideos#266 from xobs/add-moduledoc-autodoc <enjoy-digital>
    |\ \
    | * | 68cea8c3 - timer: inherit ModuleDoc <Sean Cross>
    | * | 13197198 - integration: add ModuleDoc and AutoDoc <Sean Cross>
    * | | 78fb0fb9 - tools/litex_read_verilog: also delete yosys_v2j.ys <Florent Kermarrec>
    * | | 0ea7a1fd - soc_core/sdram: Don't blow up if _wb_sdram_ifs or _csr_masters are empty <Benjamin Herrenschmidt>
    * | |   742da31b - Merge pull request timvideos#264 from antmicro/mor1kx_linux <enjoy-digital>
    |\ \ \
    | * | | 5844376d - soc_core: adapt memory map for mainline Linux with mor1kx <Filip Kokosinski>
    | * | | 201218b2 - boards/targets: increase integrated ROM size if EthernetSoC is used <Filip Kokosinski>
    * | | | 06d08064 - soc_core: set csr to 0x00000000 when there is no wishbone <Florent Kermarrec>
    * | | | ad8830d9 - soc_sdram: Don't add the L2 Cache when there's no wishbone bus <Florent Kermarrec>
    |/ / /
    * | | ae38fd42 - soc_core: revert wishbone2csr to __init__ but add with_wishbone parameter <Florent Kermarrec>
    * | | 8c979565 - soc_sdram: change l2_size checks order <Florent Kermarrec>
    * | | a9acab99 - soc_core: move CSR bridge to finalize (only generate it if there is a wishbone master), revert default parameter when cpu_type is None (we have systems with cpu_type=None but that are using these peripherals) <Florent Kermarrec>
    * | | dde6dd02 - integration/builder: avoid specific _generate_standalone_includes <Florent Kermarrec>
    * | | 735ea196 - This will allow it to be built for microwatt out of tree <Benjamin Herrenschmidt>
    * | | c28086cd - soc_core: When cpu_type is "None", let's not generate useless UART, timer, ROMs, wishbone to CSR bridge etc... <Benjamin Herrenschmidt>
    * | | f909e4d7 - integration/builder: When the CPU is "None", we used to not generate any code. <Benjamin Herrenschmidt>
    |/ /
    * |   8b7d8217 - Merge pull request timvideos#263 from xobs/spi-flash-csrfield <enjoy-digital>
    |\ \
    | * | 1a6dddd5 - spi_flash: document register fields <Sean Cross>
    |/ /
    * |   4f659ba4 - Merge pull request timvideos#262 from jersey99/master <enjoy-digital>
    |\ \
    | * | 9ea11cf5 - vivado just needs to be in the path for the programmer as well <Vamsi K Vytla>
    |/ /
    * |   430fee4d - Merge pull request timvideos#261 from xobs/event-documentation <enjoy-digital>
    |\ \
    | |/
    |/|
    | * 60d8572c - csr_eventmanager: add `name` and `description` args <Sean Cross>
    |/
    * e2c78572 - cores/timer: add general documentation on Timer implementation and behavior. <Florent Kermarrec>
    * e97c1e36 - soc_sdram: improve readibility and convert l2_size to minimal allowed if provided l2_size is lower <Florent Kermarrec>
    * 99ed0877 - csr: add description to CSRStorage/CSRStatus attributes (thanks xobs) <Florent Kermarrec>
    * f2e84a58 - soc/cores/timer: fix typo (thanks xobs) <Florent Kermarrec>
    * 28885064 - soc/cores/timer/doc: rewrite a little bit, avoid some redundancy, change ident. <Florent Kermarrec>
    *   f1139c36 - Merge pull request timvideos#259 from xobs/document-timer <enjoy-digital>
    |\
    | * cb7d941a - timer: add documentation <Sean Cross>
    |/
    * cca0478a - soc/cores/spi: use new CSRField (no functional change) <Florent Kermarrec>
    * 80b2bef3 - soc/cores/bitbang: use new CSRField (no functional change) <Florent Kermarrec>
    *   3dc8d294 - Merge pull request timvideos#257 from enjoy-digital/csr_fields <enjoy-digital>
    |\
    | * 9bda614a - csr: update copyrights <Florent Kermarrec>
    | * 29134cc6 - csr: more documentation <Florent Kermarrec>
    | * 74e756aa - csr/CSRStorage: remove storage_full (was only needed by alignment_bits) <Florent Kermarrec>
    | * 5dc440e8 - csr: use IntEnum for CSRAccess <Florent Kermarrec>
    | * d2646f13 - csr/CSRStorage: remove alignment_bits: complexify too much code for the few use-cases it's really useful <Florent Kermarrec>
    | * 8e14694e - csr/fields: document, add separators, 100 characters per line <Florent Kermarrec>
    | * 4e84729c - csr/fields: add access parameter <Florent Kermarrec>
    | * 23b01f8f - csr/fields: add pulse mode support <Florent Kermarrec>
    | * 8c080e5f - soc/interconnect/csr: add initial field support <Florent Kermarrec>
    |/
    * c120f6d4 - build/openocd: add set_qe parameter to flash <Florent Kermarrec>
    * 6a0a1c9d - tools/litex_term/upload: bufferize only chunks of the file instead of the entire file to speedup upload when used on embedded devices (RPI for example) <Florent Kermarrec>
    * 16b6b357 - soc/integration/cpu_interface: don't raise OSError if we are not going to compile software and compilation toolchain is not found <Florent Kermarrec>
    * 62f53d50 - soc/integration/builder: call do_exit with vns when build is done. <Florent Kermarrec>
    *   cb5f1467 - Merge branch 'master' of http://github.com/enjoy-digital/litex <Florent Kermarrec>
    |\
    | *   a7b5c185 - Merge pull request timvideos#255 from sergachev/fix-crc32 <enjoy-digital>
    | |\
    | | * 2400f0f4 - fix crc32 <Ilia Sergachev>
    | |/
    * | 004c96b5 - soc/itnegration: update litedram <Florent Kermarrec>
    |/
    * 19f58dd9 - interconnect/wishbone: add FlipFlop to allow UpConverter to be used <Florent Kermarrec>
    * bd6ec63b - build/openocd: add stream method for JTAG UART <Florent Kermarrec>
    * b356204f - soc_core: add JTAG UART support (uart_name="jtag_uart) <Florent Kermarrec>
    * d0ebbda4 - soc/cores/jtag: add Xilinx JTAG TAPs support and simple JTAG PHY (can be used for JTAG UART) <Florent Kermarrec>
    * 2638393b - soc_zynq: fix indent <Florent Kermarrec>
    * 9051cf97 - soc_zynq: fix typo <Florent Kermarrec>
    * 67a09aef - soc/interconnect/stream: add Monitor module <Florent Kermarrec>
    *   6f150a56 - Merge pull request timvideos#254 from mithro/crc-smaller <enjoy-digital>
    |\
    | * 2a41f0d2 - Use `SMALL_CRC` to enable smaller CRC versions. <Tim 'mithro' Ansell>
    | * 08333744 - Remove extra whitespace. <Tim 'mithro' Ansell>
    | * c0e72386 - libbase: crc16: commit smaller version of crc16 <Sean Cross>
    | * a59d0efc - libbase: crc32: add smaller version <Sean Cross>
    * |   27c334d4 - Merge pull request timvideos#252 from mithro/only-change-on-contents <Tim Ansell>
    |\ \
    | |/
    |/|
    | * 3ff6a18a - Only write file if contents will change. <Tim 'mithro' Ansell>
    |/
    * a2938a7a - soc/cores: simplify JTAGAtlantic (only keep alt_jtag_atlantic instance), move to jtag and allow selecting it as uart with uart_name"jtag_atlantic" <Florent Kermarrec>
    *   19d3acfc - Merge pull request timvideos#251 from micro-FPGA/master <enjoy-digital>
    |\
    | * fb00ee85 - Create atlantic.py <Antti Lukats>
    | *   92e5b4b2 - Merge pull request timvideos#2 from enjoy-digital/master <Antti Lukats>
    | |\
    | * | f47e4978 - libero enable enhanced constraints <Antti Lukats>
    * | | 41fe7cae - core/spi: add minimal SPISlave <Florent Kermarrec>
    * | | b8457559 - gen/fhdl/verilog: allow single element verilog inline attribute <Florent Kermarrec>
    * | | 5a7b4c34 - targets/nexys_video: generate clk100 <Florent Kermarrec>
    * | | c179741c - software/bios: switch to standard CRLF <Florent Kermarrec>
    * | | 0328ba7d - tools/litex_term: add automatic check to see if we need to insert LF or not <Florent Kermarrec>
    * | | ffebd207 - bios/tools: allow disabling CRC check on serialboot (to speedup debug/loading large images when only serial is available) <Florent Kermarrec>
    * | | 4842bdcf - tools/litex_term: add sdl_payload_length <Florent Kermarrec>
    * | | 3e30c648 - litex_setup: add litex-boards <Florent Kermarrec>
    * | |   d79cd87d - Merge pull request timvideos#246 from gsomlo/gls-native-rv64 <enjoy-digital>
    |\ \ \
    | * | | 6d844a03 - software: use native toolchain for same host, target architectures <Gabriel L. Somlo>
    |/ / /
    * | |   d36f1fb7 - Merge pull request timvideos#244 from atommann/master <enjoy-digital>
    |\ \ \
    | |_|/
    |/| |
    | * | a45dbee5 - changing http to https <atommann>
    | * | 1d957d7a - Update .gitmodules <atommann>
    * | | 4990bf33 - soc/core: simplify/cleanup HyperRAM core - rename core to hyperbus. - change layout (cs_n with variable length instead of cs0_n, cs1_n). - use DifferentialOutput when differential clock is used. - add test (python3 -m unittest test.test_hyperbus). <Florent Kermarrec>
    * | | d1502d41 - soc/cores: add initial simple hyperram core <Antti Lukats>
    | |/
    |/|
    * | 6e6fe83a - build/altera/quartus: add add_ip method to use Quartus QSYS files <Florent Kermarrec>
    * | 2899928a - cpu_interface: add json csr map export, simplify csv csr map export using json <Florent Kermarrec>
    * | 9d4b7cd5 - bios/sdram: set init done after memtest (for standalone LiteDRAM controllers) <Florent Kermarrec>
    * | 0cd4e45f - build/xilinx/vivado: use "" for strings <Florent Kermarrec>
    * | 8d161a47 - build/xilinx/vivado: remove with_phys_opt <Florent Kermarrec>
    * |   f6638ded - Merge pull request timvideos#243 from sergachev/master <enjoy-digital>
    |\ \
    | * | 861eea8a - build/xilinx/vivado: improve directive support <Ilia Sergachev>
    * | |   ccc2cbd9 - Merge pull request timvideos#241 from railnova/zynq <enjoy-digital>
    |\ \ \
    | |/ /
    |/| |
    | * | db4c609a - [fix] prevent Vivado from inferring DSP48 in AXIBurst2Beat <chmousset>
    |/ /
    * | 6d5fddc1 - cores/spi_flash/S7SPIFlash: make cs_n optional in pads (when driven externally) <Florent Kermarrec>
    * |   383c05e2 - Merge pull request timvideos#240 from danielkucera/patch-1 <enjoy-digital>
    |\ \
    | |/
    |/|
    | * a5eaf172 - more understandable error when missing a memory <Daniel Kucera>
    |/
    *   2b815f70 - Merge pull request timvideos#235 from gsomlo/gls-trellis-yosys-opt <enjoy-digital>
    |\
    | * 6c298cb7 - build/lattice/trellis: use abc9 techmapping pass with yosys <Gabriel L. Somlo>
    |/
    * 31bfb546 - software/libbase/mdio: set data before clock, revert two cycle turnaround and test with different phys <Florent Kermarrec>
    * e670cb91 - cores/cpu: add riscv-none-embed toolchain support to riscv32 cpus <Florent Kermarrec>
    * 6d94c07d - software/libase/mdio: cleanup and reduce raw_turnaround by 1 cycle <Florent Kermarrec>
    * 0c287b11 - cores/clock/S7PLL: fix -1/-3 speedgrade vco max freq swap <Florent Kermarrec>
    * 82cd557c - software/bios: add Ethernet PHY MDIO read/write/dump commands <Florent Kermarrec>
    * 0ba9ab92 - altera/common: fix AsyncResetSynchronizer polarity and simplify <Florent Kermarrec>
    * 124dff8f - build/xilinx/common: improve presentation <Florent Kermarrec>
    * 60873a5b - microsemi/common: improve presentation <Florent Kermarrec>
    * 36d9d78c - build/altera/common: improve presentation <Florent Kermarrec>
    * 95953d29 - platforms/default_clk_period: use 1e9/freq <Florent Kermarrec>
    * f1d8c70b - targets/minispartan6/crg: only keep S6PLL code <Florent Kermarrec>
    * d3d0a623 - cores/clock: juse use 1e9/freq instead of period_ns <Florent Kermarrec>
    * a881817f - cores/clock/s6pll: add phase support <Florent Kermarrec>
    * 6b7ca0cf - cores/clock/xilinx: change clkfbout_mult loop order to select highest vco_freq <Florent Kermarrec>
    * 1884649d - litex_term: make sure to unconfigure console when board is unplugged <Florent Kermarrec>
    * e052d7f6 - soc/integration/builder: -x <Florent Kermarrec>
    * 236070fd - cores: -x on spi.py <Florent Kermarrec>
    * a9fe2788 - wishbone/SRAM: make read_only emited verilog code compatible with all tools <Florent Kermarrec>
    * ce5c5859 - soc/cores/uart: add FT245 FIFO mode support (sync & async) <Florent Kermarrec>
    * a496760c - build/altera/quartus: use .bat on win32/cygwin <Florent Kermarrec>
    * 7e0ea070 - build/xilinx/vivado: change severity of Common 17-55 critical warning to warning <Florent Kermarrec>
    * 92d93ad2 - cores/pwm: remove default CSR reset values. <Florent Kermarrec>
    * 25ca0a8b - soc: generate git header and show migen/litex git sha1 in bios <Florent Kermarrec>
    * ae00482d - Merge pull request timvideos#223 from sergachev/master <enjoy-digital>
    * fdb119cb - support vivado incremental implementation <Ilia Sergachev>

 * litex-renode changed from b3fdb9b to 742360f
    *   742360f - Merge pull request timvideos#15 from antmicro/zephyr_dts <Tim Ansell>
    |\
    | * c9b9651 - Add script generating DTS overlay for Zephyr <Mateusz Holenko>
    * | b0ebee5 - Merge pull request timvideos#14 from antmicro/memory_regions_verification <Mateusz Hołenko>
    |/
    * ad52a03 - Verify memory sub-regions <Mateusz Holenko>
    * 2cb6886 - Rework handling address/size values in `Configuration` <Mateusz Holenko>
    * 462df23 - Simplify flash memory generation <Mateusz Holenko>
    * 3a1f7c8 - Generate memory regions size in hex <Mateusz Holenko>
    * f010339 - Print peripheral address in hex <Mateusz Holenko>
    * 0742996 - Fix a typo <Mateusz Holenko>

 * migen changed from 0.6.dev-289-g5585912 to 0.6.dev-306-g41922fd
    * 41922fd - sayma_amc2: amc_fpga_sysref* <Sebastien Bourdeauducq>
    * 3714470 - sayma_amc: fix dac_sync pin locations <Sebastien Bourdeauducq>
    * 4a6ef29 - sayma_amc2: DAC JESD links have been swapped <Sebastien Bourdeauducq>
    * 3012df6 - sayma_amc2: sma_io -> mcx_io <Sebastien Bourdeauducq>
    * ecf8412 - sayma2: remove serwb <Sebastien Bourdeauducq>
    * fc31a9e - sayma_rtm2: add HMC workaround signals <Sebastien Bourdeauducq>
    * 21b2fbd - sayma_rtm2: fix swapped scl/sda <Sebastien Bourdeauducq>
    * 0114468 - sayma_rtm2: cross UART <Sebastien Bourdeauducq>
    * 5a28590 - sayma_rtm2: clk50 is DNP, use GTP clock instead <Sebastien Bourdeauducq>
    * ef7dab2 - sayma_rtm2: always xc7a50t <Sebastien Bourdeauducq>
    * 63a5f55 - sayma_rtm2: add filtered_clk_sel signal <Sebastien Bourdeauducq>
    * 9211304 - sayma_amc2: add filtered_clk_sel signal <Sebastien Bourdeauducq>
    * 9e59e41 - sayma_amc2: fix typo in previous commit <Sebastien Bourdeauducq>
    * 58d9c82 - sayma_amc2: fix ddram_32 assignments <Sebastien Bourdeauducq>
    * 57a7311 - Added support for the Xilinx AC701 FPGA development board <Tobias Rosenkranz>
    * f4fcd10 - fix previous commit <Sebastien Bourdeauducq>
    * 34f24f3 - zedboard: use Vivado toolchain <Sebastien Bourdeauducq>

Full submodule status
--
 3a6108a75be356a3dc53760d22782f1323248b6b edid-decode (remotes/origin/HEAD)
 01d8f819f15baf9a8cc5d96945a51e4d267ff564 flash_proxies (remotes/origin/HEAD)
 401554f94c5fbfae1a4de98504c5c2994a6f714a litedram (remotes/origin/HEAD)
 4d9e74f10a3fe7bf71ba9bde50f49689c6458dc5 liteeth (remotes/origin/HEAD)
 47e76f447f6e3d97aac2638a98f967d44db5c349 litepcie (remotes/origin/HEAD)
 db5d2f7881161ce5b9a10a0ab42555f884b9d7c1 litesata (remotes/origin/HEAD)
 7a9fa9d3b18362bf707dff25a78661395ef9ee7a litescope (remotes/origin/HEAD)
 7457a29b1a47fe15e81fa37f3bbdd510788f1d53 liteusb (remotes/origin/HEAD)
 49bafa481075e0bfbaf067b63c351ec29e993894 litevideo (remotes/origin/HEAD)
 a54b80b9b4eaa6defca99b0749da8426535bbb62 litex (v0.1-1333-ga54b80b9)
 742360f2ba4c400c6164908f03c6ca3d965f168b litex-renode (remotes/origin/HEAD)
 41922fde2a8c36cd0f99d4b7ebb3ba9c37ce1489 migen (0.6.dev-306-g41922fd)
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Reviewers

@ewenmcneill ewenmcneill ewenmcneill left review comments

@jimmo jimmo jimmo approved these changes

Assignees
No one assigned
Labels
None yet
Projects
None yet
Milestone
No milestone
Development

Successfully merging this pull request may close these issues.

third_party/qemu-litex not automatically updated if changed
3 participants
@mithro @ewenmcneill @jimmo