tinyfpga-bx: Add prog-port to Makefile #192

whatnick · 2019-08-06T08:22:23Z

Closes #191 Need to update docs to export PROG_PORT on WSL

tinyprog can auto-find the tinyfpga_bx if PROG_PORT is not specified.

mithro

Seems to be working now.

@ambrop72

* edid-decode changed from 6def7bc to 15df4ae * 15df4ae - Makefile: add CPPFLAGS <Hans Verkuil> * dc763d7 - Update email addresses <Hans Verkuil> * 726576d - edid-decode: add CTA-861.4/5 support <Hans Verkuil> * flash_proxies changed from a628956 to 1c21ee4 * 1c21ee4 - README: update <Robert Jördens> * litedram changed from d89b171 to 67de3ce * 67de3ce - Merge pull request timvideos#85 from antmicro/fix_databits <enjoy-digital> |\ | * 24851c9 - PhySettings: set missing databits parameter for S6QuarterRateDDRPHY <Mateusz Holenko> * | fef5303 - test: clean test_downconverter/test_upconverter (thanks sb0) <Florent Kermarrec> |/ * 7fbe0b7 - Merge pull request timvideos#84 from open-design/is42s16320 <enjoy-digital> |\ | * 5c66547 - modules: SDRAM: add IS42S16320 support <Antony Pavlov> |/ * 8e2df17 - modules: fix tRFC change on MT16KTF1G64HZ <Florent Kermarrec> * bc88cfa - modules: allow tRFC to be defined in ck or ns, fix some DDR3/DDR4 definitions (thanks @ambrop72 for the review) <Florent Kermarrec> * fbd7ae3 - modules: make IS43TR16128B consistent with others SDRAMModules <Florent Kermarrec> * 02448a3 - Merge pull request timvideos#83 from ambrop72/IS43TR16128B_125K <enjoy-digital> |\ | * d108970 - modules/ddr3: add IS43TR16128B_125K <Ambroz Bizjak> |/ * da68e21 - Merge pull request timvideos#82 from gsomlo/gls-expose-csr <enjoy-digital> |\ | * 65451f4 - examples/litedram_gen: allow direct access to CSR (I/O) registers <Gabriel L. Somlo> |/ * 50e1d47 - PhySettings: add databits to allow SoC to compute memory size more easily <Florent Kermarrec> * b93412b - examples: remove verilog simulation <Florent Kermarrec> * a7e46bb - example/litedram_gen: reserve_nmi_interrupt no longer exists <Florent Kermarrec> * 094fc2e - Merge pull request timvideos#79 from gsomlo/gls-ulong-addr <enjoy-digital> |\ | * 54d3312 - sdram_init: use "unsigned long" for address values <Gabriel L. Somlo> |/ * 3caaa2e - common/tXXDController: revert Yosys workarounds <Florent Kermarrec> * 44bbb93 - phy: add copyrights <Florent Kermarrec> * 6ddc2c8 - README: update <Florent Kermarrec> * 9190a76 - travis: simplify and add RISC-V toolchain to run examples <Florent Kermarrec> * e824288 - frontend/axi: move AXIBurst2Beat to LiteX <Florent Kermarrec> * be269da - frontend/axi: use definitions from LiteX <Florent Kermarrec> * e81b5a1 - sdram_init: set __attribute__((unused)) on command_px to avoid compilation warning <Florent Kermarrec> * c4161cf - examples: update sim <Florent Kermarrec> * 201a0e2 - test/test_examples: add nexys4ddr <Florent Kermarrec> * 69afaf5 - common: add separators, reorganize a bit <Florent Kermarrec> * 0bc241c - phy/ecp5ddrphy: use inline comments on ECP5DDRPHYInit <Florent Kermarrec> * c65ff97 - phy/ecp5ddrphy: simplify ECP5DDRPHYInit, integrate it in the PHY, add burstdet registers <Florent Kermarrec> * 4274db8 - common/TXXDcontroller: fix for compatibility with Yosys and vendor tools <Florent Kermarrec> * a74d5c9 - common/TXXDcontroller: set ready default value to 1 with self.comb instead of reset value <Florent Kermarrec> * cec35f3 - Merge pull request timvideos#77 from daveshah1/ecp5_75MHz <enjoy-digital> |\ | * fa26dcd - ecp5ddrphy: Shift read position forwards to fix higher frequencies <David Shah> |/ * 6715c1b - Merge pull request timvideos#76 from daveshah1/trellis_io <enjoy-digital> |\ | * 691d930 - ecp5ddrphy: Use triples for inputs to fix build with TRELLIS_IOs <David Shah> |/ * 9057f51 - phy: add ECP5 imports <Florent Kermarrec> * f660618 - phy: add initial ECP5DDRPHY <Florent Kermarrec> * 640194a - examples: add nexys4ddr_config <Florent Kermarrec> * 0ac1af3 - examples/litedram_gen: add DDR2 support <Florent Kermarrec> * f4184ec - example/litedram_gen: update, add descriptions of config parameters <Florent Kermarrec> * 79806aa - modules/ddr3: add MT41K64M16 <Florent Kermarrec> * ea6b841 - phy/s7ddrphy and usddrphy: add cmd_latency parameter <Florent Kermarrec> * fd3e9af - phy/s7ddrphy: fix cmd delays <Florent Kermarrec> * f61c8d9 - phy/s7ddrphy: make clk/cmd odelaye2s configurable <Florent Kermarrec> * e0224f4 - phy/usddrphy: make clk/cmd odelaye3s configurable <Florent Kermarrec> * liteeth changed from 77fa4bf to 2424e62 * 2424e62 - software: also include generated/mem.h <Florent Kermarrec> * e88fc50 - software: remote ethmac_mem.h dependency (no longer exists in LiteX) <Florent Kermarrec> * b318300 - phy/ku_1000basex: keep tx/rx in reset until pll is fully reseted and locked <Florent Kermarrec> * e6c35cd - phy/ku_1000basex: incease pll_reset <Florent Kermarrec> * 816f592 - phy: add initial ECP5RGMII PHY <Florent Kermarrec> * b4c1cfe - core/icmp: fix reply checksum when request checksum >= 0xf800 <Florent Kermarrec> * litepcie changed from 3804c49 to de6cd01 * de6cd01 - frontend/dma: ensure we finish LitePCIeDMAWriter transaction when DMA is disabled. <Florent Kermarrec> * 260c562 - frontend/wishbone: cleanup qword_aligned support <Florent Kermarrec> * 89b3920 - README: update <Florent Kermarrec> * 22310cc - phy: add initial Cyclone5 support <Florent Kermarrec> * 9cdb982 - phy/s7pciephy: rename external_phy to external_hard_ip <Florent Kermarrec> * 3b6cffd - frontend/wishbone: add qword_aligned parameter <Florent Kermarrec> * d191b1e - core: add endianness support <Florent Kermarrec> * 4df720a - examples/targets/dma: remove typo (dma connection is done internally in loopback mode) <Florent Kermarrec> * 14d852e - examples/targets/dma: remove soft reset, simplify crg, minor cleanups <Florent Kermarrec> * 64857af - phy/s7pciephy: improve presentation <Florent Kermarrec> * 55fa0d4 - phy/s7pciephy: remove pcie clk presence detection. <Florent Kermarrec> * f042273 - phy/s7pciephy: allow using external sources for the PHY. <Florent Kermarrec> * bd5d4dc - phy/s7pciephy: remove unnecessary reset on pcie clock domain <Florent Kermarrec> * ccfb201 - frontend/dma: update loop_status when request is sent <Florent Kermarrec> * litesata changed from b78a731 to 6fe4cce * 6fe4cce - examples/targets/bist: simplify analyzer <Florent Kermarrec> * 846bd62 - phy/a7sataphy: rework tx/rx_startup_fsm using liteiclink code <Florent Kermarrec> * 5e02ac9 - phy/a7sataphy: use proper transceiver name <Florent Kermarrec> * e63c8aa - examples/test/test_analyzer: use shorter import <Florent Kermarrec> * 319dd72 - examples/targets/bist: update <Florent Kermarrec> * df27cdf - examples/targets: add bist_nexys_video (still wip) <Florent Kermarrec> * 2ba5508 - Merge pull request timvideos#15 from enjoy-digital/artix7 <enjoy-digital> |\ | * 0b254b0 - examples/make: remove platform option <Florent Kermarrec> | * e0fc55c - examples/targets/bist: revert kc705/genesys2 bist example <Florent Kermarrec> | * cabc908 - example: add led blinking on refclk, add startup fsm to analyzer <Florent Kermarrec> | * d16b495 - examples: add more debug, rx/tx leds not blinking (no clock? bad init?) <Florent Kermarrec> | * 1519dc3 - targets/bist: use 100 MHz clock, fix reset polarity <Florent Kermarrec> | * 1fe543f - phy/a7sataphy: integrate GTPQuadPLL <Florent Kermarrec> | * ca47e05 - examples/targets/bist: start artix7 testing with sata_gen1 <Florent Kermarrec> | * 1fc848e - examples: add nexys_video support <Florent Kermarrec> | * 9152729 - phy/a7sataphy: update parameters from wizard <Florent Kermarrec> | * ef5d0b9 - phy: add initial a7sataphy <Florent Kermarrec> | * 12b5085 - phy/k7sataphy: remove drp interface (not used) <Florent Kermarrec> | * 246487c - phy/k7sataphy: improve readibility <Florent Kermarrec> | * 41f4446 - phy/k7sataphy: make GTXE2_CHANNEL instance similar to gtx_7series in liteiclink <Florent Kermarrec> | * 27df062 - phy: replace trx_dw with data_width <Florent Kermarrec> | * d52c7b8 - phy/k7sataphy: remove ones <Florent Kermarrec> | * 1d1da98 - phy/k7sataphy: refactor gtxe2_channel instance <Florent Kermarrec> | * 10d6376 - phy: move k7 phy to a single k7sataphy file <Florent Kermarrec> * 7299fef - example/make.py: create the build directory when building the core if not existing <Florent Kermarrec> * litescope changed from c1d8bdf to 2474ce9 * 2474ce9 - software/dump/common: change variable name for values2x loop (thanks keesj) <Florent Kermarrec> * 7f20aa4 - examples/make/build-core: create build directory if not existing <Florent Kermarrec> * litex changed from af52842f to 113f7f40 * 113f7f40 - Merge pull request timvideos#199 from ambrop72/no-ethmac-fix <enjoy-digital> |\ | * ca70ea91 - bios: Fix build when ethphy is present but ethmac is not. <Ambroz Bizjak> |/ * ab1f5804 - test/test_axi: remove litex.gen.sim import (was only useful for debug) <Florent Kermarrec> * 5318bcd3 - setup.py: add migen to install_requires <Florent Kermarrec> * 33d7cc5f - Merge pull request timvideos#198 from TomKeddie/tomk_20190610_artyspi <enjoy-digital> |\ | * 5346c368 - boards/arty : Add directly connected spi clk pin to avoid need for STARTUPE2 <Tom Keddie> * | 38a2d89a - test/test_code8b10b: add test_coding <Florent Kermarrec> * | 8fdd5220 - test/test_prbs: add PRBSGenerator/Checker tests <Florent Kermarrec> * | 243d7c76 - soc/cores: add PRBS (Pseudo Random Binary Sequence) Generator/Checker <Florent Kermarrec> * | cfa952b0 - tools/litex_term: exit on 2 consecutive CTRL-C <Florent Kermarrec> * | 1c34b4a0 - cpu/vexriscv: update submodule <Florent Kermarrec> * | 79665873 - doc: add litex-hub logo <Florent Kermarrec> * | 442d7358 - doc: redesign new logo <Florent Kermarrec> * | 59118627 - doc: add new logo <Florent Kermarrec> * | 850b311d - cpu/vexriscv: update submodule <Florent Kermarrec> * | 755a2660 - build/sim: allow configuring verilator optimization level <Florent Kermarrec> * | 4b6ad8aa - build/sim: allow defining start/end cycles for tracing <Florent Kermarrec> * | ecb60f6e - build/sim: use -O0 for verilator compilation <Florent Kermarrec> * | c64129dc - soc/integration/soc_core: list rocket as supported CPU <Florent Kermarrec> * | ca4e7811 - software/bios: change prompt to "litex" in green. <Florent Kermarrec> * | 8d0f008a - integration/soc_core: improve readibility (add separators/comments) <Florent Kermarrec> * | 55ebcc00 - test/test_targets: add de10lite <Florent Kermarrec> * | e545b15f - Merge pull request timvideos#196 from msloniewski/de10lite_support <enjoy-digital> |\ \ | * | 04ce4790 - boards/targets: add target for de10lite platform <msloniewski> | * | f2a740d5 - boards/platforms: add de10lite Terasic platform support <msloniewski> | * | a826aaca - build/altera: Add possibility to turn off generation of .rbf file <msloniewski> * | | 77805a5e - Merge pull request timvideos#195 from antmicro/extend_generated_headers <enjoy-digital> |\ \ \ | |/ / |/| | | * | 93b61a65 - integration/builder: generate flash_boot address to csv <Mateusz Holenko> | * | d0b019b1 - integration/builder: generate shadow_base address to mem.h and csv <Mateusz Holenko> |/ / * | cb2d4372 - Merge pull request timvideos#193 from gsomlo/gls-memcpy-fix <enjoy-digital> |\ \ | * | f88b85a3 - software/libbase: memcpy: simple, arch-width agnostic implementation <Gabriel L. Somlo> |/ / * | 42e9d097 - Merge pull request timvideos#192 from sutajiokousagi/pr_c99_types <Tim Ansell> |\ \ | * | ab0b2cac - fix signed char type to be explicitly signed <bunnie> * | | b0d35a49 - Merge pull request timvideos#191 from sergachev/master <Tim Ansell> |\ \ \ | * | | db890736 - fix csr_name in add_csr() <Ilia Sergachev> | * | | 40cbe3a9 - fix interrupt_name <Ilia Sergachev> |/ / / * | | b300c321 - test/test_targets: add de2_115, de1soc <Florent Kermarrec> * | | 220e2bdc - boards/platform/arty: add Arty A7-100 variant <Florent Kermarrec> * | | 8e6ecfb9 - Merge pull request timvideos#189 from open-design/terasic-boards <enjoy-digital> |\ \ \ | * | | 6cf1a814 - boards: add Terasic DE2-115 initial support <Antony Pavlov> | * | | 03725991 - boards: add Terasic DE1-SoC Board support <Antony Pavlov> * | | | 9682189b - Merge pull request timvideos#190 from sutajiokousagi/pr_c99_types <Tim Ansell> |\ \ \ \ | |/ / / |/| / / | |/ / | * | 200d413d - update stdint.h to include c99 types <bunnie> |/ / * | a48858f8 - Merge pull request timvideos#188 from gsomlo/gls-csr-cleanup <enjoy-digital> |\ \ | * | 273a3ea1 - soc/integration/cpu_interface: improve code legibility <Gabriel L. Somlo> |/ / * | 08a811b1 - soc/interconnect/gearbox: add msb_first/lsb_first order <Florent Kermarrec> * | 675f7830 - boards/targets/arty: generate 25MHz ethernet clock with S7PLL <Florent Kermarrec> * | d7b00c8c - Merge pull request timvideos#187 from open-design/indent <Tim Ansell> |\ \ | * | 26e6355f - litex/boards/targets: don't use tab for indentation <Antony Pavlov> |/ / * | 51095112 - soc/interconnect/axi: add round/robin arbitration between writes/reads <Florent Kermarrec> * | 0fb6342f - travis: update RISC-V toolchain <Florent Kermarrec> * | 961101d8 - bios/irc: remove compilation workaround <Florent Kermarrec> * | cd543b29 - README: update RISC-V toolchain <Florent Kermarrec> * | 7e837bf1 - .gitmodules/rocket: switch to https://github.com/enjoy-digital/rocket-litex-verilog <Florent Kermarrec> * | 712977a0 - software/bios/isr.c: workaround compilation issue (need to be fixed) <Florent Kermarrec> * | 28ba8b32 - soc/integration/soc_core: revert default mem_map (do specific RocketChip remapping for now) <Florent Kermarrec> * | cf369c43 - boards/targets: revert default sys_clk_freq on nexys4ddr/versa_ecp5 (but add parameter to configure it) <Florent Kermarrec> * | aa640f29 - Merge pull request timvideos#186 from gsomlo/gls-rocket <enjoy-digital> |\ \ | * | 019fd940 - fixup: generated-verilog submodule for experimental Rocket support <Gabriel L. Somlo> | * | 1a530cf2 - soc/cores/cpu/rocket: Support for 64-bit RocketChip (experimental) <Gabriel L. Somlo> |/ / * | 3de49118 - Merge pull request timvideos#185 from gsomlo/gls-sim-sdram <enjoy-digital> |\ \ | |/ |/| | * e90caa86 - tools/litex_sim: restore functionality of '--with-sdram' option <Gabriel L. Somlo> |/ * 3a72688b - Merge pull request timvideos#183 from xobs/usb-to-0x43 <enjoy-digital> |\ | * 014c9505 - remote: usb: print "access denied" error <Sean Cross> | * faf6554c - remote: usb: use 0x43/0xc3 for packet header <Sean Cross> |/ * 10670e22 - soc/cores/minerva: update to latest <Florent Kermarrec> * a3134f13 - Merge pull request timvideos#182 from gsomlo/gls-nexys4-eth-fixup <enjoy-digital> |\ | * 5707bdc0 - boards/nexys4ddr: ethernet support fix-up <Gabriel L. Somlo> |/ * 0a8699f1 - Merge branch 'master' of http://github.com/enjoy-digital/litex <Florent Kermarrec> |\ | * 1ea22d49 - software/include/base/csr-defs.h: add specific CSR_IRQ_MASK/PENDING for Minerva <Florent Kermarrec> * | 526ba1b1 - soc_core: remove csr_expose and add add_csr_master method <Florent Kermarrec> |/ * f2570701 - software/bios/boot: remove specific linux commands (not needed with device tree) <Florent Kermarrec> * 938d00c2 - boards/targets/de0nano: reduce to 50MHz sys_clk, simplify CRG <Florent Kermarrec> * 11838bae - platforms/de0nano: change serial pins (put then next to the GND pin) <Florent Kermarrec> * eb6fa458 - cpu/vexriscv/core: update <Florent Kermarrec> * 0cad80e9 - cpu/vexriscv: update submodule (new linux variant) <Florent Kermarrec> * 5f6e7874 - boards/nexys4ddr: add ethernet support (RMII 100Mbps) <Florent Kermarrec> * 0ba1cb87 - boards/targets/netv2: +x <Florent Kermarrec> * 2f2b9b31 - soc/cores: remove cordic <Florent Kermarrec> * 6e4ac1c4 - LICENSE: clarify <Florent Kermarrec> * 67159349 - soc/interconnect: remove axi_lite <Florent Kermarrec> * 745d83a3 - boards: add initial NeTV2 support (clocks, leds, dram, ethernet) <Florent Kermarrec> * a49d170a - soc/integration/soc_sdram: simplify/fix main_ram_size computation using new databits value of the phy <Florent Kermarrec> * 7445b9e2 - soc/integration/soc_core: allow user to defined internal csr/interrupts <Florent Kermarrec> * f333abcf - boards/targets: use new add_csr method <Florent Kermarrec> * d76a2c7d - tools/litex_sim: add uart csr (required when with_uart=False with new add_csr method) <Florent Kermarrec> * b6be534c - soc/integration/soc_core: rework csr assignation/reservation <Florent Kermarrec> * 3f09af6d - boards/targets: declare ethmac interrupt with new add_interrupt method <Florent Kermarrec> * 2abb3e80 - Merge branch 'master' of http://github.com/enjoy-digital/litex <Florent Kermarrec> |\ | * c11eb4b5 - Merge pull request timvideos#179 from gsomlo/gls-xtra-addrlen <enjoy-digital> | |\ | | * c264a009 - soc/integration/cpu_interface: more arch-specific address size fixes <Gabriel L. Somlo> | |/ * | 47dc8758 - integration/soc_core: rework interrupt assignation/reservation <Florent Kermarrec> * | 3ee9ce05 - test/test_targets: fix test_ulx3s name <Florent Kermarrec> * | 435cdad0 - boards/targets: fix ulx3s/versa_ecp5 build <Florent Kermarrec> * | 8caa38bc - cpu: add `reserved_interrupts` property <Mateusz Holenko> * | ff517915 - boards/targets: make sys_clk_freq a parameter <Florent Kermarrec> |/ * a8cbe4ad - boards/targets/minispartan6: for now revert experimental s6pll clocking <Florent Kermarrec> * 6fcbf10e - boards/plarforms/minispartan6: default to xc6slx25 <Florent Kermarrec> * b7e37133 - bios/boot/ update linux memory mapping <Florent Kermarrec> * 190ff89a - tools/litex_term: add json support to load images to memory, allow passing speed as float <Florent Kermarrec> * a50aff2c - Merge pull request timvideos#178 from daveshah1/vexriscv_linux_yosys <enjoy-digital> |\ | * a048ba47 - vexriscv: Fix some floating signals <David Shah> |/ * fcd518b5 - bios/boot: add specific flash_boot for linux with vexriscv <Florent Kermarrec> * 1ba1ad9a - bios/boot: rename MM_RAM to EMULATOR_RAM <Florent Kermarrec> * fbb24720 - soc/get_mem_data: add direct support for regions <Florent Kermarrec> * 0714816f - soc/interconnect/axi: add AXI2AXILite converter and use it in AXI2Wishbone <Florent Kermarrec> * c6d0d234 - soc/interconnect/axi: add AXI Lite definition <Florent Kermarrec> * 9fab4752 - soc/interconnect/axi: add comment on axi signas that are present but not used <Florent Kermarrec> * 59890763 - cores/cpu/vexriscv: add VexRiscvTimer and use it for the linux variant <Florent Kermarrec> * 21bf1038 - bios/boot: add liftoff banner just before booting <Florent Kermarrec> * 8f4685b3 - bios/boot/netboot: only get boot.bin as default, add linux_vexriscv netboot config <Florent Kermarrec> * 6cf1ff09 - soc/interconnect/axi: connect axi.ar/aw when selecting write or read <Florent Kermarrec> * 6affc56a - soc/interconnect/axi: wishbone address shift is not always 2, make it generic <Florent Kermarrec> * 698bc882 - soc/interconnect/wishbone: allow setting adr_width (default to 30) <Florent Kermarrec> * 4dccb8a9 - soc/interconnect/axi/AXI2Wishbone: add buffer on axi command to be sure command is accepted before response is sent <Florent Kermarrec> * 9f8f0eb1 - build/sim: update tapcfg <Florent Kermarrec> * 2515c7b0 - Merge pull request timvideos#176 from gsomlo/gls-ulong-addr <enjoy-digital> |\ | * 5c2b8685 - software: use "unsigned long" for address values, also 8-byte alignment <Gabriel L. Somlo> |/ * 74d37465 - test/test_targets: comment bad variant tests for now <Florent Kermarrec> * 5c1d9805 - soc/interconnect/axi: add burst support to AXI2Wishbone <Florent Kermarrec> * 6de27135 - soc/interconnect/axi: add capabilities to AXIBurst2Beat and simplify/optimize <Florent Kermarrec> * 305b8879 - integration/soc_core: use cpu name as cpu-type for all cpus (mor1kx was instanciated with or1k) <Florent Kermarrec> * 4e50f36b - build/tools: add deprecated_warning <Florent Kermarrec> * b40d1b73 - cpu_interface: default to gcc for all cpus unless told otherwise (mor1kx default was clang) <Florent Kermarrec> * dbb71af1 - cpu: use property methods to return name, endianness, gcc triple/flags, linker output format <Florent Kermarrec> * d828c3a5 - cpu: integrate nmigen version of Minerva, add submodule <Florent Kermarrec> * 2c3c6bdf - Updating documents from LiteX BuildEnv Wiki <Florent Kermarrec> * bf27869a - fix vexriscv build <Kurt Kiefer> * 2d5bae3d - Merge pull request timvideos#175 from mithro/cpu-docs <enjoy-digital> |\ | * 5cbc5bc1 - Adding testing of cpu variants. <Tim 'mithro' Ansell> | * 71a83731 - Work with no `cpu_variant` provided. <Tim 'mithro' Ansell> | * 65650919 - Updating documents from LiteX BuildEnv Wiki <Tim 'mithro' Ansell> | * a43de819 - Updating documents from LiteX BuildEnv Wiki <Tim 'mithro' Ansell> | * 39c579ba - Standardize the `cpu_variant` strings. <Tim 'mithro' Ansell> | * e42de8fe - docs: Adding script to pull useful docs from LiteX BuildEnv's wiki. <Tim 'mithro' Ansell> * | 3a2e2836 - .gitmodules: use our VexRiscv-verilog <Florent Kermarrec> |/ * 78c09125 - soc/integration/soc_core: fix get_mem_data when not file is not multiple of 4 bytes <Florent Kermarrec> * 0175f86c - soc/integration/soc_core: fix get_mem_data for json files <Florent Kermarrec> * 4443b507 - soc/integration/soc_core: add integrated_sram_init <Florent Kermarrec> * f27084c6 - soc/integration/cpu_interface: fix banner in get_mem_header <Florent Kermarrec> * 5ec99d94 - Merge pull request timvideos#173 from gsomlo/gls-git-revision <enjoy-digital> |\ | * d21cba2f - build: handle exceptional case when litex/migen not deployed as git repo <Gabriel L. Somlo> |/ * 27fbb814 - tools/remote/csr_builder: allow comments in csv file and cleanup <Florent Kermarrec> * e8f3c491 - software/libnet/microudp: rearrange send_packet, add comments and remove txlen padding <Florent Kermarrec> * 44e0cdda - software/libnet/microudp: speed-up ARP by changing timeout/tries <Florent Kermarrec> * 3ee78a5b - build/tools: fix typo <Florent Kermarrec> * f0fe9f3c - setup.py: add short names for tools <Florent Kermarrec> * 9ded2eb2 - tools/litex_term: change TERM prompt to LXTERM <Florent Kermarrec> * 475deb51 - build: add migen and litex git revision to generated file <Florent Kermarrec> * 8b5cf295 - build/tools: git_revision is not doing what we want, return "--------" for now <Florent Kermarrec> * 228f2867 - litex_setup: revert default install behaviour but add --user support <Florent Kermarrec> * 9fbbf928 - Merge pull request timvideos#171 from keesj/develop_as_user <enjoy-digital> |\ | * 24bdb648 - Install development packages in the user directory <Kees Jongenburger> * | 0f60ec35 - tools/litex_server: fix comms import <Florent Kermarrec> * | 68f12495 - soc/integration: also add sha-1/date to generated software files <Florent Kermarrec> * | 42574122 - build: add sha-1/date to generated verilog, change git_version to git_revision <Florent Kermarrec> |/ * f7c0b118 - test/test_targets: cover all platforms <Florent Kermarrec> * 818dfae1 - boards/platforms/ulx3s: fix default clock <Florent Kermarrec> * 17b6164c - boards/platforms/sp605: apply same simplifications than on others platforms <Florent Kermarrec> * 24bf0293 - boards/platforms: add SP605 <Michael Betz> * 10cf0fde - cores/cpu/vexriscv: fix wrong revert <Florent Kermarrec> * d2ad1441 - targets/ac701: cleanup and make it similar to others targets. <Florent Kermarrec> * a24bf72f - targets/xilinx: remove keep attribute on clock going to idelayctrl <Florent Kermarrec> * ea8dbff8 - boards/platform/ac701: add proper copyright, cleanup to be similar to others platforms <Florent Kermarrec> * 0122982e - boards/platforms/kc705: provide only one default programmer as others platforms <Florent Kermarrec> * 89a59026 - boards: Xilinx ac701 dev board support <Vamsi K Vytla> * 88b882c7 - build/xilinx/ise.py: write .v file for post synthesis sim <Michael Betz> * 7396ebbb - build/xilinx/programmer: cleanup XC3SProg position parameter <Florent Kermarrec> * f579cbc6 - build/xilinx/programmer: add position parameter to XC3SProg <Michael Betz> * fb4f8818 - .gitignore: ignore tilde files <Vamsi K Vytla> * 535d8672 - targets/minispartan6: use S6PLL in CRG <Florent Kermarrec> * 40342404 - cores/clock: add divclk_divide_range on S6PLL/S6DCM <Florent Kermarrec> * 0d282f38 - cores/clock: use common XilinxClocking class for all Xilinx clocking modules <Florent Kermarrec> * 83699ea0 - cores/clock: add initial Spartan6 PLL/DCM support <Michael Betz> * eff141da - build: add git version (sha-1) used to create the scripts <Florent Kermarrec> * cc141a64 - build: scripts are generated by LiteX <Florent Kermarrec> * 115c842e - build/xilinx/vivado: cleanup pull request timvideos#170 <Florent Kermarrec> * 3b24b8d5 - Merge pull request timvideos#170 from ldoolitt/master <enjoy-digital> |\ | * fda18fd6 - build/xilinx/vivado: only try Xilinx setup if vivado is not already in the path <Larry Doolittle> |/ * 7d278854 - global: switch to VexRiscv as the default CPU <Florent Kermarrec> * 28d80bd6 - ci: fix test_targets/test_simple <Florent Kermarrec> * b7f53fb9 - test: remove waveforms generation <Florent Kermarrec> * e98ac680 - travis: simplify, enable and add RISC-V toolchain to build targets <Florent Kermarrec> * 8c789970 - boards/platforms: add separators, cleanup imports <Florent Kermarrec> * cb8c26d1 - boards/platforms: provide only one default programmer per platform. <Florent Kermarrec> * e1d202df - boards/platforms/kc705: only keep Vivado support <Florent Kermarrec> * 53c7be6e - boards: always define timing constraints the same way (1e9/freq_mhz) <Florent Kermarrec> * 02ffbed5 - boards/targets/ulx3s: allow running test_targets on it <Florent Kermarrec> * 5a1925df - boards/targets: add keep attribute directly in crg <Florent Kermarrec> * 67a79d7c - Merge pull request timvideos#167 from xobs/network-flag-check <enjoy-digital> |\ | * f71b8d4f - litex_server: check socket flags exist before using them <Sean Cross> |/ * 9ee6c35b - tools: move from litex.soc.tools to litex.tools and fix usb.core import <Florent Kermarrec> * 49fd93ae - Merge pull request timvideos#165 from xobs/vexriscv-cpu-reset-address <enjoy-digital> |\ | * c780fb22 - Merge branch 'master' of https://github.com/enjoy-digital/litex <Sean Cross> | |\ | * | e2cf45b8 - cpu: vexriscv: allow cpu_reset_address to be overridden <Sean Cross> * | | ca6065a6 - Merge pull request timvideos#164 from xobs/litex-usb-server <enjoy-digital> |\ \ \ | * | | c6918364 - utils: litex_server: add usb support <Sean Cross> | * | | 9dd59d63 - tools: remote: add usb communications protocol <Sean Cross> * | | | 9cbed91b - soc/interconnect/axi: add AXIBurst2Beat <Florent Kermarrec> * | | | 5a8115d9 - soc/interconnect/avalon: add description <Florent Kermarrec> | |_|/ |/| | * | | fa956086 - soc/integration/soc_zynq: fix HP0 connections <Florent Kermarrec> * | | a78ca2de - build/xilinx/vivado: only set library for vhdl files (not supported for verilog/system-verilog) <Florent Kermarrec> |/ / * | a92e90b2 - soc/interconnect: add avalon with converters to/from native streams <Florent Kermarrec> * | d860eeea - Merge pull request timvideos#162 from antmicro/full-conf-vexriscv <enjoy-digital> |\ \ | * | 40de01bc - vexriscv: Add full and full_debug CPU variant <Joanna Brozek> * | | ce81a39c - Merge pull request timvideos#163 from gsomlo/gls-verilated-cmdargs <enjoy-digital> |\ \ \ | |/ / |/| | | * | e1683078 - build/sim/core: Initialize Verilator commandArgs <Gabriel L. Somlo> |/ / * | 017147c6 - build/altera: switch to sdc constraints, add add_false_path_constraints method <Florent Kermarrec> * | 1275e2f1 - build/xilinx/vivado: set quiet property on MultiReg/AsyncResetSynchronizer constraints <Florent Kermarrec> * | c252972b - soc/cores/clock: add divclk_divide/vco_margin support on S7/Ultrascale <Florent Kermarrec> * | f986974d - soc/cores/clock: improve presentation <Florent Kermarrec> * | 538ca59a - build/xilinx/vivado: round period constraints to lowest picosecond <Florent Kermarrec> * | 66a74b15 - Merge pull request timvideos#161 from enjoy-digital/litex_server_arguments <enjoy-digital> |\ \ | * | a2bc4bb7 - litex_server: set socket.SO_REUSEPORT to avoid waiting 60s in case of unclean termination <Florent Kermarrec> | * | be99083e - litex_server: add message and exit when mandarory arguments are missing. <Florent Kermarrec> | * | db11aec9 - litex_server: allow setting bind port, remove auto-incrementing on bind_port <Florent Kermarrec> | * | 76bc5785 - litex_server: refactor parameters and to allow setting bind address <Florent Kermarrec> |/ / * | 13a76ec7 - software/libnet/microudp: simplify txbuffer managment <Florent Kermarrec> * | 3441eb05 - software/libnet/microudp: cleanup eth_init <Florent Kermarrec> * | 92a79c6d - software/libnet/microudp: simplify rxbuffer managment <Florent Kermarrec> * | fdeff7f6 - software/libnet/microudp: set raw frame size to ETHMAC_SLOT_SIZE <Florent Kermarrec> * | 1569e2e0 - software/libnet: remove use of ethmac_mem.h <Florent Kermarrec> * | c7ac9676 - bios/sdram: add __attribute__((unused)) on cdelay <Florent Kermarrec> * | 7e53bff3 - litex_setup: add litesata <Florent Kermarrec> * | 792245f1 - boards/targets/kcu105: add Ethernet (with 1Gbps SFP adapter) <Florent Kermarrec> * | f8dcdb70 - software/libnet: add #ifdef on eth_init <Florent Kermarrec> * | e475cfbb - Merge pull request timvideos#158 from vbuitvydas/altera-contrib <enjoy-digital> |\ \ | * | 04939990 - litex/build/altera/quartus: changes to make top level assigment in .qsf file with build name <vytautasb> | * | 8558065f - litex/build/altera/common: added reset synchronizer <vytautasb> |/ / * | 866fa344 - integration/soc_zynq: fix missing SoCCore.do_finalize <Florent Kermarrec> * | 794c3c58 - integration/soc_zynq: add add_hp0 method <Florent Kermarrec> * | 38d404c3 - integration/soc_zynq: use add methods to add optional peripherals <Florent Kermarrec> * | 7375856b - integration/soc_zynq: connect axi signals that were missing <Florent Kermarrec> * | b15fd9d8 - interconnect/axi: add missing axi signals <Florent Kermarrec> * | f95748d1 - Merge pull request timvideos#157 from CBJamo/master <enjoy-digital> |\ \ | * | 1f0b3f81 - Add ifdef check for MAIN_RAM_SIZE <Caleb Jamison> |/ / * | f452d3e9 - README: bump copyright year <Florent Kermarrec> * | dd214d2d - bios/main: align SoC info, show CPU speed on CPU line, show L2 <Florent Kermarrec> * | 6599f7bb - bios/main: move sdrinit <Florent Kermarrec> * | b92b89ab - bios/main: print boot sequence only if sdr_ok <Florent Kermarrec> * | f4369c8f - bios/main: remove csr functions (not used and only supported by lm32), improve help presentation <Florent Kermarrec> * | 66dffb70 - software/bios: improve readibility, add soc informations <Florent Kermarrec> * | e8559990 - Merge pull request timvideos#156 from gsomlo/gls-axi-width <enjoy-digital> |\ \ | * | 449632e4 - soc/interconnect/axi: data/address length cleanup <Gabriel L. Somlo> |/ / * | 552b0243 - soc/interconnect/axi: remove dead code (thanks gsomlo) <Florent Kermarrec> * | b682dacd - Merge pull request timvideos#154 from daveshah1/yosys_xilinx_edif <enjoy-digital> |\ \ | * | 57e1ccd5 - build/xilinx: Update Yosys write_edif parameters <David Shah> * | | fd7ed6c1 - utils/litex_sim: fix main_ram_size <Florent Kermarrec> * | | 3f386dad - soc_core/get_mem_data: add json support <Florent Kermarrec> * | | 7bc13ba8 - build/microsemi/libero_soc: add linux build script support <Florent Kermarrec> * | | 7b88980d - vexriscv: allow user to use an external variant <Florent Kermarrec> * | | b04a756a - vexriscv/core: fix min variant <Florent Kermarrec> * | | a549f094 - utils/litex_sim: handle cpu_endianness for rom-init/ram-init <Florent Kermarrec> * | | 411bca79 - utils/litex_sim: increase default integrated_main_ram_size to 256MB, automatically boot on main_ram when ram_init is specified <Florent Kermarrec> * | | 7ec3ed4d - Merge pull request timvideos#153 from railnova/fix_utils <enjoy-digital> |\ \ \ | * | | aed2e9b4 - [fix] utils was not installed from pip <chmousset> | |/ / * | | 3543b567 - Merge pull request timvideos#152 from gsomlo/gls-trellis-svf <enjoy-digital> |\ \ \ | |/ / |/| | | * | b014c719 - build/lattice/trellis: also generate bitstream in svf format <Gabriel L. Somlo> |/ / * | 317dba83 - software/bios/sdram: use specific ERR_DDRPHY_BITSLIP/NMODULES computation <Florent Kermarrec> * | 7de1fe51 - targets/versa_ecp5: update ECP5DDRPHY on BaseSoC, add EthernetSoC <Florent Kermarrec> * | ca63db40 - bios/sdram: use burstdet detection for ECP5DDRPHY init <Florent Kermarrec> |/ * 2ebfab5e - Merge pull request timvideos#150 from daveshah1/trellis_bus_fixes <enjoy-digital> |\ | * ebe8f600 - lattice/common: Fix tristate buses with Trellis <David Shah> |/ * 935f3a53 - boards/ulx3s: add device selection parameter <Florent Kermarrec> * e6f97e08 - targets/ulx3s: use AsyncResetSynchronizer and derivate sys_clk/sys_clk_ps constraints from clk25 <Florent Kermarrec> * 5ef28bdf - build/lattice/trellis: add package support <Florent Kermarrec> * 1b34c07d - build/lattice/trellis: basecfg now integrated in nextpnr <Florent Kermarrec> * 7e995eb4 - boards/targets/ulx3s: allow building with diamond or trellis <Florent Kermarrec> * 4bf789ea - soc/software/bios/boot: add vexriscv workaround <Florent Kermarrec> * 1fd81c28 - soc/integration: add initial SoCZynq SoC <Florent Kermarrec> * 3c527dcb - soc/interconnect: add initial axi code with bus definition and AXI2Wishbone <Florent Kermarrec> * ed257879 - test: add test_axi_lite (with test code from soc/interconnect/axi_lite lightly modified) <Florent Kermarrec> * 4aa07f2a - soc/interconnect: rename axi to axi_lite <Florent Kermarrec> * 6a4c133c - test: add basic test_csr <Florent Kermarrec> * c9f9e237 - Merge pull request timvideos#149 from daveshah1/versa_trellis <enjoy-digital> |\ | * ff7e0fab - versa_ecp5: Add option to build with Trellis <David Shah> | * 024b41c5 - trellis: Add LPF frequency constraints and remove -nomux <David Shah> * | e38dfd99 - soc/software/sdram: fix compilation on ultrascale <Florent Kermarrec> |/ * 5f29a12e - targets/versa_ecp5: integrate DDR3 <Florent Kermarrec> * 3dd529e4 - soc/software/bios/sdram: add ECP5 support <Florent Kermarrec> * 2fd6d0e7 - soc/software/bios/sdram: improve write_level robustness <Florent Kermarrec> * 36772b75 - soc/software/bios/sdram: improve sdrlevel readibility <Florent Kermarrec> * 6a980781 - soc/software/bios/sdram: add helpers for rst/inc of delays <Florent Kermarrec> * dad7b292 - Merge pull request timvideos#148 from daveshah1/versa_remove_n <enjoy-digital> |\ | * 321dd8fc - versa_ecp5: Remove negative diff IO pins <David Shah> |/ * c03b1ad1 - platforms/versa_ecp5: add ddram pins <Florent Kermarrec> * ff155a47 - soc/tools/remote/comm_uart: be sure to flush in waiting bytes before read and write <Florent Kermarrec> * d3ecdd99 - soc/cores/clock: add actual clk_freqs to config <Florent Kermarrec> * migen changed from 0.6.dev-241-gafe4405 to 0.6.dev-283-g562c046 * 562c046 - Correct URL of logo Signed-off-by: Chipmuenk <mail@chipmuenk.de> <Chipmuenk> * db7ce84 - updated packaging infos <Chipmuenk> * a9e5029 - platforms: add de10lite support <msloniewski> * a69e1fd - altera/quartus: fix generated build script <msloniewski> * 1b804d7 - platforms: add max1000 support <msloniewski> * bc90344 - metlino: v1.0rc5 <Sebastien Bourdeauducq> * 9031bfe - metlino: add VHDCI EEM carrier connector <Sebastien Bourdeauducq> * 83b209e - metlino: add LEDs, I2C, Si5324, transceivers <Sebastien Bourdeauducq> * 4289590 - metlino: set bitstream properties <Sebastien Bourdeauducq> * aea0841 - metlino: add gth_clk200 and port0 <Sebastien Bourdeauducq> * 7299f4e - metlino: add spiflash <Sebastien Bourdeauducq> * 6815691 - metlino: use same SDRAM constraints as Sayma <Sebastien Bourdeauducq> * 42fe506 - metlino: update pins to 1.0rc4 <Sebastien Bourdeauducq> * 54d666d - Lattice iCE40: add comment on the polarity of differential I/O pairs <airwoodix> * 090ece7 - Lattice iCE40: pass positive pin to SB_IO in DifferentialInput <airwoodix> * ee3508b - Revert e43cd74 <airwoodix> * e43cd74 - Lattice iCE40: fix DifferentialInput polarity <airwoodix> * e6d02be - humpback: fix serial pinouts (crossover cables) <airwoodix> * c8cae39 - Lattice iCE40: implement DifferentialInput <Etienne Wodey> * a6f9cbd - Add Sinara Humpback platform (timvideos#177) <Étienne Wodey> * 4e66a71 - Fix `-vlgincdir` for xst. <Tim 'mithro' Ansell> * edcadbc - sayma_rtm2: si5324_clkout -> cdr_clk_clean <Sebastien Bourdeauducq> * 49b9d8a - sayma_amc2: add rtm_amc_link <Sebastien Bourdeauducq> * 0080bed - sayma_rtm2: add AFE test pins <Sebastien Bourdeauducq> * 032340d - sayma_rtm2: add rtm_amc_link <Sebastien Bourdeauducq> * 8bf0ab8 - sayma_rtm2: fix clk50 IOStandard <Sebastien Bourdeauducq> * 5dc0b23 - sayma_rtm: select correct speed grade and IDCODE for v2 <Sebastien Bourdeauducq> * 98a075c - sayma_rtm: update for v2.0rc4 <Sebastien Bourdeauducq> * cd71a2a - fix permissions <Sebastien Bourdeauducq> * 5a843a1 - sayma_amc: update gth_clk200, add DDMTD signals <Sebastien Bourdeauducq> * 2154882 - sayma_amc: OVERTEMPPOWERDOWN is called OVERTEMPSHUTDOWN on Ultrascale <Sebastien Bourdeauducq> * 3773947 - sayma_amc: si5324_clkout -> cdr_clk_clean <Sebastien Bourdeauducq> * 383512b - sayma_amc2: update to v2.0rc4 <Sebastien Bourdeauducq> * 936732f - add sayma_rtm2 <Sebastien Bourdeauducq> * d482b93 - sayma_amc2: add ddrXX_clk <Sebastien Bourdeauducq> * 25646d4 - sayma_amc2: enable OVERTEMPPOWERDOWN <Sebastien Bourdeauducq> * 9fd7a48 - remove Roach <Sebastien Bourdeauducq> * 9d90900 - sayma_amc: use LVDS for serwb <Sebastien Bourdeauducq> * 3da7113 - sayma_amc: fix aux_clk I/O standard <Sebastien Bourdeauducq> * 9a25f90 - sayma_amc: fix v2 platform name <Sebastien Bourdeauducq> * 7765238 - add Sayma AMC v2 platform <Sebastien Bourdeauducq> * ae42105 - migen: replace `collections` with `collections.abc` as necessary (timvideos#176) <Sean Cross> Full submodule status -- 15df4aebf06da579241c58949493b866139d0e2b edid-decode (remotes/origin/HEAD) 1c21ee44a2b3936f62e4b43f2bcbf63ce9404691 flash_proxies (heads/master) 67de3cee14b13beabc90804e3b62c66e028fd951 litedram (heads/master) 2424e62bf9637c2623b627a56aca7a3f90349e92 liteeth (heads/master) de6cd01d3f158387337bf4f47fd5a351ec2c3267 litepcie (heads/master) 6fe4cceaab77d6a117fa539f461b3ae9ca7e668e litesata (heads/master) 2474ce9db23e4d06bff4bbeacf0051efa3042f37 litescope (heads/master) 0a9110f901182a1233cc4e64b6e39175f6784621 liteusb (heads/master) 98e145fba8c25394e9958bad67e2a457d145127e litevideo (heads/master) 113f7f408e7c95150011c55ca473f45befb7f9bb litex (remotes/origin/HEAD) 562c0466443f859d6cf0c87a0bb50db094d27cf4 migen (0.6.dev-283-g562c046)

* litedram changed from f51052f to 47a0d5f * 47a0d5f - litedram_gen/LiteDRAMUSDDRPHYCRG: remove AsyncResetSynchronizer on sys/sys4x (reset handled by USIDELAYCTRL). <Florent Kermarrec> * 02e67ec - Merge pull request timvideos#192 from antmicro/jboc/port-adaptation <enjoy-digital> |\ | * 22bd01c - frontend/wishbone: simplify by reusing LiteDRAMNativePortConverter <Jędrzej Boczar> | * b0bde29 - frontend/wishbone: fix wb2native missing wdata.ready when wb/port data widths differ <Jędrzej Boczar> | * 79314f9 - frontend/wishbone: fix wdata.valid being high with old data, use cmd.last=1 <Jędrzej Boczar> | * 000a352 - frontend/adaptation: delay sending write commands to prevent data loss during up-conversion <Jędrzej Boczar> | * 84fb7d3 - frontend/adaptation: refactor up-converter logic to use FSM for clarity <Jędrzej Boczar> | * efe9a44 - frontend/adaptation: clean up LiteDRAMNativePortUpConverter code <Jędrzej Boczar> | * 2f35e97 - frontend/adaptation: fix error when read follows write to the same address <Jędrzej Boczar> | * 1587ee3 - frontend/adaptation: use port.cmd.last instead of port.flush in up-converter <Jędrzej Boczar> | * 35fa91c - test/crossbar: up-conversion with mode="both" should be working now <Jędrzej Boczar> | * 9b90a56 - frontend/adaptation: combine read/write port up-converters and extend tests <Jędrzej Boczar> | * 762cd6d - test/adaptation: add port converter tests with mode="both" <Jędrzej Boczar> | * 7a0f7a7 - test/common: fix error in test data <Jędrzej Boczar> | * 1cc9656 - test/crossbar: improve NativePortDriver to use separate generatos on data paths <Jędrzej Boczar> | * 025e280 - test/crossbar: fix test that was not being run <Jędrzej Boczar> * 71b991e - Merge pull request timvideos#210 from oskirby/ddr3-tdqs-mode <enjoy-digital> |\ | * 805a374 - Add support for TDQS mode. <Owen Kirby> |/ * c01e868 - phy/gensdrphy/HalfRateGENSDRPHY: review/simplify and reduce read_latency by 1. <Florent Kermarrec> * litescope changed from 15179cb to a80c964 * a80c964 - Merge pull request timvideos#22 from antmicro/jboc/test-script <enjoy-digital> * 8b0274d - examples: add a more general script for testing <Jędrzej Boczar> * litex changed from 7bf191ca to abc49964 * abc49964 - tools/litex_json2dts: add missing copyrights. <Florent Kermarrec> * aed0dcee - setup: add litex_json2dts to console_scripts. <Florent Kermarrec> * b64209b3 - Merge pull request timvideos#620 from antmicro/add_litex_json2dts <enjoy-digital> |\ | * fafa844a - json2dts: Add Linux DT generation script <Mateusz Holenko> * 0ca99b79 - build/sim/config: add default_clk/default_clk_freq parameters for retro-compatibility with previous API. <Florent Kermarrec> * 696ea468 - build/sim: use json_object_get_int64 instead of json_object_get_uint64. <Florent Kermarrec> * 382c1a3a - Merge pull request timvideos#619 from antmicro/jboc/sim-clocker <enjoy-digital> * f778ff09 - build/sim: improve timebase calculation (strict checks) and update modules <Jędrzej Boczar> * c1ae7e59 - build/sim: allow for arbitrary clocks generation using clockers <Jędrzej Boczar> * 38054874 - build/sim: use a real timebase in the simulation <Jędrzej Boczar> * litex-boards changed from 2ce24df to ee28d7b * ee28d7b - targets/ulx3s/add_oled: simplify. <Florent Kermarrec> * 623faa9 - Merge pull request timvideos#96 from pepijndevos/oled <enjoy-digital> |\ | * eba7037 - add optional OLED peripheral to ULX3S target <Pepijn de Vos> |/ * 929e55d - platforms/trellisboard: add SDCard PMOD pins. <Florent Kermarrec> * 5fd3e8d - ecpix5: add SDCard. <Florent Kermarrec> * f058181 - README: fix typo. <Florent Kermarrec> * 94ccf1d - targets/trellisboard: simplify clocking when no DDR3, remove firmware_ram (was here for debug). <Florent Kermarrec> * ecdc1ef - README: add missings . <Florent Kermarrec> * 361afa7 - README: add links to LiteX's wiki. <Florent Kermarrec> * 02c0c0a - README: add board picture and fix a few typos. <Florent Kermarrec> * eb8a484 - targets/de10nano: fix typo. <Florent Kermarrec> * 2cef54a - targets/colorlight_5a_75x: avoid sys_clk_freq of 125MHz with etherbone (no longer required). <Florent Kermarrec> * bfbee48 - Readme/boards: fill most of the missing infos. <Florent Kermarrec> * bb65692 - add LICENSE. <Florent Kermarrec> * e9706d4 - README: add initial contents and list of supported boards. <Florent Kermarrec> * 760b8ff - arty: improve xy_pmod_io genericity (allow selecting the PMOD) and enable SDCard. <Florent Kermarrec> * 04fc98f - de0nano/ulx3s: add sdram HalfRate support (untested). <Florent Kermarrec> * d0ca1be - targets/de10nano/minispartan6: simplify HalfRate support, rename argument to sdram_rate. <Florent Kermarrec> * 9730c6f - platforms/de10nano: use additional sdram constraints required for HalfRate. <Florent Kermarrec> * 7399d13 - paltforms/de10nano/sdram: enable fast input/output on dq. <Florent Kermarrec> * b4b1ab8 - paltforms/de10nano: simplify IO constraints (for consistency with others platforms). <Florent Kermarrec> * 89c5bf4 - Merge pull request timvideos#92 from rob-ng15/master <enjoy-digital> |\ | * 7cda143 - Allow use of HalfRateGENSDRPHY <rob-ng15> | * cf98393 - Add Misc <rob-ng15> * | 1e1589a - zybo_z7: demonstrate use of PS7 (with --cpu-type=zynq7000). <Florent Kermarrec> * | 8a3b453 - add Zybo Z7 minimal platform/targets: no PS7 support and USB-UART PMOD on JB. <Florent Kermarrec> |/ * e723bef - platforms/arty: add usb_uart_pmod_io (USB-UART PMOD on JA) to ease debug with a second UART (for UARTbone/LiteScope). <Florent Kermarrec> * 19d0b95 - platforms/targets: keep in sync with litex. <Florent Kermarrec> * 0ee4b21 - trellisboard/ulx3s: fix sdcard slewrate. <Florent Kermarrec> * 7efa1c3 - platforms/arty: add missing pullups on sdcard. <Florent Kermarrec> * litex-devicetree changed from 4216376 to 81d837b Full submodule status -- 2942d0652a89646c5225bee15dd55cc3b0871766 VexRiscv (1.0.1-417-g2942d06) 3a6108a75be356a3dc53760d22782f1323248b6b edid-decode (heads/master) 3a06aa84b62ad24467fb0d2c6ceddf565e9ea447 flash_proxies (heads/master) 47a0d5fb9e552baa880afab57903a5966d1ee8a7 litedram (2020.04-88-g47a0d5f) 792013a1756ea50608726ee86989ec38cfc35a8b liteeth (2020.04-21-g792013a) 6fdd02058fba29008c90b162e0ef707dce15ebeb liteiclink (2020.04) 0b6a4bb6e742fd4de38d7ca3674f91acc5985b35 litepcie (2020.04-56-g0b6a4bb) b36d3a33fbbfcffdb77a7a9e05bc8121387858d3 litesata (2020.04-1-gb36d3a3) a80c9640757b61533f300f29628aec3b7316aca8 litescope (2020.04-4-ga80c964) 7457a29b1a47fe15e81fa37f3bbdd510788f1d53 liteusb (heads/master) 41f30143075ece3fff5c33a332ed067d1837cbb3 litevideo (2020.04) abc49964ea6719866684b474e10167950b85854e litex (2020.04-574-gabc49964) ee28d7b5ec1e0bcbeacc342c82cf539a135fbeb3 litex-boards (2020.04-162-gee28d7b) 81d837bc6897d083a6e1166269c186cd196e5cc7 litex-devicetree (heads/master) f1792587a9b50732578e0166cb5d1d83b126cfa6 litex-renode (remotes/origin/HEAD) 7bc4eb1387b39159a74c1dbd1b820728e0bfbbaa migen (0.6.dev-354-g7bc4eb1) 8f5a253b22cd4ebcd56304a3662f4c70e3b34ed5 nmigen (v0.1-69-g8f5a253) 48333804e40c7c9c1c8d5b2e70ba75f4b646d8f0 pythondata-cpu-lm32 (2020.04-5-g4833380) 4731142284cf87e89b21fb35ceff1139f2f89227 pythondata-cpu-minerva (heads/master) af561171f5fc8c684537897f12ef0f429e38624b pythondata-cpu-mor1kx (2020.04-5-gaf56117) 88974894c800ee2e827db47865e0611a07ff40d7 pythondata-cpu-picorv32 (2020.04-5-g8897489) 654057b2f5cec0f9fc99487dff67861f76fcbe7e pythondata-cpu-vexriscv (2020.04-7-g654057b) 7cfcaed2e726027fd622650b58dd77e47c495ee0 pythondata-software-compiler_rt (2020.04-5-g7cfcaed2)

* litedram changed from f51052f to 47a0d5f * 47a0d5f - litedram_gen/LiteDRAMUSDDRPHYCRG: remove AsyncResetSynchronizer on sys/sys4x (reset handled by USIDELAYCTRL). <Florent Kermarrec> * 02e67ec - Merge pull request timvideos#192 from antmicro/jboc/port-adaptation <enjoy-digital> |\ | * 22bd01c - frontend/wishbone: simplify by reusing LiteDRAMNativePortConverter <Jędrzej Boczar> | * b0bde29 - frontend/wishbone: fix wb2native missing wdata.ready when wb/port data widths differ <Jędrzej Boczar> | * 79314f9 - frontend/wishbone: fix wdata.valid being high with old data, use cmd.last=1 <Jędrzej Boczar> | * 000a352 - frontend/adaptation: delay sending write commands to prevent data loss during up-conversion <Jędrzej Boczar> | * 84fb7d3 - frontend/adaptation: refactor up-converter logic to use FSM for clarity <Jędrzej Boczar> | * efe9a44 - frontend/adaptation: clean up LiteDRAMNativePortUpConverter code <Jędrzej Boczar> | * 2f35e97 - frontend/adaptation: fix error when read follows write to the same address <Jędrzej Boczar> | * 1587ee3 - frontend/adaptation: use port.cmd.last instead of port.flush in up-converter <Jędrzej Boczar> | * 35fa91c - test/crossbar: up-conversion with mode="both" should be working now <Jędrzej Boczar> | * 9b90a56 - frontend/adaptation: combine read/write port up-converters and extend tests <Jędrzej Boczar> | * 762cd6d - test/adaptation: add port converter tests with mode="both" <Jędrzej Boczar> | * 7a0f7a7 - test/common: fix error in test data <Jędrzej Boczar> | * 1cc9656 - test/crossbar: improve NativePortDriver to use separate generatos on data paths <Jędrzej Boczar> | * 025e280 - test/crossbar: fix test that was not being run <Jędrzej Boczar> * 71b991e - Merge pull request timvideos#210 from oskirby/ddr3-tdqs-mode <enjoy-digital> |\ | * 805a374 - Add support for TDQS mode. <Owen Kirby> |/ * c01e868 - phy/gensdrphy/HalfRateGENSDRPHY: review/simplify and reduce read_latency by 1. <Florent Kermarrec> * litepcie changed from 0b6a4bb to 30456fc * 30456fc - litepcie_gen: add csr_ordering support. <Florent Kermarrec> * litescope changed from 15179cb to a80c964 * a80c964 - Merge pull request timvideos#22 from antmicro/jboc/test-script <enjoy-digital> * 8b0274d - examples: add a more general script for testing <Jędrzej Boczar> * litex changed from 9fc488bd to 00629c45 * 00629c45 - interconnect/csr: add CSR registers ordering support. <Florent Kermarrec> * ee7a7f46 - soc/interconnect/csr: improve ident. <Florent Kermarrec> * b1008b01 - integration/soc: add expection on decoder when full address space is mapped. <Florent Kermarrec> * b831dc8c - wishbone: revert default adr_width to 30. <Florent Kermarrec> * abc49964 - tools/litex_json2dts: add missing copyrights. <Florent Kermarrec> * aed0dcee - setup: add litex_json2dts to console_scripts. <Florent Kermarrec> * b64209b3 - Merge pull request timvideos#620 from antmicro/add_litex_json2dts <enjoy-digital> |\ | * fafa844a - json2dts: Add Linux DT generation script <Mateusz Holenko> * | 0ca99b79 - build/sim/config: add default_clk/default_clk_freq parameters for retro-compatibility with previous API. <Florent Kermarrec> * | 696ea468 - build/sim: use json_object_get_int64 instead of json_object_get_uint64. <Florent Kermarrec> * | 382c1a3a - Merge pull request timvideos#619 from antmicro/jboc/sim-clocker <enjoy-digital> |\ \ | |/ |/| | * f778ff09 - build/sim: improve timebase calculation (strict checks) and update modules <Jędrzej Boczar> | * c1ae7e59 - build/sim: allow for arbitrary clocks generation using clockers <Jędrzej Boczar> | * 38054874 - build/sim: use a real timebase in the simulation <Jędrzej Boczar> * | e0f131a3 - cores/uart: add txempty/rxfull CSRs. <Florent Kermarrec> * | 2a3e39b1 - tools/litex_server: enable read_merger with CommUDP. <Florent Kermarrec> * | a5d0a340 - test: specify wishbone adr_width on AXI(Lite)<-->Wishbone tests and remove debug traces. <Florent Kermarrec> * | eb3374d0 - Merge pull request timvideos#617 from gsomlo/gls_rocket_dma <enjoy-digital> |\ \ | * | 561331ed - debug: make CI print offending values <Gabriel Somlo> | * | df3428be - liblitesdcard/sdcard: (temporarily) slow down SDCARD_CLK_FREQ to 25MHz <Gabriel Somlo> | * | 2d9dc8f9 - cores/cpu/rocket: expose slave port for DMA <Gabriel Somlo> | * | d8161e5a - integration/soc: make DMA slave region cover (at least) the lower 4GB <Gabriel Somlo> | * | 70eae5cb - interconnect/wishbone: increase WB address width to 31 <Gabriel Somlo> | * | b8c9da81 - soc/interconnect/axi: add Wishbone2AXI converter <Gabriel Somlo> |/ / * | 2ec4604c - cores/gpio: add support for Record on GPIOOut, GPIOIn and GPIOInOut. <Florent Kermarrec> * | 5e53e5d7 - Merge pull request timvideos#615 from pepijndevos/openfpgaloader <enjoy-digital> |\ \ | * | 79ca4d96 - remove debugging <Pepijn de Vos> | * | f6e20700 - add openFPGAloader programmer <Pepijn de Vos> * | | eab0726c - cpu/vexriscv/core: use variant name as human_name. <Florent Kermarrec> * | | e0a763e5 - cpu/vexriscv/system.h: provide empty flush_cpu_i/dcache functions for variants with no i/d cache. <Florent Kermarrec> * | | 3ff1bcaf - cpu/zynq7000: set csr map to 0x00000000. <Florent Kermarrec> * | | c0253e3f - Merge pull request timvideos#611 from antmicro/jboc/axi-lite <enjoy-digital> |\ \ \ | | |/ | |/| | * | e78d950a - soc/interconnect/axi: add AXILite -> AXI converter <Jędrzej Boczar> * | | cc844054 - tools/litex_server/read_merger: review/simplify a bit. <Florent Kermarrec> * | | 4f382ccf - Merge pull request timvideos#605 from cklarhorst/feature-uart-read-merger <enjoy-digital> |\ \ \ | * | | 2034c563 - Merge sequential reads for the UART litex_server backend <Christian Klarhorst> * | | | a942e358 - cpu/blackparrot: minor cleanups, add sim variant (since use different flist). <Florent Kermarrec> * | | | 86e910df - Merge pull request timvideos#610 from Dolu1990/vexriscv_smp <enjoy-digital> |\ \ \ \ | * | | | 023ab15e - soc/cores/cpu/vexriscv_smp enable dynamic litedram datawidth <Dolu1990> | * | | | e5cd5d54 - Merge branch 'master' into vexriscv_smp <Dolu1990> | |\ \ \ \ | |/ / / / |/| | | | * | | | | 1938ce36 - integration/soc/add_sdram: allow the CPU to add the direct memory buses when adding the sdram. <Florent Kermarrec> * | | | | 6576416b - cores/cpu/rocket: add use_memory_bus parameter to easily disable direct memory bus for testing. <Florent Kermarrec> | * | | | 789a70e7 - Merge branch 'master' into vexriscv_smp <Dolu1990> | |\ \ \ \ | |/ / / / |/| | | | * | | | | 0696b409 - CHANGES: update. <Florent Kermarrec> * | | | | fe38e12b - cpu/vexriscv_smp: move litedram import, remove os.path import. <Florent Kermarrec> * | | | | 59b95fad - litex_setup: fix vexriscv-smp repository. <Florent Kermarrec> * | | | | 9d052f38 - Merge pull request timvideos#607 from Dolu1990/vexriscv_smp <enjoy-digital> |\ \ \ \ \ | | * | | | d284dfbe - soc/cores/cpu/vexriscv_smp config update <Dolu1990> | |/ / / / | * / / / aa57c7a2 - soc/cores/cpu/vexriscv_smp integration <Dolu1990> |/ / / / * | | | f87513ab - liblitesdcard/sdcard: increase SDCARD_CLK_FREQ to 50MHz. <Florent Kermarrec> * | | | 9518ccf4 - integration/soc/etherbone: expose ethcore (useful to combine udp/etherbone). <Florent Kermarrec> | |_|/ |/| | * | | 9e07623b - integration/soc: fix dma_bus typo. <Florent Kermarrec> |/ / * / 1fdffdfd - targets: keep in sync with litex-boards. <Florent Kermarrec> |/ * 8a0684b1 - Merge pull request timvideos#604 from antmicro/jboc/axi-lite <enjoy-digital> |\ | * 879e6ffe - soc/interconnect/axi: add basic AXI Lite up-converter <Jędrzej Boczar> | * 32160e61 - soc/interconnect/axi: separate AXI Lite converter channels <Jędrzej Boczar> * | ed721198 - Merge pull request timvideos#603 from enjoy-digital/socdoc-extensions <Sean Cross> |\ \ | * | 29b2baf9 - doc: socdoc: document new `sphinx_extra_config` parameter <Sean Cross> | * | dd366467 - litex: add `sphinx_extra_config` to `generate_docs()` <Sean Cross> * | | 3d16838d - Merge pull request timvideos#602 from enjoy-digital/socdoc-extensions <enjoy-digital> |\| | | * | 7fecfbf8 - doc: socdoc: document `sphinx_extensions` parameter <Sean Cross> |/ / * | 83370399 - CHANGES: update. <Florent Kermarrec> * | 041c7527 - core/cpu: integrate Zynq as a classical CPU (Zynq7000), deprecate SoCZynq. <Florent Kermarrec> |/ * 8bdf6941 - liblitesdcard/sdcard: use max divider of 256 (128 was not enough for the initial 400Khz clock frequency). <Florent Kermarrec> * 8f92034d - CHANGES: update. <Florent Kermarrec> * 99e88dfc - Merge pull request timvideos#600 from antmicro/jboc/axi-lite <enjoy-digital> |\ | * a9d8b813 - test/axi: move all AXI Lite tests to separate file <Jędrzej Boczar> | * 367eb122 - soc/integration: use AXILiteSRAM when using bus_standard="axi-lite" <Jędrzej Boczar> | * 8ae501c3 - test/axi: add crossbar stress tests <Jędrzej Boczar> | * 706bc25d - soc/integration: add bus standard parser arguments <Jędrzej Boczar> | * 32d9e212 - soc/interconnect/axi: improve Timeout module and test it with shared interconnect <Jędrzej Boczar> | * 2cab7fbf - test/axi: add shared AXI Lite interconnect tests <Jędrzej Boczar> | * 3a08b21d - soc/interconnect/axi: implement AXI Lite decoder <Jędrzej Boczar> | * 214cfdca - soc/interconnect/axi: lock AXILiteArbiter until all requests have been responded to <Jędrzej Boczar> | * baf23c9c - test/test_axi: add AXI Lite interconnect arbiter tests <Jędrzej Boczar> | * a8a583d6 - socinterconnect/axi: interconnect shared sketch <Jędrzej Boczar> | * f47ccdae - soc/interconnect/axi: point-to-point interconnect and timeout module with tests <Jędrzej Boczar> | * b4c1120e - soc/integration: choose interconnect based on bus standard <Jędrzej Boczar> | * 69d8dd78 - soc/integration: add axi-lite standard to SoCBusHandler <Jędrzej Boczar> * | d38048ba - soc: add initial DMA bus support (optionally provided by CPU(s) for cache coherency). <Florent Kermarrec> |/ * 2361abb1 - Merge pull request timvideos#599 from antmicro/gen-mmcm-pr <enjoy-digital> |\ | * 66c5f371 - litex-gen: add mmcm core <Piotr Binkowski> * 6b72f52c - boards: keep in sync with litex-boards. <Florent Kermarrec> * 1f27b740 - soc/integration/add_sdcard: add direct connection to VexRiscv's dmabus for testing. <Florent Kermarrec> * 408d1a9f - cpu/vexriscv/system.h: update flush_cpu_dcache. <Florent Kermarrec> * 47ce15b4 - interconnect/wishbone: add minimal UpConverter. <Florent Kermarrec> * litex-boards changed from 2ce24df to ee28d7b * ee28d7b - targets/ulx3s/add_oled: simplify. <Florent Kermarrec> * 623faa9 - Merge pull request timvideos#96 from pepijndevos/oled <enjoy-digital> |\ | * eba7037 - add optional OLED peripheral to ULX3S target <Pepijn de Vos> |/ * 929e55d - platforms/trellisboard: add SDCard PMOD pins. <Florent Kermarrec> * 5fd3e8d - ecpix5: add SDCard. <Florent Kermarrec> * f058181 - README: fix typo. <Florent Kermarrec> * 94ccf1d - targets/trellisboard: simplify clocking when no DDR3, remove firmware_ram (was here for debug). <Florent Kermarrec> * ecdc1ef - README: add missings . <Florent Kermarrec> * 361afa7 - README: add links to LiteX's wiki. <Florent Kermarrec> * 02c0c0a - README: add board picture and fix a few typos. <Florent Kermarrec> * eb8a484 - targets/de10nano: fix typo. <Florent Kermarrec> * 2cef54a - targets/colorlight_5a_75x: avoid sys_clk_freq of 125MHz with etherbone (no longer required). <Florent Kermarrec> * bfbee48 - Readme/boards: fill most of the missing infos. <Florent Kermarrec> * bb65692 - add LICENSE. <Florent Kermarrec> * e9706d4 - README: add initial contents and list of supported boards. <Florent Kermarrec> * 760b8ff - arty: improve xy_pmod_io genericity (allow selecting the PMOD) and enable SDCard. <Florent Kermarrec> * 04fc98f - de0nano/ulx3s: add sdram HalfRate support (untested). <Florent Kermarrec> * d0ca1be - targets/de10nano/minispartan6: simplify HalfRate support, rename argument to sdram_rate. <Florent Kermarrec> * 9730c6f - platforms/de10nano: use additional sdram constraints required for HalfRate. <Florent Kermarrec> * 7399d13 - paltforms/de10nano/sdram: enable fast input/output on dq. <Florent Kermarrec> * b4b1ab8 - paltforms/de10nano: simplify IO constraints (for consistency with others platforms). <Florent Kermarrec> * 89c5bf4 - Merge pull request timvideos#92 from rob-ng15/master <enjoy-digital> |\ | * 7cda143 - Allow use of HalfRateGENSDRPHY <rob-ng15> | * cf98393 - Add Misc <rob-ng15> * | 1e1589a - zybo_z7: demonstrate use of PS7 (with --cpu-type=zynq7000). <Florent Kermarrec> * | 8a3b453 - add Zybo Z7 minimal platform/targets: no PS7 support and USB-UART PMOD on JB. <Florent Kermarrec> |/ * e723bef - platforms/arty: add usb_uart_pmod_io (USB-UART PMOD on JA) to ease debug with a second UART (for UARTbone/LiteScope). <Florent Kermarrec> * 19d0b95 - platforms/targets: keep in sync with litex. <Florent Kermarrec> * 0ee4b21 - trellisboard/ulx3s: fix sdcard slewrate. <Florent Kermarrec> * 7efa1c3 - platforms/arty: add missing pullups on sdcard. <Florent Kermarrec> Full submodule status -- 2942d0652a89646c5225bee15dd55cc3b0871766 VexRiscv (1.0.1-417-g2942d06) 3a6108a75be356a3dc53760d22782f1323248b6b edid-decode (heads/master) 3a06aa84b62ad24467fb0d2c6ceddf565e9ea447 flash_proxies (heads/master) 47a0d5fb9e552baa880afab57903a5966d1ee8a7 litedram (2020.04-88-g47a0d5f) 792013a1756ea50608726ee86989ec38cfc35a8b liteeth (2020.04-21-g792013a) 6fdd02058fba29008c90b162e0ef707dce15ebeb liteiclink (2020.04) 30456fcb0697ef6c9252b9f2c0b2edf0c45ea353 litepcie (2020.04-57-g30456fc) b36d3a33fbbfcffdb77a7a9e05bc8121387858d3 litesata (2020.04-1-gb36d3a3) a80c9640757b61533f300f29628aec3b7316aca8 litescope (2020.04-4-ga80c964) 7457a29b1a47fe15e81fa37f3bbdd510788f1d53 liteusb (heads/master) 41f30143075ece3fff5c33a332ed067d1837cbb3 litevideo (2020.04) 00629c45b0ecb44149893439d040d4b4267ba4ea litex (2020.04-578-g00629c45) ee28d7b5ec1e0bcbeacc342c82cf539a135fbeb3 litex-boards (2020.04-162-gee28d7b) f1792587a9b50732578e0166cb5d1d83b126cfa6 litex-renode (remotes/origin/HEAD) 7bc4eb1387b39159a74c1dbd1b820728e0bfbbaa migen (0.6.dev-354-g7bc4eb1) 8f5a253b22cd4ebcd56304a3662f4c70e3b34ed5 nmigen (v0.1-69-g8f5a253) 48333804e40c7c9c1c8d5b2e70ba75f4b646d8f0 pythondata-cpu-lm32 (2020.04-5-g4833380) 4731142284cf87e89b21fb35ceff1139f2f89227 pythondata-cpu-minerva (heads/master) af561171f5fc8c684537897f12ef0f429e38624b pythondata-cpu-mor1kx (2020.04-5-gaf56117) 88974894c800ee2e827db47865e0611a07ff40d7 pythondata-cpu-picorv32 (2020.04-5-g8897489) 654057b2f5cec0f9fc99487dff67861f76fcbe7e pythondata-cpu-vexriscv (2020.04-7-g654057b) 7cfcaed2e726027fd622650b58dd77e47c495ee0 pythondata-software-compiler_rt (2020.04-5-g7cfcaed2)

@mtdudek

* litedram changed from f51052f to 2020.08-3-g5c69da5 * 5c69da5 - bench: add initial kcu105 bench target. <Florent Kermarrec> * 9995c0f - bench: switch integrated_rom to "rw" mode and reload it over Etherbone at startup. <Florent Kermarrec> * ac825e5 - add SPDX License identifier to header and specify file is part of LiteDRAM. <Florent Kermarrec> * 198bcba - test/reference: update. <Florent Kermarrec> * e3b86fe - getting started: update. <Florent Kermarrec> * a0a886e - litedram/init: export xdr ratio and databits. <Florent Kermarrec> * 94241d0 - bench: use new platform.request_all on LedChaser. <Florent Kermarrec> * 7420597 - bench: add genesys2 bench. <Florent Kermarrec> * 37fb44f - add bench directory with a first bench on arty board. <Florent Kermarrec> * 4e62d28 - examples/.yml: set cmd_latency to 1 on Kintex7/Ultrascale (values valided in LiteX-Boards). <Florent Kermarrec> * 07bf34d - frontend/wishbone: revert non-FSM version, the FSM one does not seem to cover all cases. <Florent Kermarrec> * 9c5ce52 - common: add connect method to LiteDRAMNativePort and use it in adapter for identify converter. <Florent Kermarrec> * 06f7192 - frontend/adapter/LiteDRAMNativePortConverter: simplify using ratio. <Florent Kermarrec> * a3dfc1d - frontend/adapter: minor cleanups. <Florent Kermarrec> * deac4c8 - frontend/adapter: simplify LiteDRAMNativePortDownConverter. <Florent Kermarrec> * ce4e7f9 - frontend/adapter: simplify LiteDRAMNativePortCDC using stream.ClockDomainCrossing. <Florent Kermarrec> * 16fd46b - frontend: rename adaptation to adapter. <Florent Kermarrec> * 4970c8a - frontend/wishbone: simplify/review and get FSM back (ease comprehension). <Florent Kermarrec> * 47a0d5f - litedram_gen/LiteDRAMUSDDRPHYCRG: remove AsyncResetSynchronizer on sys/sys4x (reset handled by USIDELAYCTRL). <Florent Kermarrec> * 02e67ec - Merge pull request timvideos#192 from antmicro/jboc/port-adaptation <enjoy-digital> |\ | * 22bd01c - frontend/wishbone: simplify by reusing LiteDRAMNativePortConverter <Jędrzej Boczar> | * b0bde29 - frontend/wishbone: fix wb2native missing wdata.ready when wb/port data widths differ <Jędrzej Boczar> | * 79314f9 - frontend/wishbone: fix wdata.valid being high with old data, use cmd.last=1 <Jędrzej Boczar> | * 000a352 - frontend/adaptation: delay sending write commands to prevent data loss during up-conversion <Jędrzej Boczar> | * 84fb7d3 - frontend/adaptation: refactor up-converter logic to use FSM for clarity <Jędrzej Boczar> | * efe9a44 - frontend/adaptation: clean up LiteDRAMNativePortUpConverter code <Jędrzej Boczar> | * 2f35e97 - frontend/adaptation: fix error when read follows write to the same address <Jędrzej Boczar> | * 1587ee3 - frontend/adaptation: use port.cmd.last instead of port.flush in up-converter <Jędrzej Boczar> | * 35fa91c - test/crossbar: up-conversion with mode="both" should be working now <Jędrzej Boczar> | * 9b90a56 - frontend/adaptation: combine read/write port up-converters and extend tests <Jędrzej Boczar> | * 762cd6d - test/adaptation: add port converter tests with mode="both" <Jędrzej Boczar> | * 7a0f7a7 - test/common: fix error in test data <Jędrzej Boczar> | * 1cc9656 - test/crossbar: improve NativePortDriver to use separate generatos on data paths <Jędrzej Boczar> | * 025e280 - test/crossbar: fix test that was not being run <Jędrzej Boczar> * 71b991e - Merge pull request timvideos#210 from oskirby/ddr3-tdqs-mode <enjoy-digital> |\ | * 805a374 - Add support for TDQS mode. <Owen Kirby> |/ * c01e868 - phy/gensdrphy/HalfRateGENSDRPHY: review/simplify and reduce read_latency by 1. <Florent Kermarrec> * liteeth changed from 792013a to 54acf9f * 54acf9f - phy/pcs_1000basex: keep up to date with MiSoC (adds SGMII and 10/100Mbps support). <Florent Kermarrec> * 64b85e6 - add SPDX License identifier to header and specify file is part or LiteEth. <Florent Kermarrec> * f275af8 - liteeth_gen: get Wishbone Platform's IOs with Interface.get_ios. <Florent Kermarrec> * 0705b35 - Merge pull request timvideos#46 from Xiretza/gen-py-wishbone <enjoy-digital> * 6a9a513 - Update gen.py to work with latest LiteX in wishbone mode <Xiretza> * liteiclink changed from 6fdd020 to 2020.08-1-gefd200f * efd200f - add SPDX License identifier to header and specify file is part of LiteICLink. <Florent Kermarrec> * 60b1994 - getting started: update. <Florent Kermarrec> * litepcie changed from 0b6a4bb to 2020.08-1-g0718fd1 * 0718fd1 - add SPDX License identifier to header and specify file is part of LitePCIe. <Florent Kermarrec> * 29d4963 - getting started: update. <Florent Kermarrec> * 30456fc - litepcie_gen: add csr_ordering support. <Florent Kermarrec> * litesata changed from b36d3a3 to 2020.08-1-gba006a7 * ba006a7 - add SPDX License identifier to header and specify file is part of LiteSATA. <Florent Kermarrec> * 2e4591c - getting started: update. <Florent Kermarrec> * litescope changed from 15179cb to 2020.08-2-g02b543e * 02b543e - litescope_cli: add capture subsampling support. <Florent Kermarrec> * 2739d5a - add SPDX License identifier to header and specify file is part of LiteScope. <Florent Kermarrec> * ec7bd6b - getting started: update. <Florent Kermarrec> * 7d22774 - Merge pull request timvideos#27 from cklarhorst/fix-storage-wrong-clock-domain <enjoy-digital> |\ | * ad4e46c - Fix: 2 signals in the storage class belong to the wrong clock domain <Christian Klarhorst> |/ * 2ad73a0 - Merge pull request timvideos#25 from cklarhorst/fix-trigger-flush-timer-wrong-clock-domain <enjoy-digital> |\ | * 16e6555 - Fix: A WaitTimer belongs to the wrong clock domain (trigger flush) <Christian Klarhorst> |/ * 0066866 - travis: install riscv toolchain for example. <Florent Kermarrec> * 6a322ed - test/test_examples: update. <Florent Kermarrec> * bc6c5e3 - examples: add mininal example on Arty with Etherbone and ibus/counter on analyzer. <Florent Kermarrec> * 0182377 - examples: remove obsolete examples rename litescope_test to litescope_cli and add it as console script. <Florent Kermarrec> * a80c964 - Merge pull request timvideos#22 from antmicro/jboc/test-script <enjoy-digital> * 8b0274d - examples: add a more general script for testing <Jędrzej Boczar> * litex changed from 9fc488bd to 3897acb9 * 3897acb9 - lattice/nx: update copyrights. <Florent Kermarrec> * 4364043b - integration/soc: expose integrated_rom_mode to allow ROM to be writable (useful for BIOS/ROM development where content is reloaded over UARTBone/Etherbone). <Florent Kermarrec> * 885c339d - soc/cores: add initial NX-LRAM support. <Piense> * cf13833e - cores/clock: add initial NX-OSCA support. <Piense> * e441bd60 - build/lattice: add initial Radiant support for NX FPGA family (Crosslink-NX/Certus-NX). <Piense> * 8a44464a - Merge pull request timvideos#640 from antmicro/mor1kx_dt <enjoy-digital> |\ | * 4dab1eb0 - litex_json2dts: Add support for mor1kx <Mateusz Holenko> * | 4f1c32ab - targets/de0nano: set sys2x_ps to 180° for sdram_rate=1:2. <Florent Kermarrec> * | d16051ff - boards/ulx3s: keep up to date with litex-boards. <Florent Kermarrec> * | d826c606 - soc/cores/clock/ECP5PLL: specificy CLKOS3_F/CPHASE and -1 on cphase to match Clarity Designer values. <Florent Kermarrec> * | 9e37b16e - soc/interconnect/axi/AXILite2CSR: add register parameter for genericity. <Florent Kermarrec> |/ * 42d8fc22 - Merge branch 'master' of https://github.com/enjoy-digital/litex <Florent Kermarrec> |\ | * ee0e2402 - Merge pull request timvideos#631 from gsomlo/gls-abc9-fixup <enjoy-digital> | |\ | | * c4710b37 - build/lattice/trellis: make "-abc9" an optional argument <Gabriel Somlo> * | | 77ae2433 - test: add SPDX License identifier to header and specify file is part of LiteX. <Florent Kermarrec> * | | b8371ef4 - tools: add SPDX License identifier to header and specify file is part of LiteX. <Florent Kermarrec> * | | 93d906f9 - soc: add SPDX License identifier and specify file is part of LiteX. <Florent Kermarrec> * | | e52ffd2d - gen: add specify SPDX License identifier and specify file is part of Migen and has been modified/adapted for LiteX. <Florent Kermarrec> * | | 70610b23 - build: add SPDX License identifier and specify file is part of LiteX. <Florent Kermarrec> * | | 6ee882d1 - platforms/targets: add SPDX License identifier to header and specify file is part of LiteX. <Florent Kermarrec> |/ / * | 9950e756 - build/io: fix InferedSDRIO (thanks @mtdudek). <Florent Kermarrec> * | bae871a8 - Merge pull request timvideos#632 from gsomlo/gls-sdcard-refactor <enjoy-digital> |\ \ | * | e0b2b815 - liblitesdcard/sdcard: read sdcard response only when needed <Gabriel Somlo> | * | a47b2de5 - sdcard: refactor command functions <Gabriel Somlo> | * | bfd6b3c3 - liblitesdcard/sdcard: cosmetic fixes (indentation, #ifdef, etc.) <Gabriel Somlo> | * | 37ebcd3b - factor out busy_wait_us() <Gabriel Somlo> | |/ * | 3206dba9 - Merge pull request timvideos#636 from Xiretza/minerva-cli-filetype <enjoy-digital> |\ \ | * | e3bb3a94 - Fix call to generation of minerva output file <Xiretza> | |/ * | 8bc5dd7c - Merge pull request timvideos#635 from Xiretza/collections-abc-deprecation <enjoy-digital> |\ \ | * | fcc7058b - Fix DeprecationWarning for collections.abc <Xiretza> | |/ * | 79844362 - Merge pull request timvideos#634 from betrusted-io/spi_opi_timing_only <enjoy-digital> |\ \ | |/ |/| | * d783e86f - add a pipe register to relax an async_default timing path <bunnie> * | 35929c0f - soc/integration/csr_bridge: use registered version only when SDRAM is present. <Florent Kermarrec> * | e4f5dd98 - interconnect/wishbone/Wishbone2CSR: add registered version and use it as default. <Florent Kermarrec> * | b344196a - build/lattice/diamond: use diamondc instead of pnmainc (avoid having to set environment variables). <Florent Kermarrec> * | f730f1d7 - cores/cpu/vexriscv_smp fix argument parsing <Dolu1990> * | 0e480dd6 - bios/main/sdram: fix speed reporting (Mbps/pin not MHz). <Florent Kermarrec> * | bb7f3343 - Merge pull request timvideos#627 from gsomlo/gls-dma-addr-64 <enjoy-digital> |\ \ | * | ba34c852 - cores/dma, liblitesdcard/sdcard: use 64 bits for dma base address <Gabriel Somlo> |/ / * | 4cf28a01 - software/bios: display SDRAM databits and freq. <Florent Kermarrec> * | 6f69679d - cpu/vexriscv_smp: more coherent_dma to __init__ instead of add_memory_buses. <Florent Kermarrec> * | b3531cd2 - cores/cpu: add external cpu_type. <Florent Kermarrec> * | b9d3aab5 - targets: use platform.request_all on LedChaser. <Florent Kermarrec> * | 14c91664 - build/generic_platform: add request_all method. <Florent Kermarrec> * | 57335b99 - cores/cpu/zynq7000: simplify using new loose parameter of Platform.request. <Florent Kermarrec> * | 4867f2b3 - Merge pull request timvideos#624 from trabucayre/emio_zynq <enjoy-digital> |\ \ | * | 87c26a30 - soc/cores/cpu/zynq7000: add enet0, enet0_mdio, sdio, sdio_cd and sdio_wp only when configured in EMIO mode <Gwenhael Goavec-Merou> * | | 48d63f23 - build/generic_plaform: add loose parameter to return None when not available/existing. <Florent Kermarrec> * | | 81df7b70 - Merge pull request timvideos#625 from scanakci/blackparrot_litex <enjoy-digital> |\ \ \ | * | | 2457859b - update BlackParrot transducer <sadullah> | * | | d2dabcef - Blackparrot human name update <sadullah> | |/ / * / / 188e6f57 - integration/soc/add_etherbone: pass phy to ethcore not self.ethphy. <Florent Kermarrec> |/ / * | d5062d1f - Merge pull request timvideos#623 from Dolu1990/vexriscv_smp <enjoy-digital> |\ \ | * | 07a8e696 - cpu/vexriscv_smp Add --with-coherent-dma <Dolu1990> |/ / * | 9a4c5aa1 - integration/soc/add_sdram: update rules to connect main bus to dram. <Florent Kermarrec> * | a1644510 - cpu/vexriscv_smp: fix args_read. <Florent Kermarrec> * | 896b68cd - cpu/vexriscv_smp: cleanup, fix coherent_dma connection. <Florent Kermarrec> * | 342f359e - Merge pull request timvideos#622 from antmicro/fix_connectors <enjoy-digital> |\ \ | * | de9ea19c - arty: Change USB-uart and I2S Pmod configuration <Pawel Sagan> * | | 3b293612 - soc/interconnect/axi: minor cleanups. <Florent Kermarrec> * | | 303d6cca - interconnect/stream: set default AsyncFIFO depth to None and add depth parameter to ClockDomainCrossing. <Florent Kermarrec> * | | 00629c45 - interconnect/csr: add CSR registers ordering support. <Florent Kermarrec> * | | ee7a7f46 - soc/interconnect/csr: improve ident. <Florent Kermarrec> * | | b1008b01 - integration/soc: add expection on decoder when full address space is mapped. <Florent Kermarrec> * | | b831dc8c - wishbone: revert default adr_width to 30. <Florent Kermarrec> | |/ |/| * | abc49964 - tools/litex_json2dts: add missing copyrights. <Florent Kermarrec> * | aed0dcee - setup: add litex_json2dts to console_scripts. <Florent Kermarrec> * | b64209b3 - Merge pull request timvideos#620 from antmicro/add_litex_json2dts <enjoy-digital> |\ \ | * | fafa844a - json2dts: Add Linux DT generation script <Mateusz Holenko> * | | 0ca99b79 - build/sim/config: add default_clk/default_clk_freq parameters for retro-compatibility with previous API. <Florent Kermarrec> * | | 696ea468 - build/sim: use json_object_get_int64 instead of json_object_get_uint64. <Florent Kermarrec> * | | 382c1a3a - Merge pull request timvideos#619 from antmicro/jboc/sim-clocker <enjoy-digital> |\ \ \ | |/ / |/| | | * | f778ff09 - build/sim: improve timebase calculation (strict checks) and update modules <Jędrzej Boczar> | * | c1ae7e59 - build/sim: allow for arbitrary clocks generation using clockers <Jędrzej Boczar> | * | 38054874 - build/sim: use a real timebase in the simulation <Jędrzej Boczar> * | | e0f131a3 - cores/uart: add txempty/rxfull CSRs. <Florent Kermarrec> * | | 2a3e39b1 - tools/litex_server: enable read_merger with CommUDP. <Florent Kermarrec> * | | a5d0a340 - test: specify wishbone adr_width on AXI(Lite)<-->Wishbone tests and remove debug traces. <Florent Kermarrec> * | | eb3374d0 - Merge pull request timvideos#617 from gsomlo/gls_rocket_dma <enjoy-digital> |\ \ \ | * | | 561331ed - debug: make CI print offending values <Gabriel Somlo> | * | | df3428be - liblitesdcard/sdcard: (temporarily) slow down SDCARD_CLK_FREQ to 25MHz <Gabriel Somlo> | * | | 2d9dc8f9 - cores/cpu/rocket: expose slave port for DMA <Gabriel Somlo> | * | | d8161e5a - integration/soc: make DMA slave region cover (at least) the lower 4GB <Gabriel Somlo> | * | | 70eae5cb - interconnect/wishbone: increase WB address width to 31 <Gabriel Somlo> | * | | b8c9da81 - soc/interconnect/axi: add Wishbone2AXI converter <Gabriel Somlo> |/ / / * | | 2ec4604c - cores/gpio: add support for Record on GPIOOut, GPIOIn and GPIOInOut. <Florent Kermarrec> * | | 5e53e5d7 - Merge pull request timvideos#615 from pepijndevos/openfpgaloader <enjoy-digital> |\ \ \ | * | | 79ca4d96 - remove debugging <Pepijn de Vos> | * | | f6e20700 - add openFPGAloader programmer <Pepijn de Vos> * | | | eab0726c - cpu/vexriscv/core: use variant name as human_name. <Florent Kermarrec> * | | | e0a763e5 - cpu/vexriscv/system.h: provide empty flush_cpu_i/dcache functions for variants with no i/d cache. <Florent Kermarrec> * | | | 3ff1bcaf - cpu/zynq7000: set csr map to 0x00000000. <Florent Kermarrec> * | | | c0253e3f - Merge pull request timvideos#611 from antmicro/jboc/axi-lite <enjoy-digital> |\ \ \ \ | | |/ / | |/| | | * | | e78d950a - soc/interconnect/axi: add AXILite -> AXI converter <Jędrzej Boczar> * | | | cc844054 - tools/litex_server/read_merger: review/simplify a bit. <Florent Kermarrec> * | | | 4f382ccf - Merge pull request timvideos#605 from cklarhorst/feature-uart-read-merger <enjoy-digital> |\ \ \ \ | * | | | 2034c563 - Merge sequential reads for the UART litex_server backend <Christian Klarhorst> * | | | | a942e358 - cpu/blackparrot: minor cleanups, add sim variant (since use different flist). <Florent Kermarrec> | |_|_|/ |/| | | * | | | 86e910df - Merge pull request timvideos#610 from Dolu1990/vexriscv_smp <enjoy-digital> |\ \ \ \ | * | | | 023ab15e - soc/cores/cpu/vexriscv_smp enable dynamic litedram datawidth <Dolu1990> | * | | | e5cd5d54 - Merge branch 'master' into vexriscv_smp <Dolu1990> | |\ \ \ \ | |/ / / / |/| | | | * | | | | 1938ce36 - integration/soc/add_sdram: allow the CPU to add the direct memory buses when adding the sdram. <Florent Kermarrec> * | | | | 6576416b - cores/cpu/rocket: add use_memory_bus parameter to easily disable direct memory bus for testing. <Florent Kermarrec> | * | | | 789a70e7 - Merge branch 'master' into vexriscv_smp <Dolu1990> | |\ \ \ \ | |/ / / / |/| | | | * | | | | 0696b409 - CHANGES: update. <Florent Kermarrec> * | | | | fe38e12b - cpu/vexriscv_smp: move litedram import, remove os.path import. <Florent Kermarrec> * | | | | 59b95fad - litex_setup: fix vexriscv-smp repository. <Florent Kermarrec> * | | | | 9d052f38 - Merge pull request timvideos#607 from Dolu1990/vexriscv_smp <enjoy-digital> |\ \ \ \ \ | | * | | | d284dfbe - soc/cores/cpu/vexriscv_smp config update <Dolu1990> | |/ / / / | * / / / aa57c7a2 - soc/cores/cpu/vexriscv_smp integration <Dolu1990> |/ / / / * | | | f87513ab - liblitesdcard/sdcard: increase SDCARD_CLK_FREQ to 50MHz. <Florent Kermarrec> * | | | 9518ccf4 - integration/soc/etherbone: expose ethcore (useful to combine udp/etherbone). <Florent Kermarrec> | |_|/ |/| | * | | 9e07623b - integration/soc: fix dma_bus typo. <Florent Kermarrec> |/ / * / 1fdffdfd - targets: keep in sync with litex-boards. <Florent Kermarrec> |/ * 8a0684b1 - Merge pull request timvideos#604 from antmicro/jboc/axi-lite <enjoy-digital> |\ | * 879e6ffe - soc/interconnect/axi: add basic AXI Lite up-converter <Jędrzej Boczar> | * 32160e61 - soc/interconnect/axi: separate AXI Lite converter channels <Jędrzej Boczar> * | ed721198 - Merge pull request timvideos#603 from enjoy-digital/socdoc-extensions <Sean Cross> |\ \ | * | 29b2baf9 - doc: socdoc: document new `sphinx_extra_config` parameter <Sean Cross> | * | dd366467 - litex: add `sphinx_extra_config` to `generate_docs()` <Sean Cross> * | | 3d16838d - Merge pull request timvideos#602 from enjoy-digital/socdoc-extensions <enjoy-digital> |\| | | * | 7fecfbf8 - doc: socdoc: document `sphinx_extensions` parameter <Sean Cross> |/ / * | 83370399 - CHANGES: update. <Florent Kermarrec> * | 041c7527 - core/cpu: integrate Zynq as a classical CPU (Zynq7000), deprecate SoCZynq. <Florent Kermarrec> |/ * 8bdf6941 - liblitesdcard/sdcard: use max divider of 256 (128 was not enough for the initial 400Khz clock frequency). <Florent Kermarrec> * 8f92034d - CHANGES: update. <Florent Kermarrec> * 99e88dfc - Merge pull request timvideos#600 from antmicro/jboc/axi-lite <enjoy-digital> |\ | * a9d8b813 - test/axi: move all AXI Lite tests to separate file <Jędrzej Boczar> | * 367eb122 - soc/integration: use AXILiteSRAM when using bus_standard="axi-lite" <Jędrzej Boczar> | * 8ae501c3 - test/axi: add crossbar stress tests <Jędrzej Boczar> | * 706bc25d - soc/integration: add bus standard parser arguments <Jędrzej Boczar> | * 32d9e212 - soc/interconnect/axi: improve Timeout module and test it with shared interconnect <Jędrzej Boczar> | * 2cab7fbf - test/axi: add shared AXI Lite interconnect tests <Jędrzej Boczar> | * 3a08b21d - soc/interconnect/axi: implement AXI Lite decoder <Jędrzej Boczar> | * 214cfdca - soc/interconnect/axi: lock AXILiteArbiter until all requests have been responded to <Jędrzej Boczar> | * baf23c9c - test/test_axi: add AXI Lite interconnect arbiter tests <Jędrzej Boczar> | * a8a583d6 - socinterconnect/axi: interconnect shared sketch <Jędrzej Boczar> | * f47ccdae - soc/interconnect/axi: point-to-point interconnect and timeout module with tests <Jędrzej Boczar> | * b4c1120e - soc/integration: choose interconnect based on bus standard <Jędrzej Boczar> | * 69d8dd78 - soc/integration: add axi-lite standard to SoCBusHandler <Jędrzej Boczar> * | d38048ba - soc: add initial DMA bus support (optionally provided by CPU(s) for cache coherency). <Florent Kermarrec> |/ * 2361abb1 - Merge pull request timvideos#599 from antmicro/gen-mmcm-pr <enjoy-digital> |\ | * 66c5f371 - litex-gen: add mmcm core <Piotr Binkowski> * 6b72f52c - boards: keep in sync with litex-boards. <Florent Kermarrec> * 1f27b740 - soc/integration/add_sdcard: add direct connection to VexRiscv's dmabus for testing. <Florent Kermarrec> * 408d1a9f - cpu/vexriscv/system.h: update flush_cpu_dcache. <Florent Kermarrec> * 47ce15b4 - interconnect/wishbone: add minimal UpConverter. <Florent Kermarrec> * litex-boards changed from 2ce24df to 2020.08-9-g63b65e2 * 63b65e2 - crosslink_nx_evn: update copyrights. <Florent Kermarrec> * 153326f - targets/icebreaker: update flash. <Florent Kermarrec> * 795e34a - add initial Crosslink-NX support. <Piense> * 84c19a6 - targets/de0nano: set sys2x_ps phase to 180° for sdram_rate=1:2. <Florent Kermarrec> * 70594a5 - ulx3s: simplify sdram constraints and increase phase to 180 for sdram_rate=1:2. <Florent Kermarrec> * 1781be1 - general: add SPDX License identifier to header and specify files are part of LiteX-Boards. <Florent Kermarrec> * 83d8b8d - platforms/acorn_cle_215: integrated sdcard ios as extension. <Florent Kermarrec> * d365836 - Merge pull request timvideos#100 from connorwk/master <enjoy-digital> |\ | * f328909 - Moved platform call inside of BaseSoC init for compatibility with linux-on-litex-vexriscv support. Added optional spi-sdcard support over P2 header. <connorwk> |/ * 45bb329 - targets/colorlight_5a_75x: enable HalfRate SDRAM PHY. <Florent Kermarrec> * b6a1ad5 - targets/orangecrab: add simple CRG when built without DDR3. <Florent Kermarrec> * 869cead - targets: use platform.request_all on LedChaser. <Florent Kermarrec> * 8583c44 - Merge pull request timvideos#98 from antmicro/arty_pmod_configuration <enjoy-digital> |\ | * d2cd6d4 - arty: Change USB-uart and I2S Pmod configuration <Pawel Sagan> |/ * ee28d7b - targets/ulx3s/add_oled: simplify. <Florent Kermarrec> * 623faa9 - Merge pull request timvideos#96 from pepijndevos/oled <enjoy-digital> |\ | * eba7037 - add optional OLED peripheral to ULX3S target <Pepijn de Vos> |/ * 929e55d - platforms/trellisboard: add SDCard PMOD pins. <Florent Kermarrec> * 5fd3e8d - ecpix5: add SDCard. <Florent Kermarrec> * f058181 - README: fix typo. <Florent Kermarrec> * 94ccf1d - targets/trellisboard: simplify clocking when no DDR3, remove firmware_ram (was here for debug). <Florent Kermarrec> * ecdc1ef - README: add missings . <Florent Kermarrec> * 361afa7 - README: add links to LiteX's wiki. <Florent Kermarrec> * 02c0c0a - README: add board picture and fix a few typos. <Florent Kermarrec> * eb8a484 - targets/de10nano: fix typo. <Florent Kermarrec> * 2cef54a - targets/colorlight_5a_75x: avoid sys_clk_freq of 125MHz with etherbone (no longer required). <Florent Kermarrec> * bfbee48 - Readme/boards: fill most of the missing infos. <Florent Kermarrec> * bb65692 - add LICENSE. <Florent Kermarrec> * e9706d4 - README: add initial contents and list of supported boards. <Florent Kermarrec> * 760b8ff - arty: improve xy_pmod_io genericity (allow selecting the PMOD) and enable SDCard. <Florent Kermarrec> * 04fc98f - de0nano/ulx3s: add sdram HalfRate support (untested). <Florent Kermarrec> * d0ca1be - targets/de10nano/minispartan6: simplify HalfRate support, rename argument to sdram_rate. <Florent Kermarrec> * 9730c6f - platforms/de10nano: use additional sdram constraints required for HalfRate. <Florent Kermarrec> * 7399d13 - paltforms/de10nano/sdram: enable fast input/output on dq. <Florent Kermarrec> * b4b1ab8 - paltforms/de10nano: simplify IO constraints (for consistency with others platforms). <Florent Kermarrec> * 89c5bf4 - Merge pull request timvideos#92 from rob-ng15/master <enjoy-digital> |\ | * 7cda143 - Allow use of HalfRateGENSDRPHY <rob-ng15> | * cf98393 - Add Misc <rob-ng15> * | 1e1589a - zybo_z7: demonstrate use of PS7 (with --cpu-type=zynq7000). <Florent Kermarrec> * | 8a3b453 - add Zybo Z7 minimal platform/targets: no PS7 support and USB-UART PMOD on JB. <Florent Kermarrec> |/ * e723bef - platforms/arty: add usb_uart_pmod_io (USB-UART PMOD on JA) to ease debug with a second UART (for UARTbone/LiteScope). <Florent Kermarrec> * 19d0b95 - platforms/targets: keep in sync with litex. <Florent Kermarrec> * 0ee4b21 - trellisboard/ulx3s: fix sdcard slewrate. <Florent Kermarrec> * 7efa1c3 - platforms/arty: add missing pullups on sdcard. <Florent Kermarrec> * litex-renode changed from f179258 to 3d01f40 * 3d01f40 - Merge pull request timvideos#29 from antmicro/i2c_generation <Mateusz Hołenko> * ed34c42 - generate-renode-scripts: Add I2C support <Mateusz Holenko> * a431211 - generate-zephyr-dts: Add I2C support <Mateusz Holenko> * 9f4f0fb - [FIX] Fix config generation <Mateusz Holenko> * nmigen changed from 8f5a253 to 1ad6e32 * 1ad6e32 - Clifford -> Claire <Sebastien Bourdeauducq> * 40f7f12 - Add option to specify solver in nmigen.test.utils <Donald Sebastian Leung> Full submodule status -- 2942d0652a89646c5225bee15dd55cc3b0871766 VexRiscv (1.0.1-417-g2942d06) 3a6108a75be356a3dc53760d22782f1323248b6b edid-decode (heads/master) 3a06aa84b62ad24467fb0d2c6ceddf565e9ea447 flash_proxies (heads/master) 5c69da5d6db245dedab479509c0eaa8c1c80027c litedram (2020.08-3-g5c69da5) 54acf9fd76c226d7760294ffde86418e52e0951b liteeth (2020.04-26-g54acf9f) efd200fa9e625144131a310fc09fd1fecf1682e6 liteiclink (2020.08-1-gefd200f) 0718fd135fc30e0a3598eaf66ce2fcb54b62193c litepcie (2020.08-1-g0718fd1) ba006a78c12e25354dafb021510c043dbe070614 litesata (2020.08-1-gba006a7) 02b543e5ba24c025212515f6e32f542629d823e8 litescope (2020.08-2-g02b543e) 7457a29b1a47fe15e81fa37f3bbdd510788f1d53 liteusb (heads/master) 41f30143075ece3fff5c33a332ed067d1837cbb3 litevideo (2020.04) 3897acb9e4b91ad58abbcea8e3cff6e44223bd02 litex (2020.04-639-g3897acb9) 63b65e278c279a9cf8c4da31db8f7e845edba394 litex-boards (2020.08-9-g63b65e2) 3d01f408539b4641f9d2b42ebd8237436e49d16b litex-renode (remotes/origin/HEAD) 7bc4eb1387b39159a74c1dbd1b820728e0bfbbaa migen (0.6.dev-354-g7bc4eb1) 1ad6e3207f02e913407867dddddb8f50fad0ced4 nmigen (v0.1-71-g1ad6e32) 48333804e40c7c9c1c8d5b2e70ba75f4b646d8f0 pythondata-cpu-lm32 (2020.08) 4731142284cf87e89b21fb35ceff1139f2f89227 pythondata-cpu-minerva (2020.08) af561171f5fc8c684537897f12ef0f429e38624b pythondata-cpu-mor1kx (2020.08) 88974894c800ee2e827db47865e0611a07ff40d7 pythondata-cpu-picorv32 (2020.08) 654057b2f5cec0f9fc99487dff67861f76fcbe7e pythondata-cpu-vexriscv (2020.08) 7cfcaed2e726027fd622650b58dd77e47c495ee0 pythondata-software-compiler_rt (2020.08) da4c8c72eeb22894369b3936abb73f828f222b8e valentyusb (v0.3.3-195-gda4c8c7)

timvideos#191 Add prog-port to Makefile

4385477

probot-autolabeler bot added board-tinyfpga_bx boards-ice40 labels Aug 6, 2019

mithro force-pushed the feat_prog_port_wsl branch from 5e89547 to e36aee9 Compare August 8, 2019 19:55

tinyfpga_bx: Enable not specifying PROG_PORT.

00bf221

tinyprog can auto-find the tinyfpga_bx if PROG_PORT is not specified.

mithro force-pushed the feat_prog_port_wsl branch from e36aee9 to 00bf221 Compare August 8, 2019 21:30

mithro changed the title ~~#191 Add prog-port to Makefile~~ tinyfpga-bx: Add prog-port to Makefile Aug 8, 2019

mithro approved these changes Aug 8, 2019

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mithro merged commit 1fb8ed5 into timvideos:master Aug 8, 2019

whatnick deleted the feat_prog_port_wsl branch October 8, 2019 05:32

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tinyfpga-bx: Add prog-port to Makefile #192

tinyfpga-bx: Add prog-port to Makefile #192

whatnick commented Aug 6, 2019

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tinyfpga-bx: Add prog-port to Makefile #192

tinyfpga-bx: Add prog-port to Makefile #192

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