This is an implementation of a simple CPU in Logisim and Verilog.
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Updated
Jan 11, 2019 - Verilog
This is an implementation of a simple CPU in Logisim and Verilog.
The project will simulate a simple computer system consisting of a CPU and Memory.
Simply the simulated version of the CPU based on 'Reptile' design. It takes an assembly code file as input and shows the final state of all registers and data memory.
A survey on architectural simulators focused on CPU caches.
16-Bit RISC Based CPU Design and Simulation in Python
CENOS: The Modern CPU Simulator
Simple RISC-V CPUs running a baremental ray-tracer program.
CPU Cache Simulation using gem5
Similar - Logic Design & Simulation
In this repo, I'll put projects that I've done in collaboration with chatbots like OpenAI ChatGPT, Google Bard, etc.
Logic gate & circuit simulation framework; 8-bit CPU simulation.
6502 CPU simulator
These are various files pertaining to a CPU I designed. Can be used in conjunction with my Logisim CPU youtube video series.
Intel8085-Simulator: An ongoing project to create a simulator for the Intel 8085 microprocessor. Users can run binary files containing Intel 8085 opcodes and observe their execution. Feel free to use this brief description as needed! 🚀
Simple TLB (Translation lookaside buffer) realization on verilog.
Tera - A simulated ternary (base 3) CPU, assembly language, assembler and decompiler. Uses trytes made up of 9 trits rather than bytes of 8 bits.
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