Here are
21 public repositories
matching this topic...
A Python toolbox for building complex digital hardware [fork for adding nexsys3 support]
Updated
May 31, 2017
Python
USB 2.0 Device IP core using Migen with out-of-box AXI Slave Interface
Updated
Oct 24, 2017
Verilog
gateware for the main fpga, including a hispi decoder and image processing
Updated
Sep 27, 2018
Verilog
Updated
Oct 21, 2018
Python
A unit-test framework for testing Migen modules directely on hardware.
Updated
Jan 23, 2020
Python
WARC Open Fusesoc Cores Repository
Scripts and gateware for the TinyFPGA bx
Updated
Mar 18, 2020
AGS Script
Updated
Apr 11, 2020
Python
CPLD gateware for the Sinara Urukul module
Updated
Nov 18, 2021
Python
Describing RTL circuit in Ruby
Updated
Mar 17, 2022
Ruby
Updated
Jan 27, 2023
Python
Gateware and software for Fastino (32 channel 2.5 MS/s 16 bit DAC for the Sinara ecosystem)
Updated
Mar 2, 2023
Python
FPGA gateware and pre-build bitstreams that expose SPI over JTAG. The protocol is implemented (among others) by openocd.
Updated
Mar 16, 2023
Python
Hardware Motion and Motor Control Library
Updated
Jul 22, 2023
Python
Support files for participating in a Fomu workshop
Updated
Mar 17, 2024
Verilog
Template project for LiteX-based SoCs
Updated
Jul 11, 2024
Python
AXI support for Migen/MiSoC
Updated
Jul 21, 2024
Python
A simple C++ project configured for use with Visual Studio Code, including IntelliSense support, custom file associations, and a GitHub Actions workflow for continuous integration. COA LiTEX
CPLD gateware for the Sinara Mirny module.
Updated
Aug 20, 2024
Python
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