From 08b7092aaa326d2e113d0a5ed41f4d7c0e2fe53b Mon Sep 17 00:00:00 2001 From: dalance Date: Fri, 4 Oct 2024 18:54:20 +0900 Subject: [PATCH] Fix error by repeated generics usage --- .../analyzer/src/handlers/check_expression.rs | 36 +++++++---- crates/analyzer/src/handlers/check_type.rs | 64 +++++++++++++------ .../testcases/sv/54_generic_function.sv.map | 2 +- .../map/testcases/sv/55_generic_module.sv.map | 2 +- .../testcases/sv/56_generic_interface.sv.map | 2 +- .../testcases/sv/57_generic_package.sv.map | 2 +- .../map/testcases/sv/58_generic_struct.sv.map | 2 +- testcases/sv/54_generic_function.sv | 20 ++++-- testcases/sv/55_generic_module.sv | 1 + testcases/sv/56_generic_interface.sv | 1 + testcases/sv/57_generic_package.sv | 1 + testcases/sv/58_generic_struct.sv | 1 + testcases/veryl/54_generic_function.veryl | 10 ++- testcases/veryl/55_generic_module.veryl | 1 + testcases/veryl/56_generic_interface.veryl | 1 + testcases/veryl/57_generic_package.veryl | 1 + testcases/veryl/58_generic_struct.veryl | 1 + 17 files changed, 101 insertions(+), 47 deletions(-) diff --git a/crates/analyzer/src/handlers/check_expression.rs b/crates/analyzer/src/handlers/check_expression.rs index fa810af1..0b5ef33f 100644 --- a/crates/analyzer/src/handlers/check_expression.rs +++ b/crates/analyzer/src/handlers/check_expression.rs @@ -110,7 +110,6 @@ impl<'a> VerylGrammarTrait for CheckExpression<'a> { | SymbolKind::TypeDef(_) | SymbolKind::Modport(_) | SymbolKind::Namespace - | SymbolKind::GenericInstance(_) | SymbolKind::ClockDomain | SymbolKind::Test(_) => { self.errors.push(error); @@ -135,6 +134,7 @@ impl<'a> VerylGrammarTrait for CheckExpression<'a> { | SymbolKind::GenericParameter(_) | SymbolKind::StructMember(_) | SymbolKind::UnionMember(_) + | SymbolKind::GenericInstance(_) | SymbolKind::Variable(_) => {} SymbolKind::Enum(_) | SymbolKind::Union(_) | SymbolKind::Struct(_) => { @@ -150,21 +150,33 @@ impl<'a> VerylGrammarTrait for CheckExpression<'a> { // Must be a function call let expid = x.expression_identifier.as_ref(); if let Ok(rr) = symbol_table::resolve(expid) { - match rr.found.kind { + let is_function = match &rr.found.kind { SymbolKind::Function(_) | SymbolKind::SystemVerilog | SymbolKind::ModportFunctionMember(..) - | SymbolKind::SystemFunction => {} - _ => { - let identifier = rr.found.token.to_string(); - let token: TokenRange = x.expression_identifier.as_ref().into(); - self.errors.push(AnalyzerError::call_non_function( - &identifier, - &rr.found.kind.to_kind_name(), - self.text, - &token, - )); + | SymbolKind::SystemFunction => true, + SymbolKind::GenericInstance(x) => { + let base = symbol_table::get(x.base).unwrap(); + match base.kind { + SymbolKind::Function(_) + | SymbolKind::SystemVerilog + | SymbolKind::ModportFunctionMember(..) + | SymbolKind::SystemFunction => true, + _ => false, + } } + _ => false, + }; + + if !is_function { + let identifier = rr.found.token.to_string(); + let token: TokenRange = x.expression_identifier.as_ref().into(); + self.errors.push(AnalyzerError::call_non_function( + &identifier, + &rr.found.kind.to_kind_name(), + self.text, + &token, + )); } } } diff --git a/crates/analyzer/src/handlers/check_type.rs b/crates/analyzer/src/handlers/check_type.rs index 2e365d51..18b37ad5 100644 --- a/crates/analyzer/src/handlers/check_type.rs +++ b/crates/analyzer/src/handlers/check_type.rs @@ -245,14 +245,34 @@ impl<'a> VerylGrammarTrait for CheckType<'a> { let mut params = vec![]; let mut ports = vec![]; let mut check_port_connection = false; - match symbol.found.kind { + + let type_expected = match symbol.found.kind { SymbolKind::Module(ref x) if self.in_module => { params.append(&mut x.parameters.clone()); ports.append(&mut x.ports.clone()); check_port_connection = true; + None + } + SymbolKind::Interface(_) | SymbolKind::SystemVerilog => None, + SymbolKind::GenericInstance(ref x) => { + let base = symbol_table::get(x.base).unwrap(); + match base.kind { + SymbolKind::Module(ref x) if self.in_module => { + params.append(&mut x.parameters.clone()); + ports.append(&mut x.ports.clone()); + check_port_connection = true; + None + } + SymbolKind::Interface(_) | SymbolKind::SystemVerilog => None, + _ => { + if self.in_module { + Some("module or interface") + } else { + Some("interface") + } + } + } } - SymbolKind::Interface(_) => (), - SymbolKind::SystemVerilog => (), SymbolKind::GenericParameter(ref x) => { if let GenericBoundKind::Proto(ref x) = x.bound { if let Ok(symbol) = symbol_table::resolve((x, &symbol.found.namespace)) @@ -261,32 +281,34 @@ impl<'a> VerylGrammarTrait for CheckType<'a> { params.append(&mut x.parameters.clone()); ports.append(&mut x.ports.clone()); check_port_connection = true; + None } else { - self.errors.push(AnalyzerError::mismatch_type( - name, - "module or interface", - &symbol.found.kind.to_kind_name(), - self.text, - &arg.identifier.as_ref().into(), - )); + Some("module or interface") } + } else { + None } + } else { + None } } _ => { - let expected = if self.in_module { - "module or interface" + if self.in_module { + Some("module or interface") } else { - "interface" - }; - self.errors.push(AnalyzerError::mismatch_type( - name, - expected, - &symbol.found.kind.to_kind_name(), - self.text, - &arg.identifier.as_ref().into(), - )); + Some("interface") + } } + }; + + if let Some(expected) = type_expected { + self.errors.push(AnalyzerError::mismatch_type( + name, + expected, + &symbol.found.kind.to_kind_name(), + self.text, + &arg.identifier.as_ref().into(), + )); } if check_port_connection { diff --git a/testcases/map/testcases/sv/54_generic_function.sv.map b/testcases/map/testcases/sv/54_generic_function.sv.map index 7b7377f9..d037a2f1 100644 --- a/testcases/map/testcases/sv/54_generic_function.sv.map +++ b/testcases/map/testcases/sv/54_generic_function.sv.map @@ -1 +1 @@ -{"version":3,"file":"54_generic_function.sv.map","sources":["../../../veryl/54_generic_function.veryl"],"names":["","module","Module54",";","function","logic","[","10","]","(","input","a",")","return","+","1","endfunction","20","_a","=","__FuncA__10","_b","__FuncA__20","2","4","12","_c","__FuncB__10__2","14","_d","__FuncB__10__4","endmodule"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACZC,mBAEKC,MAAKC,CAACC,MAACC,aAFeC;QACpBC,MAAML,MAAKC,CAACC,MAACC,EAAhBG,CAAiBX;IACrBY,EAAEZ,CAAYA;QACVa,OAAOF,EAAEG,EAAEC,CAACZ;IAChBa;IAJAZ,mBAEKC,MAAKC,CAACW,MAACT,aAFeC;QACpBC,MAAML,MAAKC,CAACW,MAACT,EAAhBG,CAAiBX;IACrBY,EAAEZ,CAAYA;QACVa,OAAOF,EAAEG,EAAEC,CAACZ;IAChBa;;IAEQX,MAAKC,CAACC,MAAEC,EAAZU;mBAAcC,EAAEC,WAAWX,CAACM,CAACH,CAACT;IAC1BE,MAAKC,CAACW,MAAET,EAAZa;mBAAcF,EAAEG,WAAWb,CAACM,CAACH,CAACT;;IAElCC,mBAEKC,MAAKC,CAACC,GAAEO,EAAES,KAACf,gBAFyBC;QAClCC,MAAML,MAAKC,CAACC,GAAEO,EAAES,KAACf,EAApBG,CAAqBX;IACzBY,EAAEZ,CAAgBA;QACda,OAAOF,EAAEG,EAAEC,CAACZ;IAChBa;IAJAZ,mBAEKC,MAAKC,CAACC,GAAEO,EAAEU,KAAChB,gBAFyBC;QAClCC,MAAML,MAAKC,CAACC,GAAEO,EAAEU,KAAChB,EAApBG,CAAqBX;IACzBY,EAAEZ,CAAgBA;QACda,OAAOF,EAAEG,EAAEC,CAACZ;IAChBa;;IAEQX,MAAKC,CAACmB,MAAEjB,EAAZkB;mBAAcP,EAAEQ,cAAWlB,CAACM,CAACH,CAACT;IAC1BE,MAAKC,CAACsB,MAAEpB,EAAZqB;mBAAcV,EAAEW,cAAcrB,CAACM,CAACH,CAACT;AACzC4B"} \ No newline at end of file +{"version":3,"file":"54_generic_function.sv.map","sources":["../../../veryl/54_generic_function.veryl"],"names":["","module","Module54",";","function","logic","[","10","]","(","input","a",")","return","+","1","endfunction","20","_a","=","__FuncA__10","_b","_c","__FuncA__20","_d","2","4","12","_e","__FuncB__10__2","_f","14","_g","__FuncB__10__4","_h","endmodule"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACZC,mBAEKC,MAAKC,CAACC,MAACC,aAFeC;QACpBC,MAAML,MAAKC,CAACC,MAACC,EAAhBG,CAAiBX;IACrBY,EAAEZ,CAAYA;QACVa,OAAOF,EAAEG,EAAEC,CAACZ;IAChBa;IAJAZ,mBAEKC,MAAKC,CAACW,MAACT,aAFeC;QACpBC,MAAML,MAAKC,CAACW,MAACT,EAAhBG,CAAiBX;IACrBY,EAAEZ,CAAYA;QACVa,OAAOF,EAAEG,EAAEC,CAACZ;IAChBa;;IAEQX,MAAKC,CAACC,MAAEC,EAAZU;mBAAcC,EAAEC,WAAWX,CAACM,CAACH,CAACT;IAC1BE,MAAKC,CAACC,MAAEC,EAAZa;mBAAcF,EAAEC,WAAWX,CAACM,CAACH,CAACT;IAC1BE,MAAKC,CAACW,MAAET,EAAZc;mBAAcH,EAAEI,WAAWd,CAACM,CAACH,CAACT;IAC1BE,MAAKC,CAACW,MAAET,EAAZgB;mBAAcL,EAAEI,WAAWd,CAACM,CAACH,CAACT;;IAElCC,mBAEKC,MAAKC,CAACC,GAAEO,EAAEW,KAACjB,gBAFyBC;QAClCC,MAAML,MAAKC,CAACC,GAAEO,EAAEW,KAACjB,EAApBG,CAAqBX;IACzBY,EAAEZ,CAAgBA;QACda,OAAOF,EAAEG,EAAEC,CAACZ;IAChBa;IAJAZ,mBAEKC,MAAKC,CAACC,GAAEO,EAAEY,KAAClB,gBAFyBC;QAClCC,MAAML,MAAKC,CAACC,GAAEO,EAAEY,KAAClB,EAApBG,CAAqBX;IACzBY,EAAEZ,CAAgBA;QACda,OAAOF,EAAEG,EAAEC,CAACZ;IAChBa;;IAEQX,MAAKC,CAACqB,MAAEnB,EAAZoB;mBAAcT,EAAEU,cAAWpB,CAACM,CAACH,CAACT;IAC1BE,MAAKC,CAACqB,MAAEnB,EAAZsB;mBAAcX,EAAEU,cAAWpB,CAACM,CAACH,CAACT;IAC1BE,MAAKC,CAACyB,MAAEvB,EAAZwB;mBAAcb,EAAEc,cAAcxB,CAACM,CAACH,CAACT;IAC7BE,MAAKC,CAACyB,MAAEvB,EAAZ0B;mBAAcf,EAAEc,cAAcxB,CAACM,CAACH,CAACT;AACzCgC"} \ No newline at end of file diff --git a/testcases/map/testcases/sv/55_generic_module.sv.map b/testcases/map/testcases/sv/55_generic_module.sv.map index bbdba366..61f514dc 100644 --- a/testcases/map/testcases/sv/55_generic_module.sv.map +++ b/testcases/map/testcases/sv/55_generic_module.sv.map @@ -1 +1 @@ -{"version":3,"file":"55_generic_module.sv.map","sources":["../../../veryl/55_generic_module.veryl"],"names":["","module","Module55",";","veryl_testcase___Module55A__Module55B","u0","veryl_testcase___Module55A__Module55C","u1","veryl_testcase___Module55E__Module55C","u2","veryl_testcase___Module55E__Module55D","u3","veryl_testcase___Module55F__Module55C","u4","veryl_testcase___Module55F__Module55B","u5","veryl_testcase___Module55H__10","u6","endmodule","veryl_testcase_Module55B","u","veryl_testcase_Module55C","veryl_testcase_Module55D","Module55B","Module55C","Module55D","veryl_testcase___Module55A__Module55D","typedef struct packed","{","logic","[","10","]","value","__StructH__10","_a","=","0"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACZH,AAASI,sCAAJC,KAA0BF;IAC/BH,AAASM,sCAAJC,KAA0BJ;IAC/BH,AAASQ,sCAAJC,KAA0BN;IAC/BH,AAASU,sCAAJC,KAA0BR;IAC/BH,AAASY,sCAAJC,KAA0BV;IAC/BH,AAASc,sCAAJC,KAAiBZ;IACtBH,AAASgB,+BAAJC,KAAmBd;AAC5Be;;;AAKIjB,4CAA+BE;IAC/BH,AAAQmB,yBAAHC,IAAIjB;AACbe;AAFIjB,4CAA+BE;IAC/BH,AAAQqB,yBAAHD,IAAIjB;AACbe;AAFIjB,4CAA+BE;IAC/BH,AAAQsB,yBAAHF,IAAIjB;AACbe;;AAEAjB,sBAAOsB,SAAsBpB;AAACe;;AAE9BjB,sBAAOuB,SAAsBrB;AAACe;;AAE9BjB,sBAAOwB,SAAsBtB;AAACe;;AAE9BjB,4CAA+BE;IAC3BH,AAAQM,sCAAHc,IAAiBjB;AAC1Be;AAFAjB,4CAA+BE;IAC3BH,AAAQ0B,sCAAHN,IAAiBjB;AAC1Be;;AAEAjB,4CAA2CE;IACvCH,AAAQqB,yBAAHD,IAAIjB;AACbe;AAFAjB,4CAA2CE;IACvCH,AAAQmB,yBAAHC,IAAIjB;AACbe;;;AAMAjB,qCAA6BE;IACzBwB,sBAA2BC;QAChBC,MAAKC,CAACC,MAACC,EAAdC,KAAe9B;oBACnBH;;IAEQkC,cAAJC;mBAAiBC,EAAEC,CAAClC;AAC5Be"} \ No newline at end of file +{"version":3,"file":"55_generic_module.sv.map","sources":["../../../veryl/55_generic_module.veryl"],"names":["","module","Module55",";","veryl_testcase___Module55A__Module55B","u0","veryl_testcase___Module55A__Module55C","u1","veryl_testcase___Module55E__Module55C","u2","veryl_testcase___Module55E__Module55D","u3","veryl_testcase___Module55F__Module55C","u4","veryl_testcase___Module55F__Module55B","u5","veryl_testcase___Module55H__10","u6","u7","endmodule","veryl_testcase_Module55B","u","veryl_testcase_Module55C","veryl_testcase_Module55D","Module55B","Module55C","Module55D","veryl_testcase___Module55A__Module55D","typedef struct packed","{","logic","[","10","]","value","__StructH__10","_a","=","0"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACZH,AAASI,sCAAJC,KAA0BF;IAC/BH,AAASM,sCAAJC,KAA0BJ;IAC/BH,AAASQ,sCAAJC,KAA0BN;IAC/BH,AAASU,sCAAJC,KAA0BR;IAC/BH,AAASY,sCAAJC,KAA0BV;IAC/BH,AAASc,sCAAJC,KAAiBZ;IACtBH,AAASgB,+BAAJC,KAAmBd;IACxBH,AAASgB,+BAAJE,KAAmBf;AAC5BgB;;;AAKIlB,4CAA+BE;IAC/BH,AAAQoB,yBAAHC,IAAIlB;AACbgB;AAFIlB,4CAA+BE;IAC/BH,AAAQsB,yBAAHD,IAAIlB;AACbgB;AAFIlB,4CAA+BE;IAC/BH,AAAQuB,yBAAHF,IAAIlB;AACbgB;;AAEAlB,sBAAOuB,SAAsBrB;AAACgB;;AAE9BlB,sBAAOwB,SAAsBtB;AAACgB;;AAE9BlB,sBAAOyB,SAAsBvB;AAACgB;;AAE9BlB,4CAA+BE;IAC3BH,AAAQM,sCAAHe,IAAiBlB;AAC1BgB;AAFAlB,4CAA+BE;IAC3BH,AAAQ2B,sCAAHN,IAAiBlB;AAC1BgB;;AAEAlB,4CAA2CE;IACvCH,AAAQsB,yBAAHD,IAAIlB;AACbgB;AAFAlB,4CAA2CE;IACvCH,AAAQoB,yBAAHC,IAAIlB;AACbgB;;;AAMAlB,qCAA6BE;IACzByB,sBAA2BC;QAChBC,MAAKC,CAACC,MAACC,EAAdC,KAAe/B;oBACnBH;;IAEQmC,cAAJC;mBAAiBC,EAAEC,CAACnC;AAC5BgB"} \ No newline at end of file diff --git a/testcases/map/testcases/sv/56_generic_interface.sv.map b/testcases/map/testcases/sv/56_generic_interface.sv.map index b4a4c272..1263b7c6 100644 --- a/testcases/map/testcases/sv/56_generic_interface.sv.map +++ b/testcases/map/testcases/sv/56_generic_interface.sv.map @@ -1 +1 @@ -{"version":3,"file":"56_generic_interface.sv.map","sources":["../../../veryl/56_generic_interface.veryl"],"names":["","module","Module56",";","veryl_testcase___Interface56A__Package56A","u0","veryl_testcase___Interface56A__Package56B","u1","veryl_testcase___Interface56B__Package56A","u2","veryl_testcase___Interface56B__Package56B","u3","endmodule","interface","logic","[","veryl_testcase_Package56A::X","]","_a","endinterface","veryl_testcase_Package56B::X","_b","package","Package56A","localparam","int unsigned","X","=","1","endpackage","Package56B","2"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACZH,AAASI,0CAAJC,KAA8BF;IACnCH,AAASM,0CAAJC,KAA8BJ;IACnCH,AAASQ,0CAAJC,KAA8BN;IACnCH,AAASU,0CAAJC,KAAoBR;AAC7BS;;;AAGIC,mDAAmCV;IAC3BW,MAAKC,CAACC,gCAAIC,EAAdC,EAAef;AACvBgB;;;AAFIN,mDAAmCV;IAC3BW,MAAKC,CAACK,gCAAIH,EAAdC,EAAef;AACvBgB;;;AAGIN,mDAAgDV;IACxCW,MAAKC,CAACC,gCAAIC,EAAdI,EAAelB;AACvBgB;AAFIN,mDAAgDV;IACxCW,MAAKC,CAACK,gCAAIH,EAAdI,EAAelB;AACvBgB;;AAEAG,uBAAQC,UAAWpB;IACfqB,WAASC,aAAHC,EAAOC,EAAEC,CAACzB;AACpB0B;;AAEAP,uBAAQQ,UAAW3B;IACfqB,WAASC,aAAHC,EAAOC,EAAEI,CAAC5B;AACpB0B"} \ No newline at end of file +{"version":3,"file":"56_generic_interface.sv.map","sources":["../../../veryl/56_generic_interface.veryl"],"names":["","module","Module56",";","veryl_testcase___Interface56A__Package56A","u0","veryl_testcase___Interface56A__Package56B","u1","veryl_testcase___Interface56B__Package56A","u2","u4","veryl_testcase___Interface56B__Package56B","u3","endmodule","interface","logic","[","veryl_testcase_Package56A::X","]","_a","endinterface","veryl_testcase_Package56B::X","_b","package","Package56A","localparam","int unsigned","X","=","1","endpackage","Package56B","2"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACZH,AAASI,0CAAJC,KAA8BF;IACnCH,AAASM,0CAAJC,KAA8BJ;IACnCH,AAASQ,0CAAJC,KAA8BN;IACnCH,AAASQ,0CAAJE,KAA8BP;IACnCH,AAASW,0CAAJC,KAAoBT;AAC7BU;;;AAGIC,mDAAmCX;IAC3BY,MAAKC,CAACC,gCAAIC,EAAdC,EAAehB;AACvBiB;;;AAFIN,mDAAmCX;IAC3BY,MAAKC,CAACK,gCAAIH,EAAdC,EAAehB;AACvBiB;;;AAGIN,mDAAgDX;IACxCY,MAAKC,CAACC,gCAAIC,EAAdI,EAAenB;AACvBiB;AAFIN,mDAAgDX;IACxCY,MAAKC,CAACK,gCAAIH,EAAdI,EAAenB;AACvBiB;;AAEAG,uBAAQC,UAAWrB;IACfsB,WAASC,aAAHC,EAAOC,EAAEC,CAAC1B;AACpB2B;;AAEAP,uBAAQQ,UAAW5B;IACfsB,WAASC,aAAHC,EAAOC,EAAEI,CAAC7B;AACpB2B"} \ No newline at end of file diff --git a/testcases/map/testcases/sv/57_generic_package.sv.map b/testcases/map/testcases/sv/57_generic_package.sv.map index 41d0e222..6b2db48a 100644 --- a/testcases/map/testcases/sv/57_generic_package.sv.map +++ b/testcases/map/testcases/sv/57_generic_package.sv.map @@ -1 +1 @@ -{"version":3,"file":"57_generic_package.sv.map","sources":["../../../veryl/57_generic_package.veryl"],"names":["","module","Module57",";","localparam","int unsigned","A","=","veryl_testcase___Package57A__1::X","longint unsigned","B","veryl_testcase___Package57A__2::X","C","veryl_testcase___Package57B__3::X","D","veryl_testcase___Package57B__4::X","veryl_testcase___Package57C__2::StructC","_e","always_comb",".","c","1","endmodule","package","X","endpackage","2","3","4","typedef struct packed","{","logic","[","]","StructC"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACZC,WAASC,iBAAHC,EAAOC,EAAEC,iCAAkBL;IACjCC,WAASK,iBAAHC,EAAOH,EAAEI,iCAAkBR;IACjCC,WAASC,iBAAHO,EAAOL,EAAEM,iCAAkBV;IACjCC,WAASK,iBAAHK,EAAOP,EAAEQ,iCAAiBZ;;IAEtBa,wCAANC,IAA8Bd;IAClCe,YAAOD,EAAEE,CAACC,EAAEb,EAAEc,CAAClB;AACnBmB;;;AAGIC,sCAA+BpB;IAC/BC,WAASC,aAAHmB,EAAOjB,EAAEc,CAAClB;AACpBsB;;;AAFIF,sCAA+BpB;IAC/BC,WAASC,aAAHmB,EAAOjB,EAAEmB,CAACvB;AACpBsB;;;AAGIF,sCAAmCpB;IACnCC,WAASC,aAAHmB,EAAOjB,EAAEoB,CAACxB;AACpBsB;AAFIF,sCAAmCpB;IACnCC,WAASC,aAAHmB,EAAOjB,EAAEqB,CAACzB;AACpBsB;;AAEAF,sCAA+BpB;IAC3B0B,sBAAeC;QACRC,MAAKC,CAACN,KAACO,EAAVb,CAAWjB;MADR+B,QAEPlC;AACJyB"} \ No newline at end of file +{"version":3,"file":"57_generic_package.sv.map","sources":["../../../veryl/57_generic_package.veryl"],"names":["","module","Module57",";","localparam","int unsigned","A","=","veryl_testcase___Package57A__1::X","longint unsigned","B","veryl_testcase___Package57A__2::X","C","veryl_testcase___Package57B__3::X","E","D","veryl_testcase___Package57B__4::X","veryl_testcase___Package57C__2::StructC","_e","always_comb",".","c","1","endmodule","package","X","endpackage","2","3","4","typedef struct packed","{","logic","[","]","StructC"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACZC,WAASC,iBAAHC,EAAOC,EAAEC,iCAAkBL;IACjCC,WAASK,iBAAHC,EAAOH,EAAEI,iCAAkBR;IACjCC,WAASC,iBAAHO,EAAOL,EAAEM,iCAAkBV;IACjCC,WAASC,iBAAHS,EAAOP,EAAEM,iCAAkBV;IACjCC,WAASK,iBAAHM,EAAOR,EAAES,iCAAiBb;;IAEtBc,wCAANC,IAA8Bf;IAClCgB,YAAOD,EAAEE,CAACC,EAAEd,EAAEe,CAACnB;AACnBoB;;;AAGIC,sCAA+BrB;IAC/BC,WAASC,aAAHoB,EAAOlB,EAAEe,CAACnB;AACpBuB;;;AAFIF,sCAA+BrB;IAC/BC,WAASC,aAAHoB,EAAOlB,EAAEoB,CAACxB;AACpBuB;;;AAGIF,sCAAmCrB;IACnCC,WAASC,aAAHoB,EAAOlB,EAAEqB,CAACzB;AACpBuB;AAFIF,sCAAmCrB;IACnCC,WAASC,aAAHoB,EAAOlB,EAAEsB,CAAC1B;AACpBuB;;AAEAF,sCAA+BrB;IAC3B2B,sBAAeC;QACRC,MAAKC,CAACN,KAACO,EAAVb,CAAWlB;MADRgC,QAEPnC;AACJ0B"} \ No newline at end of file diff --git a/testcases/map/testcases/sv/58_generic_struct.sv.map b/testcases/map/testcases/sv/58_generic_struct.sv.map index 9d827023..d2002a25 100644 --- a/testcases/map/testcases/sv/58_generic_struct.sv.map +++ b/testcases/map/testcases/sv/58_generic_struct.sv.map @@ -1 +1 @@ -{"version":3,"file":"58_generic_struct.sv.map","sources":["../../../veryl/58_generic_struct.veryl"],"names":["","module","Module58",";","typedef struct packed","{","veryl_testcase_Package58::B","A","veryl_testcase_Package58::C","C","typedef","int signed","B","__StructA__Package58_B","_a","__StructA__Package58_C","_b","__StructA__C","_c","__StructB__Package58_C","_d","__StructB__C","_e","endmodule","package","Package58","int unsigned","longint unsigned","endpackage"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACZC,sBAA0BC;QACnBC,4BAAHC,CAAIJ;6BACRH;IAFAI,sBAA0BC;QACnBG,4BAAHD,CAAIJ;6BACRH;IAFAI,sBAA0BC;QACnBI,EAAHF,CAAIJ;mBACRH;;IAEAU,QAASC,WAAJF,CAAON;;IAEZC,sBAA8BC;QACvBG,4BAAHI,CAAIT;6BACRH;IAFAI,sBAA8BC;QACvBI,EAAHG,CAAIT;mBACRH;;IAEQa,uBAAJC,EAA2BX;IACvBY,uBAAJC,EAA2Bb;IACvBc,uBAAJC,EAA2Bf;IACvBgB,uBAAJC,EAA2BjB;IACvBkB,aAAJC,EAA2BnB;AACnCoB;;AAEAC,uBAAQC,SAAUtB;IACdO,QAASgB,iBAAJd,CAAOT;IACZO,QAASiB,iBAAJlB,CAAON;AAChByB"} \ No newline at end of file +{"version":3,"file":"58_generic_struct.sv.map","sources":["../../../veryl/58_generic_struct.veryl"],"names":["","module","Module58",";","typedef struct packed","{","veryl_testcase_Package58::B","A","veryl_testcase_Package58::C","C","typedef","int signed","B","__StructA__Package58_B","_a","__StructA__Package58_C","_b","__StructA__C","_c","__StructB__Package58_C","_d","_f","__StructB__C","_e","endmodule","package","Package58","int unsigned","longint unsigned","endpackage"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACZC,sBAA0BC;QACnBC,4BAAHC,CAAIJ;6BACRH;IAFAI,sBAA0BC;QACnBG,4BAAHD,CAAIJ;6BACRH;IAFAI,sBAA0BC;QACnBI,EAAHF,CAAIJ;mBACRH;;IAEAU,QAASC,WAAJF,CAAON;;IAEZC,sBAA8BC;QACvBG,4BAAHI,CAAIT;6BACRH;IAFAI,sBAA8BC;QACvBI,EAAHG,CAAIT;mBACRH;;IAEQa,uBAAJC,EAA2BX;IACvBY,uBAAJC,EAA2Bb;IACvBc,uBAAJC,EAA2Bf;IACvBgB,uBAAJC,EAA2BjB;IACvBgB,uBAAJE,EAA2BlB;IACvBmB,aAAJC,EAA2BpB;AACnCqB;;AAEAC,uBAAQC,SAAUvB;IACdO,QAASiB,iBAAJf,CAAOT;IACZO,QAASkB,iBAAJnB,CAAON;AAChB0B"} \ No newline at end of file diff --git a/testcases/sv/54_generic_function.sv b/testcases/sv/54_generic_function.sv index 3298531a..826ad0f0 100644 --- a/testcases/sv/54_generic_function.sv +++ b/testcases/sv/54_generic_function.sv @@ -12,8 +12,12 @@ module veryl_testcase_Module54; logic [10-1:0] _a; always_comb _a = __FuncA__10(1); - logic [20-1:0] _b; - always_comb _b = __FuncA__20(1); + logic [10-1:0] _b; + always_comb _b = __FuncA__10(1); + logic [20-1:0] _c; + always_comb _c = __FuncA__20(1); + logic [20-1:0] _d; + always_comb _d = __FuncA__20(1); function automatic logic [10 + 2-1:0] __FuncB__10__2( input logic [10 + 2-1:0] a @@ -26,9 +30,13 @@ module veryl_testcase_Module54; return a + 1; endfunction - logic [12-1:0] _c; - always_comb _c = __FuncB__10__2(1); - logic [14-1:0] _d; - always_comb _d = __FuncB__10__4(1); + logic [12-1:0] _e; + always_comb _e = __FuncB__10__2(1); + logic [12-1:0] _f; + always_comb _f = __FuncB__10__2(1); + logic [14-1:0] _g; + always_comb _g = __FuncB__10__4(1); + logic [14-1:0] _h; + always_comb _h = __FuncB__10__4(1); endmodule //# sourceMappingURL=../map/testcases/sv/54_generic_function.sv.map diff --git a/testcases/sv/55_generic_module.sv b/testcases/sv/55_generic_module.sv index 34ba08fd..ca295bb8 100644 --- a/testcases/sv/55_generic_module.sv +++ b/testcases/sv/55_generic_module.sv @@ -6,6 +6,7 @@ module veryl_testcase_Module55; veryl_testcase___Module55F__Module55C u4 (); veryl_testcase___Module55F__Module55B u5 (); veryl_testcase___Module55H__10 u6 (); + veryl_testcase___Module55H__10 u7 (); endmodule diff --git a/testcases/sv/56_generic_interface.sv b/testcases/sv/56_generic_interface.sv index 744470b6..515ac5ff 100644 --- a/testcases/sv/56_generic_interface.sv +++ b/testcases/sv/56_generic_interface.sv @@ -2,6 +2,7 @@ module veryl_testcase_Module56; veryl_testcase___Interface56A__Package56A u0 (); veryl_testcase___Interface56A__Package56B u1 (); veryl_testcase___Interface56B__Package56A u2 (); + veryl_testcase___Interface56B__Package56A u4 (); veryl_testcase___Interface56B__Package56B u3 (); endmodule diff --git a/testcases/sv/57_generic_package.sv b/testcases/sv/57_generic_package.sv index 5dac56fe..49cf49af 100644 --- a/testcases/sv/57_generic_package.sv +++ b/testcases/sv/57_generic_package.sv @@ -2,6 +2,7 @@ module veryl_testcase_Module57; localparam int unsigned A = veryl_testcase___Package57A__1::X; localparam longint unsigned B = veryl_testcase___Package57A__2::X; localparam int unsigned C = veryl_testcase___Package57B__3::X; + localparam int unsigned E = veryl_testcase___Package57B__3::X; localparam longint unsigned D = veryl_testcase___Package57B__4::X; veryl_testcase___Package57C__2::StructC _e ; diff --git a/testcases/sv/58_generic_struct.sv b/testcases/sv/58_generic_struct.sv index 86c2c894..ec5d25fb 100644 --- a/testcases/sv/58_generic_struct.sv +++ b/testcases/sv/58_generic_struct.sv @@ -22,6 +22,7 @@ module veryl_testcase_Module58; __StructA__Package58_C _b; __StructA__C _c; __StructB__Package58_C _d; + __StructB__Package58_C _f; __StructB__C _e; endmodule diff --git a/testcases/veryl/54_generic_function.veryl b/testcases/veryl/54_generic_function.veryl index abb2bb98..29c91b70 100644 --- a/testcases/veryl/54_generic_function.veryl +++ b/testcases/veryl/54_generic_function.veryl @@ -6,7 +6,9 @@ module Module54 { } let _a: logic<10> = FuncA::<10>(1); - let _b: logic<20> = FuncA::<20>(1); + let _b: logic<10> = FuncA::<10>(1); + let _c: logic<20> = FuncA::<20>(1); + let _d: logic<20> = FuncA::<20>(1); function FuncB:: ( a: input logic, @@ -14,6 +16,8 @@ module Module54 { return a + 1; } - let _c: logic<12> = FuncB::<10>(1); - let _d: logic<14> = FuncB::<10, 4>(1); + let _e: logic<12> = FuncB::<10>(1); + let _f: logic<12> = FuncB::<10>(1); + let _g: logic<14> = FuncB::<10, 4>(1); + let _h: logic<14> = FuncB::<10, 4>(1); } diff --git a/testcases/veryl/55_generic_module.veryl b/testcases/veryl/55_generic_module.veryl index 20aaf286..44cd3dc6 100644 --- a/testcases/veryl/55_generic_module.veryl +++ b/testcases/veryl/55_generic_module.veryl @@ -6,6 +6,7 @@ module Module55 { inst u4: Module55F::; inst u5: Module55F::<>; inst u6: Module55H::<10>; + inst u7: Module55H::<10>; } pub proto module Proto55; diff --git a/testcases/veryl/56_generic_interface.veryl b/testcases/veryl/56_generic_interface.veryl index 9855c7fd..27269530 100644 --- a/testcases/veryl/56_generic_interface.veryl +++ b/testcases/veryl/56_generic_interface.veryl @@ -2,6 +2,7 @@ module Module56 { inst u0: Interface56A::; inst u1: Interface56A::; inst u2: Interface56B::; + inst u4: Interface56B::; inst u3: Interface56B::<>; } diff --git a/testcases/veryl/57_generic_package.veryl b/testcases/veryl/57_generic_package.veryl index 2abfb292..d434d62c 100644 --- a/testcases/veryl/57_generic_package.veryl +++ b/testcases/veryl/57_generic_package.veryl @@ -2,6 +2,7 @@ module Module57 { const A: u32 = Package57A::<1>::X; const B: u64 = Package57A::<2>::X; const C: u32 = Package57B::<3>::X; + const E: u32 = Package57B::<3>::X; const D: u64 = Package57B::<>::X; var _e : Package57C::<2>::StructC; diff --git a/testcases/veryl/58_generic_struct.veryl b/testcases/veryl/58_generic_struct.veryl index ca7af13b..39588fe1 100644 --- a/testcases/veryl/58_generic_struct.veryl +++ b/testcases/veryl/58_generic_struct.veryl @@ -13,6 +13,7 @@ module Module58 { var _b: StructA::; var _c: StructA:: ; var _d: StructB::; + var _f: StructB::; var _e: StructB::<> ; }