From 11f23d20cb9bfc1c3e109f26122c10adadab5dc8 Mon Sep 17 00:00:00 2001 From: dalance Date: Thu, 21 Mar 2024 16:36:03 +0900 Subject: [PATCH] Adjust multiline case item indent --- crates/emitter/src/emitter.rs | 13 ++++++++++++- crates/formatter/src/formatter.rs | 13 ++++++++++++- testcases/sv/16_case.sv | 8 ++++---- testcases/veryl/16_case.veryl | 8 ++++---- 4 files changed, 32 insertions(+), 10 deletions(-) diff --git a/crates/emitter/src/emitter.rs b/crates/emitter/src/emitter.rs index b0fe656c..22404cff 100644 --- a/crates/emitter/src/emitter.rs +++ b/crates/emitter/src/emitter.rs @@ -28,6 +28,7 @@ pub struct Emitter { consumed_next_newline: bool, single_line: bool, adjust_line: bool, + case_item_indent: Option, in_always_ff: bool, in_generate: bool, in_direction_modport: bool, @@ -55,6 +56,7 @@ impl Default for Emitter { consumed_next_newline: false, single_line: false, adjust_line: false, + case_item_indent: None, in_always_ff: false, in_generate: false, in_direction_modport: false, @@ -92,6 +94,10 @@ impl Emitter { &self.string } + fn column(&self) -> usize { + self.string.len() - self.string.rfind('\n').unwrap_or(0) + } + fn str(&mut self, x: &str) { self.string.push_str(x); } @@ -107,7 +113,9 @@ impl Emitter { } fn indent(&mut self) { - self.str(&" ".repeat(self.indent * self.format_opt.indent_width)); + self.str(&" ".repeat( + self.indent * self.format_opt.indent_width + self.case_item_indent.unwrap_or(0), + )); } fn newline_push(&mut self) { @@ -1341,12 +1349,14 @@ impl VerylWalker for Emitter { /// Semantic action for non-terminal 'CaseItem' fn case_item(&mut self, arg: &CaseItem) { + let start = self.column(); match &*arg.case_item_group { CaseItemGroup::Expression(x) => self.expression(&x.expression), CaseItemGroup::Defaul(x) => self.defaul(&x.defaul), } self.colon(&arg.colon); self.space(1); + self.case_item_indent = Some(self.column() - start); match &*arg.case_item_group0 { CaseItemGroup0::Statement(x) => self.statement(&x.statement), CaseItemGroup0::LBraceCaseItemGroup0ListRBrace(x) => { @@ -1369,6 +1379,7 @@ impl VerylWalker for Emitter { self.token(&x.r_brace.r_brace_token.replace("end")); } } + self.case_item_indent = None; } /// Semantic action for non-terminal 'Attribute' diff --git a/crates/formatter/src/formatter.rs b/crates/formatter/src/formatter.rs index d4ccb526..9cbca3a8 100644 --- a/crates/formatter/src/formatter.rs +++ b/crates/formatter/src/formatter.rs @@ -16,6 +16,7 @@ pub struct Formatter { consumed_next_newline: bool, single_line: bool, adjust_line: bool, + case_item_indent: Option, } impl Default for Formatter { @@ -31,6 +32,7 @@ impl Default for Formatter { consumed_next_newline: false, single_line: false, adjust_line: false, + case_item_indent: None, } } } @@ -52,6 +54,10 @@ impl Formatter { &self.string } + fn column(&self) -> usize { + self.string.len() - self.string.rfind('\n').unwrap_or(0) + } + fn str(&mut self, x: &str) { self.string.push_str(x); } @@ -67,7 +73,9 @@ impl Formatter { } fn indent(&mut self) { - self.str(&" ".repeat(self.indent * self.format_opt.indent_width)); + self.str(&" ".repeat( + self.indent * self.format_opt.indent_width + self.case_item_indent.unwrap_or(0), + )); } fn newline_push(&mut self) { @@ -707,12 +715,14 @@ impl VerylWalker for Formatter { /// Semantic action for non-terminal 'CaseItem' fn case_item(&mut self, arg: &CaseItem) { + let start = self.column(); match &*arg.case_item_group { CaseItemGroup::Expression(x) => self.expression(&x.expression), CaseItemGroup::Defaul(x) => self.defaul(&x.defaul), } self.colon(&arg.colon); self.space(1); + self.case_item_indent = Some(self.column() - start); match &*arg.case_item_group0 { CaseItemGroup0::Statement(x) => self.statement(&x.statement), CaseItemGroup0::LBraceCaseItemGroup0ListRBrace(x) => { @@ -725,6 +735,7 @@ impl VerylWalker for Formatter { self.r_brace(&x.r_brace); } } + self.case_item_indent = None; } /// Semantic action for non-terminal 'AttributeList' diff --git a/testcases/sv/16_case.sv b/testcases/sv/16_case.sv index fb3214a7..2325c8b5 100644 --- a/testcases/sv/16_case.sv +++ b/testcases/sv/16_case.sv @@ -8,10 +8,10 @@ module veryl_testcase_Module16; 0: a = 1; 1: a = 1; 2: begin - a = 1; - a = 1; - a = 1; - end + a = 1; + a = 1; + a = 1; + end y - 1 : a = 1; default: a = 1; endcase diff --git a/testcases/veryl/16_case.veryl b/testcases/veryl/16_case.veryl index e15cf5a9..006c7cce 100644 --- a/testcases/veryl/16_case.veryl +++ b/testcases/veryl/16_case.veryl @@ -8,10 +8,10 @@ module Module16 { 0: a = 1; 1: a = 1; 2: { - a = 1; - a = 1; - a = 1; - } + a = 1; + a = 1; + a = 1; + } y - 1 : a = 1; default: a = 1; }