From 4ab294dce6fa2839683020a77b63c969c01b297b Mon Sep 17 00:00:00 2001 From: dalance Date: Mon, 30 Sep 2024 16:53:24 +0900 Subject: [PATCH] Allow msb for port --- crates/analyzer/src/handlers/check_msb_lsb.rs | 11 +++++++++-- testcases/map/testcases/sv/28_msblsb.sv.map | 2 +- testcases/sv/28_msblsb.sv | 6 +++++- testcases/veryl/28_msblsb.veryl | 5 ++++- 4 files changed, 19 insertions(+), 5 deletions(-) diff --git a/crates/analyzer/src/handlers/check_msb_lsb.rs b/crates/analyzer/src/handlers/check_msb_lsb.rs index c895de5c..8488596d 100644 --- a/crates/analyzer/src/handlers/check_msb_lsb.rs +++ b/crates/analyzer/src/handlers/check_msb_lsb.rs @@ -72,8 +72,15 @@ impl<'a> VerylGrammarTrait for CheckMsbLsb<'a> { symbol_table::resolve(self.identifier_path.last().unwrap().clone()) { let namespace = &x.found.namespace; - if let SymbolKind::Variable(x) = x.found.kind { - let types = trace_type(&x.r#type, namespace); + + let r#type = match x.found.kind { + SymbolKind::Variable(x) => Some(x.r#type), + SymbolKind::Port(x) => x.r#type, + _ => None, + }; + + if let Some(x) = r#type { + let types = trace_type(&x, namespace); let mut select_dimension = *self.select_dimension.last().unwrap(); let mut expression = None; diff --git a/testcases/map/testcases/sv/28_msblsb.sv.map b/testcases/map/testcases/sv/28_msblsb.sv.map index 0a20f2c0..50cf2fec 100644 --- a/testcases/map/testcases/sv/28_msblsb.sv.map +++ b/testcases/map/testcases/sv/28_msblsb.sv.map @@ -1 +1 @@ -{"version":3,"file":"28_msblsb.sv.map","sources":["../../../veryl/28_msblsb.veryl"],"names":["","module","Module28",";","localparam","int unsigned","WIDTH0","=","10","WIDTH1","20","logic","[","][","]","a","1","+","b","_x",":","0","_y","-","3","5","endmodule"],"mappings":"AAAAA,AAAAC,sBAAOC,QAASC;IACZC,WAAcC,aAARC,OAAYC,EAAEC,EAAEL;IACtBC,WAAcC,aAARI,OAAYF,EAAEG,EAAEP;;IAEfQ,MAAKC,CAACJ,MAAEK,EAAEH,MAAEI,eAAfC;kBAA8BR,EAAES,CAACb;IAC9BQ,MAAKC,CAACN,OAAOW,EAAET,MAAEK,EAAEJ,UAAMK,EAA5BI;kBAA8BX,EAAES,CAACb;;IAE7BQ,MAAJQ;mBAAUZ,EAAEQ,CAACH,GAHJJ,QAGQM,CAACF,GAHLF,QAGSU,CAACC,EAAIJ,EAAED,CAACF,CAACX;IAC3BQ,MAAJW;mBAAUf,EAAEW,CAACN,GAHJN,OAAOW,EAAET,SAGAe,EAAEC,CAACV,CAACF,GAHAH,aAGKQ,EAAEQ,CAACL,CAACC,CAAGP,CAACX;AAC3CuB"} \ No newline at end of file +{"version":3,"file":"28_msblsb.sv.map","sources":["../../../veryl/28_msblsb.veryl"],"names":["","module","Module28","(","input","logic","[","30","][","40","]","c",")",";","localparam","int unsigned","WIDTH0","=","10","WIDTH1","20","a","1","+","b","_x",":","0","_y","-","3","5","_z","endmodule"],"mappings":"AAAAA,AAAAC,sBAAOC,SAASC;IACTC,MAAMC,MAAKC,CAACC,MAAEC,EAAEC,MAAEC,EAArBC,CAAsBX;AAC1BY,CAAEC;IACEC,WAAcC,aAARC,OAAYC,EAAEC,EAAEL;IACtBC,WAAcC,aAARI,OAAYF,EAAEG,EAAEP;;IAEfR,MAAKC,CAACY,MAAEV,EAAEY,MAAEV,eAAfW;kBAA8BJ,EAAEK,CAACT;IAC9BR,MAAKC,CAACU,OAAOO,EAAEL,MAAEV,EAAEW,UAAMT,EAA5Bc;kBAA8BP,EAAEK,CAACT;;IAE7BR,MAAJoB;mBAAUR,EAAEI,CAACf,GAHJY,QAGQR,CAACJ,GAHLc,QAGSM,CAACC,EAAIJ,EAAED,CAACZ,CAACG;IAC3BR,MAAJuB;mBAAUX,EAAEO,CAAClB,GAHJU,OAAOO,EAAEL,SAGAW,EAAEC,CAACpB,CAACJ,GAHAa,aAGKI,EAAEQ,CAACL,CAACC,CAAGjB,CAACG;IAC/BR,MAAJ2B;mBAAUf,EAAEN,CAACL,GAVFC,QAUMG,CAACJ,GAVHG,QAUOC,CAACG;AAC/BoB"} \ No newline at end of file diff --git a/testcases/sv/28_msblsb.sv b/testcases/sv/28_msblsb.sv index 3a6336bd..9a8d0758 100644 --- a/testcases/sv/28_msblsb.sv +++ b/testcases/sv/28_msblsb.sv @@ -1,4 +1,6 @@ -module veryl_testcase_Module28; +module veryl_testcase_Module28 ( + input logic [30-1:0][40-1:0] c +); localparam int unsigned WIDTH0 = 10; localparam int unsigned WIDTH1 = 20; @@ -11,5 +13,7 @@ module veryl_testcase_Module28; always_comb _x = a[((10) - 1)][((20) - 1):0 + 1]; logic _y; always_comb _y = b[((WIDTH0 + 10) - 1) - 3][((WIDTH1) - 1) + 5:0]; + logic _z; + always_comb _z = c[((30) - 1)][((40) - 1)]; endmodule //# sourceMappingURL=../map/testcases/sv/28_msblsb.sv.map diff --git a/testcases/veryl/28_msblsb.veryl b/testcases/veryl/28_msblsb.veryl index 1b4d24e4..50230e8b 100644 --- a/testcases/veryl/28_msblsb.veryl +++ b/testcases/veryl/28_msblsb.veryl @@ -1,4 +1,6 @@ -module Module28 { +module Module28 ( + c: input logic<30, 40>, +) { const WIDTH0: u32 = 10; const WIDTH1: u32 = 20; @@ -7,4 +9,5 @@ module Module28 { let _x: logic = a[msb][msb:lsb + 1]; let _y: logic = b[msb - 3][msb + 5:lsb]; + let _z: logic = c[msb][msb]; }