From e1187801771d0dbf414b13df6c857a05c772e455 Mon Sep 17 00:00:00 2001
From: dalance <dalance@gmail.com>
Date: Fri, 10 May 2024 10:23:08 +0900
Subject: [PATCH] Update README

---
 README.md | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/README.md b/README.md
index aa2d3e60..26c77daf 100644
--- a/README.md
+++ b/README.md
@@ -59,8 +59,8 @@ With these features, Veryl provides powerful support for designers to efficientl
 pub module Delay #( // visibility control by `pub` keyword
     param WIDTH: u32 = 1, // trailing comma is allowed
 ) (
-    i_clk : input logic       ,
-    i_rst : input logic       ,
+    i_clk : input clock       ,
+    i_rst : input reset       ,
     i_data: input logic<WIDTH>,
     o_data: input logic<WIDTH>,
 ) {