Test written in veryl has the module in the ifdef line

[wigwagwent]

The only example of using the test feature I could find in the documentation uses an embed(inline) to give a system verilog test. When I don't use the embed it does not generate right. I am using the 0.10.0 release.

The test I wrote base on the example. I did not look into how to use the assert if that works yet so it is commented out.

#[test(Test2)]
module Test2 {
    initial {
    	//assert (0) else $error("error");
    }
}

The generated results

`ifdef __veryl_test_test_bug_Test2__module test_bug_Test2;
    initial begin
        //assert (0) else $error("error");
    end
endmodule
`endif

It is putting the module statement in the ifdef line.

[dalance]

This bug will be fixed by #717.
But at the moment, Veryl aims logic description not verification.
So there is no support for verification description like assert.