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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
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<TD bgColor=#ffff66><B><FONT face=arial,sans-serif color=black
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<TD bgColor=#99ff99><B><FONT face=arial,sans-serif color=black
size=-1>65816 </FONT></B></TD></TR></TBODY></TABLE></TD></TR></TBODY></TABLE></TD></TR></TBODY></TABLE>
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<H2 align=center><FONT face="Arial, Helvetica, sans-serif" color=#000066
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<H2>A 6502 Programmer's Introduction to the <B
style="COLOR: black; BACKGROUND-COLOR: #99ff99">65816</B></H2>
<H3>by <B style="COLOR: black; BACKGROUND-COLOR: #ffff66">Brett </B><B
style="COLOR: black; BACKGROUND-COLOR: #a0ffff">Tabke</B></H3>
<P>After programming in 6502 language for over a decade, I was getting a bit
BORED. One can only code the same routines with the same opcodes so many times
before the nausea of repetition becomes overpowering. When I heard the news that
CMD was building a cartridge based on a 20 MHz <B
style="COLOR: black; BACKGROUND-COLOR: #99ff99">65816</B> I was overjoyed. For
years I've heard those with <B
style="COLOR: black; BACKGROUND-COLOR: #99ff99">65816</B> bases systems brag
about its capabilities. To us old 6502 programmers, the opportunity to program
the fabled <B style="COLOR: black; BACKGROUND-COLOR: #99ff99">65816</B> is a new
lease on life.
<P>The <B style="COLOR: black; BACKGROUND-COLOR: #99ff99">65816</B> is an
8-/16-bit register selectable upgrade to the 6502 series processor. With 24 bit
addressing of up to 16 Megabytes of RAM, the powerful <B
style="COLOR: black; BACKGROUND-COLOR: #99ff99">65816</B> is a logical upgrade
that leaves 6502 programmers feeling right at home. It is amazing how fast one
can adapt to the new processor. It sounds funny to say it, but the only
difficulty I have had learning the <B
style="COLOR: black; BACKGROUND-COLOR: #99ff99">65816</B> is that there are so
many options and choices to complete the same task, that it is hard to decide
which method is best.
<P>To get started programming the <B
style="COLOR: black; BACKGROUND-COLOR: #99ff99">65816</B>, I would recommend
purchasing the book, "Programming the <B
style="COLOR: black; BACKGROUND-COLOR: #99ff99">65816</B>" from The Western
Design Center, manufacturer of the <B
style="COLOR: black; BACKGROUND-COLOR: #99ff99">65816</B>. While it is a bit
pricey, the sheer quality and content of the 600 page book is worth the money.
Rarely, if ever, has there been a CPU manual as thorough and detailed as the
Western Design book. If you know 6502 assembly, then Programming the <B
style="COLOR: black; BACKGROUND-COLOR: #99ff99">65816</B> is probably the only
<B style="COLOR: black; BACKGROUND-COLOR: #99ff99">65816</B> book you will ever
need.
<H4>Getting a Feel for the Modes</H4>
<P>The <B style="COLOR: black; BACKGROUND-COLOR: #99ff99">65816</B> may be
operated in Native mode or 6502 Emulation mode. Emulation mode is a 100% 6502
compatible mode where the whole processor looks and feels like a vintage 6502.
Native mode offers 8- or 16-bit user registers and full access to 24-bit
addressing.
<P>While in emulation mode, not only are all the 6502 opcodes present in their
virgin form, but the new <B
style="COLOR: black; BACKGROUND-COLOR: #99ff99">65816</B> instructions are also
available for usage. In fact, the first lesson to learn about programming the <B
style="COLOR: black; BACKGROUND-COLOR: #99ff99">65816</B> is that emulation mode
is much more powerful than a stock 6502. The only true difference between
emulation mode and our venerable C64's 6510 processor is that unimplemented
opcodes will not produce the results expected on the former. Since all 256 of
the potential opcodes are now implemented on the <B
style="COLOR: black; BACKGROUND-COLOR: #99ff99">65816</B>, older C64 software
that uses previously unimplemented opcodes will produce erratic results.
<P>To select between emulation and native modes, a new phantom hidden emulation
bit (E) was added to the status register. Shown in programming models hanging on
top of the Carry bit, the emulation bit is only accessible by one instruction.
The new instruction (XCE) exchanges the status of the Carry bit and Emulation
bit. To move to emulation mode, set the carry and issue an XCE instruction. To
move to native mode, clear the carry and issue the XCE instruction.
<H4>My, How Your Index Registers Have Grown!</H4>While in native mode there are
two new directly accessible bits present in the status register. The <B
style="COLOR: black; BACKGROUND-COLOR: #99ff99">65816</B> implements new
hardware interrupt vectors which include a new hardware BRK vector in ROM;
therefore, the old BRK bit of the status register is no longer needed. The BRK
bit is replaced with the X bit to select either 8- or 16-bit index registers.
The former empty bit 5 is now filled with the M bit to specify the accumulator
and memory access as 8- or 16-bit.
<P>Two new instructions are used to clear or set bits within the status
register. The SEP instruction sets bits, and REP clears bits. SEP and REP use a
one byte immediate addressing mode operand to specify which bits are to be set
or cleared. For example, to set the X bit for 8 bit user registers: <BR><BR>
<TABLE border=0>
<TBODY>
<TR>
<TD>SEP #%00010000
<TD>; set bit 4 for 8-bit index
<TR>
<TD>
<TD>; registers. </TR></TBODY></TABLE><BR><BR>Or to clear bit 4:
<TABLE border=0>
<TBODY>
<TR>
<TD>REP #%00010000
<TD>; clear bit 4 for 16-bit index
<TR>
<TD>
<TD>; registers. </TR></TBODY></TABLE><BR><BR>
<P>When in 8 bit mode, the index registers perform their function in standard
6502 form. When status bit X is set to 0, both the X and Y index registers
become 16 bits wide. With a 16-bit index register you can now reach out to a
full 64K with the various indexed addressing modes. An absolute load to an index
register in 16-bit mode will retrieve 2 bytes of memory-the one at the effective
address and the one at the effective address plus one. Simple things like INX or
DEY work on a full 16 bit, which means you no longer have to specify a memory
location for various counters, and loops based on index counters can now be
coded in a more efficient manner.
<P>The formerly empty status register bit 5 is now referred to as bit M. M is
used to specify an 8- or 16-bit wide acculmulator and memory accesses. When in 8
bit mode, (M=1), the high order 8 bits are still accessible by exchanging the
low and high bytes with a XBA instruction-it is like having two acculmulators!
However; when set for a full 16-bit wide accumulator, all math and accumulator
oriented logical intructions operate on all 16 bits! If you add up the clock
cycles and bytes required to perform a standard two byte addition, you can start
to see the true power of 16-bit registers.
<H4>More Register Improvements</H4>
<P>Zero Page has now been renamed to Direct Page-corporate thinking, go figure.
A new processor register D was added to allow Direct Page to be moved anywhere
within the first 64K of memory. The direct page register is 16 bits wide, so you
can now specify the start of direct page at any byte. Several old instructions
now include direct page addressing as well. To move direct page, just push the
new value onto the stack (16 bits) and then PLD to pull it into the direct page
register. You may also transfer the value from the 16-bit accumulator to the
direct page register with the TCD instruction. Direct page may also be moved
while in emulation mode.
<P>While in native mode, the stack pointer is a full 16 bits wide, which means
the stack is no longer limited to just 256 bytes. It can be moved anywhere
within the first 64K of memory (although while in emulation mode, the stack is
located at page one). There are several new addressing modes that can use the
stack pointer as a quasi-index register to access memory. Numerous new push and
pull instructions allow you to manipulate the stack. A few of the more useful
stack intructions useful to programmers, are the new instructions to push &
pull index registers with PHX/PHY and PLX/PLY.
<P>Two other new processors registers are the Program Bank Register (PBR) and
the Data Bank Register (DBR). The Program Bank Register can be thought of as
extending the program counter out to 24 bits. Although you can JSR and JMP to
routines located in other RAM banks, individual routines on the <B
style="COLOR: black; BACKGROUND-COLOR: #99ff99">65816</B> still must run within
a single bank of 64K-there's no automatic rollover from one bank of RAM to the
next when executing successive instructions. In this sense, it may help to think
of the <B style="COLOR: black; BACKGROUND-COLOR: #99ff99">65816</B> processor as
a marriage of Commodore's C128 Memory Management Unit (MMU) and an 'enhanced'
6502-a very similar concept.
<P>The Data Bank Register is used to reach out to any address within the 16
megabyte address space of the <B
style="COLOR: black; BACKGROUND-COLOR: #99ff99">65816</B>. When any of the
addressing modes that specify a 16-bit address are used, the Data Bank byte is
appended to the instruction address. This allows access to all 16 megabytes
without having to resort to 24-bit addressing instruction, and helps enable code
that can operate from any bank.
<H4>New Addressing Modes</H4>There are new addressing modes on the <B
style="COLOR: black; BACKGROUND-COLOR: #99ff99">65816</B>. Several new
instructions are designed to help relocatable code that can execute at any
address. The use of relocatable code on the 6502 was extremely limited. With 16
megabytes of address space, writing relocatable code increases the overall
utility of the program. To write relocatable code, several new instructions use
Program Counter Relative Long addressing. This allows relative branching within
a 64K bank of RAM. There's also Stack Relative addressing, and a push
instruction to place the program counter onto the stack, so that a code fragment
can pull it back off and can instantly know its execution address.
<P>Another new feature are two Block Move instructions, one for forward MVP and
one for backward MVN. Simply load the 16-bit X register with the starting
address, the Y index register with the ending address, the accumulator with the
number of bytes to move, and issue the MVP or MVN instructions. MVN is for move
negative, and MVP is for move positive, so that your moves don't overwrite
themselves. Block Moves use two operand bytes: one for the source bank of 64K
and one for the destination bank. Memory is moved at the rate of seven clock
cycles per byte.
<P>Several new addressing modes are used to access the full address space. A <B
style="COLOR: black; BACKGROUND-COLOR: #99ff99">65816</B> assembler would decode
"long" addressing given this input: <BR><BR>
<TABLE border=0>
<TBODY>
<TR>
<TD>LDA $0445F2
<TD>; load byte from $45F2 of RAM
<TR>
<TD>
<TD>; bank 4 </TR></TBODY></TABLE>
<TABLE border=0>
<TBODY>
<TR>
<TD>LDA $03412F,x
<TD>; load byte from $412F of bank 3
<TR>
<TD>
<TD>; plus x. </TR></TBODY></TABLE><BR>Quite a few instructions have been given
new addressing modes. How many times have you wanted to do this: <BR>
<TABLE border=0>
<TBODY>
<TR>
<TD>LDA ($12)
<TD>; load indirect without an
<TR>
<TD>
<TD>; offset. </TR></TBODY></TABLE><BR><BR>Or how about a table of routine
addresses: <BR>
<TABLE border=0>
<TBODY>
<TR>
<TD>JSR ($1234,x)
<TD>; jump to a subroutine via
<TR>
<TD>
<TD>; indexed indirect addressing! </TR></TBODY></TABLE><BR><BR>Other fun new
instructions: <BR>
<TABLE border=0>
<TBODY>
<TR>
<TD>TXY,TYX
<TD>Transfer directly between index registers
<TR>
<TD>BRA
<TD>Branch always regardless of status bits
<TR>
<TD>TSB
<TD>Test and set any bit of a byte
<TR>
<TD>TRB
<TD>Test and reset (clear) any bit of a byte
<TR>
<TD>INC A/DEC A
<TD>Increment or decrement the accumulator directly
<TR>
<TD>STZ
<TD>Store a zero to any byte </TR></TBODY></TABLE>
<H4>Summing Up</H4>As you can see, the <B
style="COLOR: black; BACKGROUND-COLOR: #99ff99">65816</B> opens up a whole new
world of programming-it feels like a new lease on life. Of course, it's going to
take some time to learn the new processor. But while the 20 MHz speed is a nice
perk, I believe that the real power of CMD's new peripheral is indeed the engine
under its hood: the <B
style="COLOR: black; BACKGROUND-COLOR: #99ff99">65816</B>-a <I>super</I> CPU!
<BR><BR>
<CENTER><IMG src=""> <BR><IMG src=""> <BR><FONT size=3><STRONG>Native Mode
Options</STRONG></FONT></CENTER><BR><FONT size=1>While in Native Mode, the m
flag controls the size of Accumulator A and most Memory Operations, while the x
flag controls the size of the X and Y Index Registers. This provides 4 different
configuration possibilities, as charted below. The REP and SEP instructions are
used in combination to swith configurations. <BR>
<CENTER>
<TABLE border=0>
<TBODY>
<TR>
<TH><FONT size=1>m</FONT>
<TH><FONT size=1>x</FONT>
<TH><FONT size=1>A/M</FONT>
<TH><FONT size=1>X/Y</FONT>
<TH><FONT size=1>Instructions</FONT>
<TR>
<TH><FONT size=1>0</FONT>
<TH><FONT size=1>0</FONT>
<TH><FONT size=1>15-bit</FONT>
<TH><FONT size=1>16-bit</FONT>
<TH><FONT size=1>REP #$30</FONT>
<TR>
<TH><FONT size=1>0</FONT>
<TH><FONT size=1>1</FONT>
<TH><FONT size=1>16-bit</FONT>
<TH><FONT size=1>8-bit</FONT>
<TH><FONT size=1>REP #$20</FONT>
<TR>
<TH>
<TH>
<TH>
<TH>
<TH><FONT size=1>SEP #$10</FONT>
<TR>
<TH><FONT size=1>1</FONT>
<TH><FONT size=1>0</FONT>
<TH><FONT size=1>8-bit</FONT>
<TH><FONT size=1>16-bit</FONT>
<TH><FONT size=1>REP #$10</FONT>
<TR>
<TH>
<TH>
<TH>
<TH>
<TH><FONT size=1>SEP #$20</FONT>
<TR>
<TH><FONT size=1>1</FONT>
<TH><FONT size=1>1</FONT>
<TH><FONT size=1>8-bit</FONT>
<TH><FONT size=1>8-bit</FONT>
<TH><FONT size=1>SEP #$30</FONT> </TR></TBODY></TABLE></CENTER><BR>It is
important to note that the m flag will control the size of all operations
dealing with memory except in operations involving the X and Y Index Registers
(CPX, CPY, LDX, LDY, STX and STY) when the x flag controls the size. <BR><BR>
<CENTER><IMG src=""> <BR><IMG src=""><BR><FONT size=3><STRONG>Emulation
Notes</STRONG></FONT></CENTER><BR><FONT size=1>While in Emulation Mode,
Accumulator A is forced to 8-bit mode. You can, however, access the upper 8 bits
with instructions that specify Accumulator B, and all 16 bits at once with
instructions that specify Accumulator C. The X and Y Index Registers are also
forced to 8-bit mode, with no means available to access the upper 8 bits. To
further assist in compatibility, the Stack is forced to Page 1 of Bank 0. The
Direct page Register (D) is fully functional in this mode, allowing direct page
to be placed anywhere in Bank 0. Likewise, the Program Bank Register (PBR) and
Data Bank Register (DBR) are also fully functional. While it would seem that
these latter items would allow programs to operate from any bank in Emulation
mode, there are some caveats; interrups will force the program bank to zero
without saving the PBR first, and RTI won't attempt to restore the bank.
Therefore, Native mode would be recommended to execute programs in other banks.
<BR><BR>
<CENTER>
<H3>Guide to 6502/65C02/<B
style="COLOR: black; BACKGROUND-COLOR: #99ff99">65816</B> Instructions</H3>|<A
href="http://www.westerndesigncenter.com/65816.html#a"> a </A>| |<A
href="http://www.westerndesigncenter.com/65816.html#b"> b </A>| |<A
href="http://www.westerndesigncenter.com/65816.html#c"> c </A>| |<A
href="http://www.westerndesigncenter.com/65816.html#d"> d </A>| |<A
href="http://www.westerndesigncenter.com/65816.html#e"> e </A>| |<A
href="http://www.westerndesigncenter.com/65816.html#i"> i </A>| |<A
href="http://www.westerndesigncenter.com/65816.html#j"> j </A>| |<A
href="http://www.westerndesigncenter.com/65816.html#l"> l </A>| |<A
href="http://www.westerndesigncenter.com/65816.html#m"> m </A>| |<A
href="http://www.westerndesigncenter.com/65816.html#n"> n </A>| |<A
href="http://www.westerndesigncenter.com/65816.html#o"> o </A>| |<A
href="http://www.westerndesigncenter.com/65816.html#p"> p </A>| |<A
href="http://www.westerndesigncenter.com/65816.html#r"> r </A>| |<A
href="http://www.westerndesigncenter.com/65816.html#s"> s </A>| |<A
href="http://www.westerndesigncenter.com/65816.html#t"> t </A>| |<A
href="http://www.westerndesigncenter.com/65816.html#w"> w </A>| |<A
href="http://www.westerndesigncenter.com/65816.html#x"> x </A>| </CENTER><BR>
<TABLE border=1>
<TBODY>
<TR>
<TH width="30%">Assembler Example
<TH>HEX
<TH width="45%">Addressing Mode
<TH>02
<TH>C02
<TH>816
<TH>Bytes
<TH>Cycles
<TR>
<TD colSpan=8><A name=a><B>ADC</B> <I>Add With Carry</I> [Flags affected:
n,v,z,c] </A>
<TR>
<TD>
<DD>ADC (<I>dp</I>,X)</DD>
<TD align=middle>61
<TD>DP Indexed Indirect,X
<TD align=middle>x
<TD align=middle>x
<TD align=middle>x
<TD align=middle>2
<TD>6<SUP><FONT size=1>1,2,4</SUP></FONT>
<TR>
<TD>
<DD>ADC <I>sr</I>,S</DD>
<TD align=middle>63
<TD>Stack Relative
<TD align=middle>
<TD align=middle>
<TD align=middle>x
<TD align=middle>2
<TD>4<SUP><FONT size=1>1,4</SUP></FONT>
<TR>
<TD>
<DD>ADC <I>dp</I></DD>
<TD align=middle>65
<TD>Direct Page
<TD align=middle>x
<TD align=middle>x
<TD align=middle>x
<TD align=middle>2
<TD>3<SUP><FONT size=1>1,2,4</SUP></FONT>
<TR>
<TD>
<DD>ADC [<I>dp</I>]</DD>
<TD align=middle>67
<TD>DP Indirect Long
<TD align=middle>
<TD align=middle>
<TD align=middle>x
<TD align=middle>2
<TD>6<SUP><FONT size=1>1,2,4</SUP></FONT>
<TR>
<TD>
<DD>ADC <I>#const</I></DD>
<TD align=middle>69
<TD>Immediate
<TD align=middle>x
<TD align=middle>x
<TD align=middle>x
<TD align=middle>2<SUP><FONT size=1>17</SUP></FONT>
<TD>2<SUP><FONT size=1>1,4</SUP></FONT>
<TR>
<TD>
<DD>ADC <I>addr</I></DD>
<TD align=middle>6D
<TD>Absolute
<TD align=middle>x
<TD align=middle>x
<TD align=middle>x
<TD align=middle>3
<TD>4<SUP><FONT size=1>1,4</SUP></FONT>
<TR>
<TD>
<DD>ADC <I>long</I></DD>
<TD align=middle>6F
<TD>Absolute Long
<TD align=middle>
<TD align=middle>
<TD align=middle>x
<TD align=middle>4
<TD>5<SUP><FONT size=1>1,4</SUP></FONT>
<TR>
<TD>
<DD>ADC ( <I>dp</I>),Y</DD>
<TD align=middle>71
<TD>DP Indirect Indexed, Y
<TD align=middle>x
<TD align=middle>x
<TD align=middle>x
<TD align=middle>2
<TD>5<SUP><FONT size=1>1,2,3,4</SUP></FONT>
<TR>
<TD>
<DD>ADC (<I>dp</I>)</DD>
<TD align=middle>72
<TD>DP Indirect
<TD align=middle>
<TD align=middle>x
<TD align=middle>x
<TD align=middle>2
<TD>5<SUP><FONT size=1>1,2,4</SUP></FONT>
<TR>
<TD>
<DD>ADC (<I>sr</I>,S),Y</DD>
<TD align=middle>73
<TD>SR Indirect Indexed,Y
<TD align=middle>
<TD align=middle>
<TD align=middle>x
<TD align=middle>2
<TD>7<SUP><FONT size=1>1,4</SUP></FONT>
<TR>
<TD>
<DD>ADC <I>dp</I>,X</DD>
<TD align=middle>75
<TD>DP Indexed,X
<TD align=middle>x
<TD align=middle>x
<TD align=middle>x
<TD align=middle>2
<TD>4<SUP><FONT size=1>1,2,4</SUP></FONT>
<TR>
<TD>
<DD>ADC [<I>dp</I>],Y</DD>
<TD align=middle>77
<TD>DP Indirect Long Indexed, Y
<TD align=middle>
<TD align=middle>
<TD align=middle>x
<TD align=middle>2
<TD>6<SUP><FONT size=1>1,2,4</SUP></FONT>
<TR>
<TD>
<DD>ADC <I>addr</I>,Y</DD>
<TD align=middle>79
<TD>Absolute Indexed,Y
<TD align=middle>x
<TD align=middle>x
<TD align=middle>x
<TD align=middle>3
<TD>4<SUP><FONT size=1>1,3,4</SUP></FONT>
<TR>
<TD>
<DD>ADC <I>addr</I>,X</DD>
<TD align=middle>7D
<TD>Absolute Indexed,X
<TD align=middle>x
<TD align=middle>x
<TD align=middle>x
<TD align=middle>3
<TD>4<SUP><FONT size=1>1,3,4</SUP></FONT>
<TR>
<TD>
<DD>ADC <I>long</I>,X</DD>
<TD align=middle>7F
<TD>Absolute Long Indexed,X
<TD align=middle>
<TD align=middle>
<TD align=middle>x
<TD align=middle>4
<TD>5<SUP><FONT size=1>1,4</SUP></FONT>
<TR>
<TD colSpan=8><B>AND</B> <I>AND Accumulator With Memory</I> [Flags
affected: n,z]
<TR>
<TD>
<DD>AND (<I>dp,</I>X)</DD>
<TD align=middle>21
<TD>DP Indexed Indirect,X
<TD align=middle>x
<TD align=middle>x
<TD align=middle>x
<TD align=middle>2
<TD>6<SUP><FONT size=1>1,2</SUP></FONT>
<TR>
<TD>
<DD>AND <I>sr,S</I></DD>
<TD align=middle>23
<TD>Stack Relative
<TD align=middle>
<TD align=middle>
<TD align=middle>x
<TD align=middle>2
<TD>4<SUP><FONT size=1>1</SUP></FONT>
<TR>
<TD>
<DD>AND <I>dp</I></DD>
<TD align=middle>25
<TD>Direct Page
<TD align=middle>x
<TD align=middle>x
<TD align=middle>x
<TD align=middle>2
<TD>3<SUP><FONT size=1>1,2</SUP></FONT>
<TR>
<TD>
<DD>AND [<I>dp</I>]</DD>
<TD align=middle>27
<TD>DP Indirect Long
<TD align=middle>
<TD align=middle>
<TD align=middle>x
<TD align=middle>2
<TD>6<SUP><FONT size=1>1,2</SUP></FONT>
<TR>
<TD>
<DD>AND <I>#const</I></DD>
<TD align=middle>29
<TD>Immediate
<TD align=middle>x
<TD align=middle>x
<TD align=middle>x
<TD align=middle>2<SUP><FONT size=1>17</SUP></FONT>
<TD>2<SUP><FONT size=1>1</SUP></FONT>
<TR>
<TD>
<DD>AND <I>addr</I></DD>
<TD align=middle>2D
<TD>Absolute
<TD align=middle>x
<TD align=middle>x
<TD align=middle>x
<TD align=middle>3
<TD>4<SUP><FONT size=1>1</SUP></FONT>
<TR>
<TD>
<DD>AND <I>long</I></DD>
<TD align=middle>2F
<TD>Absolute Long
<TD align=middle>
<TD align=middle>
<TD align=middle>x
<TD align=middle>4
<TD>5<SUP><FONT size=1>1</SUP></FONT>
<TR>
<TD>
<DD>AND (<I>dp</I>),Y</DD>
<TD align=middle>31
<TD>DP Indirect Indexed, Y
<TD align=middle>x
<TD align=middle>x
<TD align=middle>x
<TD align=middle>2
<TD>5<SUP><FONT size=1>1,2,3</SUP></FONT>
<TR>
<TD>
<DD>AND (<I>dp</I>)</DD>
<TD align=middle>32
<TD>DP Indirect
<TD align=middle>
<TD align=middle>x
<TD align=middle>x
<TD align=middle>2
<TD>5<SUP><FONT size=1>1,2</SUP></FONT>
<TR>
<TD>
<DD>AND (<I>sr</I>,S),Y</DD>
<TD align=middle>33
<TD>SR Indirect Indexed,Y
<TD align=middle>
<TD align=middle>
<TD align=middle>x
<TD align=middle>2
<TD>7<SUP><FONT size=1>1</SUP></FONT>
<TR>
<TD>
<DD>AND <I>dp</I>,X</DD>
<TD align=middle>35
<TD>DP Indexed,X
<TD align=middle>x
<TD align=middle>x
<TD align=middle>x
<TD align=middle>2
<TD>4<SUP><FONT size=1>1,2</SUP></FONT>
<TR>
<TD>
<DD>AND [<I>dp</I>],Y</DD>
<TD align=middle>37
<TD>DP Indirect Long Indexed, Y
<TD align=middle>
<TD align=middle>
<TD align=middle>x
<TD align=middle>2
<TD>6<SUP><FONT size=1>1,2</SUP></FONT>
<TR>
<TD>
<DD>AND <I>addr</I>,Y</DD>
<TD align=middle>39
<TD>Absolute Indexed,Y
<TD align=middle>x
<TD align=middle>x
<TD align=middle>x
<TD align=middle>3
<TD>4<SUP><FONT size=1>1,3</SUP></FONT>
<TR>
<TD>
<DD>AND <I>addr</I>,X</DD>
<TD align=middle>3D
<TD>Absolute Indexed,X
<TD align=middle>x
<TD align=middle>x
<TD align=middle>x
<TD align=middle>3
<TD>4<SUP><FONT size=1>1,3</SUP></FONT>
<TR>
<TD>
<DD>AND <I>long</I>,X</DD>
<TD align=middle>3F
<TD>Absolute Long Indexed,X
<TD align=middle>
<TD align=middle>
<TD align=middle>x
<TD align=middle>4
<TD>5<SUP><FONT size=1>1</SUP></FONT>
<TR>
<TD colSpan=8><B>ASL</B> <I>Accumulator or Memory Shift Left</I> [Flags
affected: n,z,c]
<TR>
<TD>
<DD>ASL <I>dp</I></DD>
<TD align=middle>06
<TD>Direct Page
<TD align=middle>x
<TD align=middle>x
<TD align=middle>x
<TD align=middle>2
<TD>5<SUP><FONT size=1>2,5</SUP></FONT>
<TR>
<TD>
<DD>ASL A <I></I></DD>
<TD align=middle>0A
<TD>Accumulator
<TD align=middle>x
<TD align=middle>x
<TD align=middle>x
<TD align=middle>1
<TD>2<SUP><FONT size=1></SUP></FONT>
<TR>
<TD>
<DD>ASL <I>addr</I></DD>
<TD align=middle>0E
<TD>Absolute
<TD align=middle>x
<TD align=middle>x
<TD align=middle>x
<TD align=middle>3
<TD>6<SUP><FONT size=1>5</SUP></FONT>
<TR>
<TD>
<DD>ASL <I>dp</I>,X</DD>
<TD align=middle>16
<TD>DP Indexed,X
<TD align=middle>x
<TD align=middle>x
<TD align=middle>x
<TD align=middle>2
<TD>6<SUP><FONT size=1>2,5</SUP></FONT>
<TR>
<TD>
<DD>ASL <I>addr</I>,X</DD>
<TD align=middle>1E
<TD>Absolute Indexed,X
<TD align=middle>x
<TD align=middle>x
<TD align=middle>x
<TD align=middle>3
<TD>7<SUP><FONT size=1>5,6</SUP></FONT>
<TR>
<TD colSpan=8><A name=b><B>BCC</B> <I>Branch if Carry Clear</I> [Flags
affected: none][Alias: BLT] </A>
<TR>
<TD>
<DD>BCC <I>nearlabel</I></DD>
<TD align=middle>90
<TD>Program Counter Relative
<TD align=middle>x
<TD align=middle>x
<TD align=middle>x
<TD align=middle>2
<TD>2<SUP><FONT size=1>7,8</SUP></FONT>
<TR>
<TD colSpan=8><B>BCS</B> <I>Branch if Carry Set</I> [Flags affected:
none][Alias: BGE]
<TR>
<TD>
<DD>BCS <I>nearlabel</I></DD>
<TD align=middle>B0
<TD>Program Counter Relative
<TD align=middle>x
<TD align=middle>x
<TD align=middle>x
<TD align=middle>2
<TD>2<SUP><FONT size=1>7,8</SUP></FONT>
<TR>
<TD colSpan=8><B>BEQ</B> <I>Branch if Equal</I> [Flags affected: none]
<TR>
<TD>
<DD>BEQ <I>nearlabel</I></DD>
<TD align=middle>F0
<TD>Program Counter Relative
<TD align=middle>x
<TD align=middle>x
<TD align=middle>x
<TD align=middle>2
<TD>2<SUP><FONT size=1>7,8</SUP></FONT>
<TR>
<TD colSpan=8><B>BIT</B> <I>Test Bits</I> [Flags affected: z (immediate
mode) n,v,z (non-immediate modes)]
<TR>
<TD>
<DD>BIT <I>dp</I></DD>
<TD align=middle>24
<TD>Direct Page
<TD align=middle>x
<TD align=middle>x
<TD align=middle>x
<TD align=middle>2
<TD>3<SUP><FONT size=1>1,2</SUP></FONT>
<TR>
<TD>
<DD>BIT <I>addr</I></DD>
<TD align=middle>2C
<TD>Absolute
<TD align=middle>x
<TD align=middle>x
<TD align=middle>x
<TD align=middle>3
<TD>4<SUP><FONT size=1>1</SUP></FONT>
<TR>
<TD>
<DD>BIT <I>dp</I>,X</DD>
<TD align=middle>34
<TD>DP Indexed,X
<TD align=middle>
<TD align=middle>x
<TD align=middle>x
<TD align=middle>2
<TD>4<SUP><FONT size=1>1,2</SUP></FONT>
<TR>
<TD>
<DD>BIT <I>addr</I>,X</DD>
<TD align=middle>3C
<TD>Absolute Indexed,X
<TD align=middle>
<TD align=middle>x
<TD align=middle>x
<TD align=middle>3
<TD>4<SUP><FONT size=1>1,3</SUP></FONT>
<TR>
<TD>
<DD>BIT <I>#const</I></DD>
<TD align=middle>89
<TD>Immediate
<TD align=middle>
<TD align=middle>x
<TD align=middle>x
<TD align=middle>2<SUP><FONT size=1>17</SUP></FONT>
<TD>2<SUP><FONT size=1>1</SUP></FONT>
<TR>
<TD colSpan=8><B>BMI</B> <I>Branch if Minus</I> [Flags affected: none]
<TR>
<TD>
<DD>BMI <I>nearlabel</I></DD>
<TD align=middle>30
<TD>Program Counter Relative
<TD align=middle>x
<TD align=middle>x
<TD align=middle>x
<TD align=middle>2
<TD>2<SUP><FONT size=1>7,8</SUP></FONT>
<TR>
<TD colSpan=8><B>BNE</B> <I>Branch if Not Equal</I> [Flags affected: none]
<TR>
<TD>
<DD>BNE <I>nearlabel</I></DD>
<TD align=middle>D0
<TD>Program Counter Relative
<TD align=middle>x
<TD align=middle>x
<TD align=middle>x
<TD align=middle>2
<TD>2<SUP><FONT size=1>7,8</SUP></FONT>
<TR>
<TD colSpan=8><B>BPL</B> <I>Branch if Plus</I> [Flags affected: none]
<TR>
<TD>
<DD>BPL <I>nearlabel</I></DD>
<TD align=middle>10
<TD>Program Counter Relative
<TD align=middle>x
<TD align=middle>x
<TD align=middle>x
<TD align=middle>2
<TD>2<SUP><FONT size=1>7,8</SUP></FONT>
<TR>
<TD colSpan=8><B>BRA</B> <I>Branch Always</I> [Flags affected: none]
<TR>
<TD>
<DD>BRA <I>nearlabel</I></DD>
<TD align=middle>80
<TD>Program Counter Relative
<TD align=middle>
<TD align=middle>x
<TD align=middle>x
<TD align=middle>2
<TD>3<SUP><FONT size=1>8</SUP></FONT>
<TR>
<TD colSpan=8><B>BRK</B> <I>Break</I> [Flags affected: b,i (6502) b,d,i
(65C02/<B style="COLOR: black; BACKGROUND-COLOR: #99ff99">65816</B>
Emulation) d,i (<B
style="COLOR: black; BACKGROUND-COLOR: #99ff99">65816</B> Native)]
<TR>
<TD>
<DD>BRK <I></I></DD>
<TD align=middle>00
<TD>Stack/Interrupt
<TD align=middle>x
<TD align=middle>x
<TD align=middle>x
<TD align=middle>2 <SUP><FONT size=1>18</SUP></FONT>
<TD>7<SUP><FONT size=1>9</SUP></FONT>
<TR>
<TD colSpan=8><B>BRL</B> <I>Branch Long Always</I> [Flags affected: none]
<TR>
<TD>
<DD>BRL <I>label</I></DD>
<TD align=middle>82
<TD>Program Counter Relative Long
<TD align=middle>
<TD align=middle>
<TD align=middle>x
<TD align=middle>3
<TD>4<SUP><FONT size=1></SUP></FONT>
<TR>
<TD colSpan=8><B>BVC</B> <I>Branch if Overflow Clear</I> [Flags affected:
none]
<TR>
<TD>
<DD>BVC <I>nearlabel</I></DD>
<TD align=middle>50
<TD>Program Counter Relative
<TD align=middle>x
<TD align=middle>x
<TD align=middle>x
<TD align=middle>2
<TD>2<SUP><FONT size=1>7,8</SUP></FONT>
<TR>
<TD colSpan=8><B>BVS</B> <I>Branch if Overflow Set</I> [Flags affected:
none]
<TR>
<TD>
<DD>BVS <I>nearlabel</I></DD>
<TD align=middle>70
<TD>Program Counter Relative
<TD align=middle>x
<TD align=middle>x
<TD align=middle>x
<TD align=middle>2
<TD>2<SUP><FONT size=1>7,8</SUP></FONT>
<TR>
<TD colSpan=8><A name=c><B>CLC</B> <I>Clear Carry</I> [Flags affected: c]
</A>
<TR>
<TD>
<DD>CLC <I></I></DD>
<TD align=middle>18
<TD>Implied
<TD align=middle>x
<TD align=middle>x
<TD align=middle>x
<TD align=middle>1
<TD>2<SUP><FONT size=1></SUP></FONT>
<TR>
<TD colSpan=8><B>CLD</B> <I>Clear Decimal Mode Flag</I> [Flags affected:
d]
<TR>
<TD>
<DD>CLD <I></I></DD>
<TD align=middle>D8
<TD>Implied
<TD align=middle>x
<TD align=middle>x
<TD align=middle>x
<TD align=middle>1
<TD>2<SUP><FONT size=1></SUP></FONT>
<TR>
<TD colSpan=8><B>CLI</B> <I>Clear Interrupt Disable Flag</I> [Flags
affected: i]
<TR>
<TD>
<DD>CLI <I></I></DD>
<TD align=middle>58
<TD>Implied
<TD align=middle>x
<TD align=middle>x
<TD align=middle>x
<TD align=middle>1
<TD>2<SUP><FONT size=1></SUP></FONT>
<TR>
<TD colSpan=8><B>CLV</B> <I>Clear Overflow Flag</I> [Flags affected: v]
<TR>
<TD>
<DD>CLV <I></I></DD>
<TD align=middle>B8
<TD>Implied
<TD align=middle>x
<TD align=middle>x
<TD align=middle>x
<TD align=middle>1
<TD>2<SUP><FONT size=1></SUP></FONT>
<TR>