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  1. self_projects self_projects Public

  2. Design-of-Dual-Clock-Asynchronous-FIFO Design-of-Dual-Clock-Asynchronous-FIFO Public

    Self Project

    Verilog

  3. ASIC-Design-and-FPGA-Implementation-of-LMS-Filter ASIC-Design-and-FPGA-Implementation-of-LMS-Filter Public

  4. Implementation-of-6-Stage-Pipelined-RISC-Processor Implementation-of-6-Stage-Pipelined-RISC-Processor Public

    Verilog

  5. Multi-Cycle-Carpinelli-s-Very-Simple-CPU-VSCPU- Multi-Cycle-Carpinelli-s-Very-Simple-CPU-VSCPU- Public

  6. my_resume my_resume Public