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@HEP-SoC

HEP-SoC

  • Switzerland

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  1. SoCMake SoCMake Public

    CMake based hardware build system

    CMake 4 2

  2. riscv-dbg riscv-dbg Public

    Forked from pulp-platform/riscv-dbg

    RISC-V Debug Support for our PULP RISC-V Cores

    SystemVerilog

  3. common_cells common_cells Public

    Forked from pulp-platform/common_cells

    Common SystemVerilog components

    SystemVerilog

  4. tech_cells_generic tech_cells_generic Public

    Forked from pulp-platform/tech_cells_generic

    Technology dependent cells instantiated in the design for generic process (simulation, FPGA)

    SystemVerilog

  5. pulpissimo pulpissimo Public

    Forked from pulp-platform/pulpissimo

    This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.

    SystemVerilog

  6. PeakRDL-regblock PeakRDL-regblock Public

    Forked from SystemRDL/PeakRDL-regblock

    Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

    Python

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