Merge branch 'espressif:master' into master

LLotme · Aug 7, 2024 · 9397a61 · 9397a61
2 parents 6fc3308 + 8e4454b
commit 9397a61
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diff --git a/.gitlab/ci/danger.yml b/.gitlab/ci/danger.yml
@@ -1,4 +1,4 @@
-# Extenal DangerJS
+# External DangerJS
 include:
   - project: espressif/shared-ci-dangerjs
     ref: master
@@ -10,7 +10,6 @@ run-danger-mr-linter:
     GIT_STRATEGY: none # no repo checkout
     ENABLE_CHECK_AREA_LABELS: 'true'
     ENABLE_CHECK_DOCS_TRANSLATION: 'true'
-    ENABLE_CHECK_RELEASE_NOTES_DESCRIPTION: 'true'
     ENABLE_CHECK_UPDATED_CHANGELOG: 'false'
   before_script: []
   cache: []

diff --git a/.gitlab/ci/host-test.yml b/.gitlab/ci/host-test.yml
@@ -385,7 +385,6 @@ test_pytest_macos:
       --ignore-result-files ${KNOWN_FAILURE_CASES_FILE_NAME}
       --app-info-filepattern \"list_job_*.txt\"
 
-
 test_idf_pytest_plugin:
   extends:
     - .host_test_template
@@ -400,3 +399,8 @@ test_idf_pytest_plugin:
     - python -m unittest test_report_generator.py
     - cd ${IDF_PATH}/tools/ci/idf_pytest
     - pytest --junitxml=${CI_PROJECT_DIR}/XUNIT_RESULT.xml
+
+test_idf_build_apps_load_soc_caps:
+  extends: .host_test_template
+  script:
+    - python tools/ci/check_soc_headers_load_in_idf_build_apps.py
diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml
@@ -241,6 +241,6 @@ repos:
         name: Lint rST files in docs folder using Sphinx Lint
         files: ^(docs/en|docs/zh_CN)/.*\.(rst|inc)$
   - repo: https://github.com/espressif/esp-idf-kconfig.git
-    rev: v2.1.0
+    rev: v2.3.0
     hooks:
       - id: check-kconfig-files
diff --git a/Kconfig b/Kconfig
@@ -135,7 +135,6 @@ mainmenu "Espressif IoT Development Framework Configuration"
         default "y" if IDF_TARGET="esp32c61"
         select FREERTOS_UNICORE
         select IDF_TARGET_ARCH_RISCV
-        select IDF_ENV_FPGA
 
     config IDF_TARGET_LINUX
         bool

diff --git a/README.md b/README.md
@@ -15,17 +15,17 @@ ESP-IDF is the development framework for Espressif SoCs supported on Windows, Li
 
 The following table shows ESP-IDF support of Espressif SoCs where ![alt text][preview] and ![alt text][supported] denote preview status and support, respectively. The preview support is usually limited in time and intended for beta versions of chips. Please use an ESP-IDF release where the desired SoC is already supported.
 
-|Chip         |          v4.4          |          v5.0          |         v5.1           |         v5.2           |         v5.3           |                                                            |
-|:----------- | :---------------------:| :---------------------:| :--------------------: | :--------------------: | :--------------------: | :--------------------------------------------------------- |
-|ESP32        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |                                                            |
-|ESP32-S2     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |                                                            |
-|ESP32-C3     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |                                                            |
-|ESP32-S3     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32_S3) |
-|ESP32-C2     |                        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32-C2) |
-|ESP32-C6     |                        |                        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32_C6) |
-|ESP32-H2     |                        |                        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32_H2) |
-|ESP32-P4     |                        |                        |                        |                        | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32-P4) |
-|ESP32-C5     |                        |                        |                        |                        | ![alt text][preview]   | [Announcement](https://www.espressif.com/en/news/ESP32-C5) |
+|Chip         |          v5.0          |         v5.1           |         v5.2           |         v5.3           |                                                            |
+|:----------- | :---------------------:| :--------------------: | :--------------------: | :--------------------: | :--------------------------------------------------------- |
+|ESP32        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |                                                            |
+|ESP32-S2     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |                                                            |
+|ESP32-C3     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |                                                            |
+|ESP32-S3     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32_S3) |
+|ESP32-C2     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32-C2) |
+|ESP32-C6     |                        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32_C6) |
+|ESP32-H2     |                        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32_H2) |
+|ESP32-P4     |                        |                        |                        | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32-P4) |
+|ESP32-C5     |                        |                        |                        | ![alt text][preview]   | [Announcement](https://www.espressif.com/en/news/ESP32-C5) |
 
 [supported]: https://img.shields.io/badge/-supported-green "supported"
 [preview]: https://img.shields.io/badge/-preview-orange "preview"

diff --git a/README_CN.md b/README_CN.md
@@ -15,17 +15,17 @@ ESP-IDF 是乐鑫官方推出的物联网开发框架，支持 Windows、Linux
 
 下表总结了乐鑫芯片在 ESP-IDF 各版本中的支持状态，其中 ![alt text][supported] 代表已支持，![alt text][preview] 代表目前处于预览支持状态。预览支持状态通常有时间限制，而且仅适用于测试版芯片。请确保使用与芯片相匹配的 ESP-IDF 版本。
 
-|芯片         |          v4.4          |          v5.0          |          v5.1          |          v5.2          |          v5.3          |                                                                 |
-|:----------- | :---------------------:| :---------------------:| :--------------------: | :--------------------: | :--------------------: | :-------------------------------------------------------------- |
-|ESP32        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |                                                                 |
-|ESP32-S2     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |                                                                 |
-|ESP32-C3     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |                                                                 |
-|ESP32-S3     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32_S3) |
-|ESP32-C2     |                        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32-C2) |
-|ESP32-C6     |                        |                        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32_C6) |
-|ESP32-H2     |                        |                        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32_H2) |
-|ESP32-P4     |                        |                        |                        |                        | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/en/news/ESP32-P4)      |
-|ESP32-C5     |                        |                        |                        |                        | ![alt text][preview]   | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32-C5) |
+|芯片         |          v5.0          |          v5.1          |          v5.2          |          v5.3          |                                                                 |
+|:----------- | :---------------------:| :--------------------: | :--------------------: | :--------------------: | :-------------------------------------------------------------- |
+|ESP32        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |                                                                 |
+|ESP32-S2     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |                                                                 |
+|ESP32-C3     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |                                                                 |
+|ESP32-S3     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32_S3) |
+|ESP32-C2     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32-C2) |
+|ESP32-C6     |                        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32_C6) |
+|ESP32-H2     |                        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32_H2) |
+|ESP32-P4     |                        |                        |                        | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32-P4) |
+|ESP32-C5     |                        |                        |                        | ![alt text][preview]   | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32-C5) |
 
 [supported]: https://img.shields.io/badge/-%E6%94%AF%E6%8C%81-green "supported"
 [preview]: https://img.shields.io/badge/-%E9%A2%84%E8%A7%88-orange "preview"
@@ -122,7 +122,7 @@ ESP-IDF 中的子模块采用相对路径（[详见 .gitmodules 文件](.gitmodu
 
 * 最新版的文档：https://docs.espressif.com/projects/esp-idf/ ，该文档是由本仓库 [docs 目录](docs) 构建得到。
 
-* [初学者指南：主要概念和资源](https://www.bilibili.com/video/BV1114y1r7du/) 
+* [初学者指南：主要概念和资源](https://www.bilibili.com/video/BV1114y1r7du/)
 
 * 可以前往 [esp32.com 论坛](https://esp32.com/) 提问，挖掘社区资源。
 

diff --git a/components/app_update/test_apps/pytest_app_update_ut.py b/components/app_update/test_apps/pytest_app_update_ut.py
@@ -1,4 +1,4 @@
-# SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+# SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
 # SPDX-License-Identifier: Unlicense OR CC0-1.0
 import re
 
@@ -22,11 +22,4 @@ def run_multiple_stages(dut: Dut, test_case_num: int, stages: int) -> None:
 @pytest.mark.temp_skip_ci(targets=['esp32c5'], reason='C5 has not supported deep sleep')  # TODO: [ESP32C5] IDF-8640, IDF-10317
 @pytest.mark.generic
 def test_app_update(dut: Dut) -> None:
-    extra_data = dut.parse_test_menu()
-    for test_case in extra_data:
-        if test_case.type != 'multi_stage':
-            dut.write(str(test_case.index))
-        else:
-            run_multiple_stages(dut, test_case.index, len(test_case.subcases))
-        dut.expect_unity_test_output(timeout=90)
-        dut.expect_exact("Enter next test, or 'enter' to see menu")
+    dut.run_all_single_board_cases(timeout=90)
diff --git a/components/bootloader_support/CMakeLists.txt b/components/bootloader_support/CMakeLists.txt
@@ -15,7 +15,7 @@ set(srcs
     "src/secure_boot.c"
     )
 
-if(NOT CONFIG_IDF_ENV_FPGA)
+if(NOT CONFIG_ESP_BRINGUP_BYPASS_RANDOM_SETTING)
     # For FPGA ENV, bootloader_random implementation is implemented in `bootloader_random.c`
     list(APPEND srcs "src/bootloader_random_${IDF_TARGET}.c")
 endif()

diff --git a/components/bootloader_support/src/bootloader_random.c b/components/bootloader_support/src/bootloader_random.c
@@ -83,10 +83,10 @@
 }
 #endif // BOOTLOADER_BUILD
 
-#if CONFIG_IDF_ENV_FPGA
+#if CONFIG_ESP_BRINGUP_BYPASS_RANDOM_SETTING
 static void s_non_functional(const char *func)
 {
-    ESP_EARLY_LOGW("rand", "%s non-functional for FPGA builds", func);
+    ESP_EARLY_LOGW("rand", "%s non-functional as RNG has not been supported yet", func);
 }
 
 void bootloader_random_enable()
@@ -98,4 +98,4 @@ void bootloader_random_disable()
 {
     s_non_functional(__func__);
 }
-#endif // CONFIG_IDF_ENV_FPGA
+#endif // CONFIG_ESP_BRINGUP_BYPASS_RANDOM_SETTING
diff --git a/components/bootloader_support/src/bootloader_random_esp32c5.c b/components/bootloader_support/src/bootloader_random_esp32c5.c
@@ -3,20 +3,103 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
+#include "sdkconfig.h"
+#include "bootloader_random.h"
 #include "soc/soc.h"
 #include "soc/pcr_reg.h"
+#include "soc/apb_saradc_reg.h"
 #include "soc/pmu_reg.h"
 #include "hal/regi2c_ctrl.h"
+#include "soc/lpperi_reg.h"
+#include "soc/regi2c_saradc.h"
 #include "esp_log.h"
 
+static const uint32_t SAR2_CHANNEL = 9;
+static const uint32_t SAR1_CHANNEL = 7;
+static const uint32_t PATTERN_BIT_WIDTH = 6;
+static const uint32_t SAR1_ATTEN = 3;
+static const uint32_t SAR2_ATTEN = 3;
+
 void bootloader_random_enable(void)
 {
-// TODO: [ESP32C5] IDF-8626
-    ESP_EARLY_LOGW("bootloader_random", "bootloader_random_enable() has not been implemented on C5 yet");
+    // pull SAR ADC out of reset
+    REG_SET_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_RST_EN);
+    REG_CLR_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_RST_EN);
+
+    // enable SAR ADC APB clock
+    REG_SET_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_REG_CLK_EN);
+
+    // pull APB register out of reset
+    REG_SET_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_REG_RST_EN);
+    REG_CLR_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_REG_RST_EN);
+
+    // enable ADC_CTRL_CLK (SAR ADC function clock)
+    REG_SET_BIT(PCR_SARADC_CLKM_CONF_REG, PCR_SARADC_CLKM_EN);
+
+    // select XTAL clock (40 MHz) source for ADC_CTRL_CLK
+    REG_SET_FIELD(PCR_SARADC_CLKM_CONF_REG, PCR_SARADC_CLKM_SEL, 0); // 0: XTAL; 1: 80M(from bbpll); 2. FOSC
+
+    // set the clock divider for ADC_CTRL_CLK to default value (in case it has been changed)
+    REG_SET_FIELD(PCR_SARADC_CLKM_CONF_REG, PCR_SARADC_CLKM_DIV_NUM, 0);
+
+    // some magic register poke from the digital team
+    SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
+    SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
+
+    // Config ADC circuit (Analog part) with I2C (HOST ID 0X69) and choose internal voltage as sampling source
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 0);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_PERIF_ADDR, 1);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_EN_TOUT_ADDR, 1);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_EN_TOUT_ADDR, 1);
+
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_HIGH_ADDR, 0x08);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_LOW_ADDR, 0x66);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_SAR1_INIT_CODE_MSB, 0x08);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_SAR1_INIT_CODE_LSB, 0x66);
+
+    // create patterns and set them in pattern table
+    uint32_t pattern_one = (SAR2_CHANNEL << 2) | SAR2_ATTEN; // we want channel 9 with max attenuation
+    uint32_t pattern_two = (SAR1_CHANNEL << 2) | SAR1_ATTEN; // we want channel 7 with max attenuation
+    uint32_t pattern_table = 0 | (pattern_two << 3 * PATTERN_BIT_WIDTH) | pattern_one << 2 * PATTERN_BIT_WIDTH;
+    REG_WRITE(APB_SARADC_SAR_PATT_TAB1_REG, pattern_table);
+
+    // set pattern length  (APB_SARADC_SARADC_SAR_PATT_LEN counts from 0)
+    REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SARADC_SAR_PATT_LEN, 1);
+
+    REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SARADC_SAR_CLK_DIV, 15);
+
+    // set timer expiry (timer is ADC_CTRL_CLK)
+    REG_SET_FIELD(APB_SARADC_CTRL2_REG, APB_SARADC_SARADC_TIMER_TARGET, 200);
+
+    // enable timer
+    REG_SET_BIT(APB_SARADC_CTRL2_REG, APB_SARADC_SARADC_TIMER_EN);
+    CLEAR_PERI_REG_MASK(LPPERI_RNG_CFG_REG, LPPERI_RNG_TIMER_EN);
 }
 
 void bootloader_random_disable(void)
 {
-// TODO: [ESP32C5] IDF-8626
-    ESP_EARLY_LOGW("bootloader_random", "bootloader_random_disable() has not been implemented on C5 yet");
+    // disable timer
+    REG_CLR_BIT(APB_SARADC_CTRL2_REG, APB_SARADC_SARADC_TIMER_EN);
+
+    // Write reset value of this register
+    REG_WRITE(APB_SARADC_SAR_PATT_TAB1_REG, 0xFFFFFF);
+
+    // Revert ADC I2C configuration and initial voltage source setting
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_HIGH_ADDR, 0x60);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_LOW_ADDR, 0x0);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_SAR1_INIT_CODE_MSB, 0x60);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_SAR1_INIT_CODE_LSB, 0x0);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 0);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_PERIF_ADDR, 0);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_EN_TOUT_ADDR, 0);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_EN_TOUT_ADDR, 0);
+
+    // Revert PMU_RF_PWC_REG to it's initial value
+    CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
+
+    // disable ADC_CTRL_CLK (SAR ADC function clock)
+    REG_WRITE(PCR_SARADC_CLKM_CONF_REG, 0x00404000);
+
+    // Set PCR_SARADC_CONF_REG to initial state
+    REG_WRITE(PCR_SARADC_CONF_REG, 0x5);
 }
diff --git a/components/bootloader_support/src/esp32c61/bootloader_esp32c61.c b/components/bootloader_support/src/esp32c61/bootloader_esp32c61.c
@@ -39,7 +39,6 @@
 #include "esp_efuse.h"
 #include "hal/mmu_hal.h"
 #include "hal/cache_hal.h"
-#include "hal/clk_tree_ll.h"
 #include "soc/lp_wdt_reg.h"
 #include "hal/efuse_hal.h"
 #include "hal/lpwdt_ll.h"
@@ -86,15 +85,6 @@ static void bootloader_super_wdt_auto_feed(void)
 
 static inline void bootloader_hardware_init(void)
 {
-    // In 80MHz flash mode, ROM sets the mspi module clk divider to 2, fix it here
-#if CONFIG_ESPTOOLPY_FLASHFREQ_80M && !CONFIG_APP_BUILD_TYPE_RAM
-    clk_ll_mspi_fast_set_hs_divider(6);
-    esp_rom_spiflash_config_clk(1, 0);
-    esp_rom_spiflash_config_clk(1, 1);
-    esp_rom_spiflash_fix_dummylen(0, 1);
-    esp_rom_spiflash_fix_dummylen(1, 1);
-#endif
-
     regi2c_ctrl_ll_master_enable_clock(true);
     regi2c_ctrl_ll_master_force_enable_clock(true); // TODO: IDF-9274 Remove this?
     regi2c_ctrl_ll_master_configure_clock();

diff --git a/components/bootloader_support/src/flash_encryption/flash_encrypt.c b/components/bootloader_support/src/flash_encryption/flash_encrypt.c
@@ -428,7 +428,7 @@ static esp_err_t encrypt_partition(int index, const esp_partition_info_t *partit
                                &partition->pos,
                                &image_data);
         should_encrypt = (err == ESP_OK);
-#ifdef SECURE_FLASH_ENCRYPT_ONLY_IMAGE_LEN_IN_APP_PART
+#ifdef CONFIG_SECURE_FLASH_ENCRYPT_ONLY_IMAGE_LEN_IN_APP_PART
         if (should_encrypt) {
             // Encrypt only the app image instead of encrypting the whole partition
             size = image_data.image_len;