refactor: naming optimizations in hwt/hwtLib Nic30/hwt#17

README.md

@@ -53,7 +53,7 @@ You can also install only C++ library/generate .deb package (nothing specific, j
 meson setup build -Dpython_package=false
 ninja -C build
 ```
-For dev purposes also this link could be usefull https://meson-python.readthedocs.io/en/latest/how-to-guides/meson-args.html#how-to-guides-meson-args
+For dev purposes also this link could be useful https://meson-python.readthedocs.io/en/latest/how-to-guides/meson-args.html#how-to-guides-meson-args
 
 ## Usage
 

tests/basic_hdl_sim_model/expected/simple_subunit.py.txt

@@ -7,8 +7,8 @@ from hwtSimApi.basic_hdl_simulator.model_utils import sensitivity, connectSimPor
 from hwtSimApi.basic_hdl_simulator.proxy import BasicRtlSimProxy
 from hwtSimApi.basic_hdl_simulator.sim_utils import sim_eval_cond
 
-class subunit0(BasicRtlSimModel):
-    def __init__(self, sim: "BasicRtlSimulator", name="subunit0"):
+class submodule0(BasicRtlSimModel):
+    def __init__(self, sim: "BasicRtlSimulator", name="submodule0"):
         BasicRtlSimModel.__init__(self, sim, name=name)
         # ports
         self.io.a = BasicRtlSimProxy(
@@ -27,12 +27,12 @@ class subunit0(BasicRtlSimModel):
         self._processes = (
             self.assig_process_b,
         )
-        self._units = ()
+        self._subHwModules = ()
         sensitivity(self.assig_process_b, self.io.a)
         self._outputs[self.assig_process_b] = (
             self.io.b,
         )
-        for u in self._units:
+        for u in self._subHwModules:
             u._init_body()
 
     # sensitivity: a
@@ -50,45 +50,45 @@ class SimpleSubunit(BasicRtlSimModel):
             sim, self, "b",
             Bits3t(1, 0), None)
         # internal signals
-        self.io.sig_subunit0_a = BasicRtlSimProxy(
-            sim, self, "sig_subunit0_a",
+        self.io.sig_submodule0_a = BasicRtlSimProxy(
+            sim, self, "sig_submodule0_a",
             Bits3t(1, 0), None)
-        self.io.sig_subunit0_b = BasicRtlSimProxy(
-            sim, self, "sig_subunit0_b",
+        self.io.sig_submodule0_b = BasicRtlSimProxy(
+            sim, self, "sig_submodule0_b",
             Bits3t(1, 0), None)
         # component instances
-        self.subunit0_inst = subunit0(sim, "subunit0_inst")
+        self.submodule0_inst = submodule0(sim, "submodule0_inst")
     def _init_body(self):
-        connectSimPort(self, self.subunit0_inst, "sig_subunit0_a", "a")
-        connectSimPort(self, self.subunit0_inst, "sig_subunit0_b", "b")
+        connectSimPort(self, self.submodule0_inst, "sig_submodule0_a", "a")
+        connectSimPort(self, self.submodule0_inst, "sig_submodule0_b", "b")
         self._interfaces = (
             self.io.a,
             self.io.b,
-            self.io.sig_subunit0_a,
-            self.io.sig_subunit0_b,
+            self.io.sig_submodule0_a,
+            self.io.sig_submodule0_b,
         )
         self._processes = (
             self.assig_process_b,
-            self.assig_process_sig_subunit0_a,
+            self.assig_process_sig_submodule0_a,
         )
-        self._units = (self.subunit0_inst,
+        self._subHwModules = (self.submodule0_inst,
         )
-        sensitivity(self.assig_process_b, self.io.sig_subunit0_b)
+        sensitivity(self.assig_process_b, self.io.sig_submodule0_b)
         self._outputs[self.assig_process_b] = (
             self.io.b,
         )
-        sensitivity(self.assig_process_sig_subunit0_a, self.io.a)
-        self._outputs[self.assig_process_sig_subunit0_a] = (
-            self.io.sig_subunit0_a,
+        sensitivity(self.assig_process_sig_submodule0_a, self.io.a)
+        self._outputs[self.assig_process_sig_submodule0_a] = (
+            self.io.sig_submodule0_a,
         )
-        for u in self._units:
+        for u in self._subHwModules:
             u._init_body()
 
-    # sensitivity: sig_subunit0_b
+    # sensitivity: sig_submodule0_b
     def assig_process_b(self):
-        self.io.b.val_next = (self.io.sig_subunit0_b.val, 0, )
+        self.io.b.val_next = (self.io.sig_submodule0_b.val, 0, )
 
     # sensitivity: a
-    def assig_process_sig_subunit0_a(self):
-        self.io.sig_subunit0_a.val_next = (self.io.a.val, 0, )
+    def assig_process_sig_submodule0_a(self):
+        self.io.sig_submodule0_a.val_next = (self.io.a.val, 0, )
 

tests/hwt/expected/decoder_using_case.py.txt

@@ -1,14 +1,14 @@
 from hwt.code import If, Switch, Concat
 from hwt.code_utils import rename_signal
+from hwt.hwIOs.std import HwIOSignal
+from hwt.hwModule import HwModule
+from hwt.hwParam import HwParam
 from hwt.hdl.types.array import HArray
-from hwt.hdl.types.bits import Bits
+from hwt.hdl.types.bits import HBits
 from hwt.hdl.types.defs import INT, SLICE, STR, BIT, FLOAT64
 from hwt.hdl.types.enum import HEnum
-from hwt.interfaces.std import Signal
-from hwt.synthesizer.param import Param
-from hwt.synthesizer.unit import Unit
 
-class decoder_using_case(Unit):
+class decoder_using_case(HwModule):
     """ http://www.asic-world.com/code/hdl_models/decoder_using_case.v
     -----------------------------------------------------
      Design Name : decoder_using_case
@@ -20,11 +20,11 @@ class decoder_using_case(Unit):
     """
     def _declr(self):
         # ports
-        self.binary_in = Signal(Bits(5))
+        self.binary_in = HwIOSignal(HBits(5))
         # 4 bit binary input
-        self.decoder_out = Signal(Bits(17))._m()
+        self.decoder_out = HwIOSignal(HBits(17))._m()
         # 16-bit  out
-        self.enable = Signal()
+        self.enable = HwIOSignal()
         # component instances
 
     def _impl(self):

tests/hwt/expected/uart.py.txt

@@ -1,14 +1,14 @@
 from hwt.code import If, Switch, Concat
 from hwt.code_utils import rename_signal
+from hwt.hwIOs.std import HwIOSignal
+from hwt.hwModule import HwModule
+from hwt.hwParam import HwParam
 from hwt.hdl.types.array import HArray
-from hwt.hdl.types.bits import Bits
+from hwt.hdl.types.bits import HBits
 from hwt.hdl.types.defs import INT, SLICE, STR, BIT, FLOAT64
 from hwt.hdl.types.enum import HEnum
-from hwt.interfaces.std import Signal
-from hwt.synthesizer.param import Param
-from hwt.synthesizer.unit import Unit
 
-class uart(Unit):
+class uart(HwModule):
     """http://www.asic-world.com/examples/verilog/uart.html
     -----------------------------------------------------
      Design Name : uart 
@@ -21,19 +21,19 @@ class uart(Unit):
     def _declr(self):
         # ports
         # Port declarations
-        self.reset = Signal()
-        self.txclk = Signal()
-        self.ld_tx_data = Signal()
-        self.tx_data = Signal(Bits(9))
-        self.tx_enable = Signal()
-        self.tx_out = Signal()._m()
-        self.tx_empty = Signal()._m()
-        self.rxclk = Signal()
-        self.uld_rx_data = Signal()
-        self.rx_data = Signal(Bits(9))._m()
-        self.rx_enable = Signal()
-        self.rx_in = Signal()
-        self.rx_empty = Signal()._m()
+        self.reset = HwIOSignal()
+        self.txclk = HwIOSignal()
+        self.ld_tx_data = HwIOSignal()
+        self.tx_data = HwIOSignal(HBits(9))
+        self.tx_enable = HwIOSignal()
+        self.tx_out = HwIOSignal()._m()
+        self.tx_empty = HwIOSignal()._m()
+        self.rxclk = HwIOSignal()
+        self.uld_rx_data = HwIOSignal()
+        self.rx_data = HwIOSignal(HBits(9))._m()
+        self.rx_enable = HwIOSignal()
+        self.rx_in = HwIOSignal()
+        self.rx_empty = HwIOSignal()._m()
         # component instances
 
     def _impl(self):
@@ -43,12 +43,12 @@ class uart(Unit):
         self.rx_in, self.rx_empty
         # internal signals
         # Internal Variables (@note: interference with ports)
-        tx_reg = self._sig("tx_reg", Bits(9))
+        tx_reg = self._sig("tx_reg", HBits(9))
         tx_over_run = self._sig("tx_over_run")
-        tx_cnt = self._sig("tx_cnt", Bits(5))
-        rx_reg = self._sig("rx_reg", Bits(9))
-        rx_sample_cnt = self._sig("rx_sample_cnt", Bits(5))
-        rx_cnt = self._sig("rx_cnt", Bits(5))
+        tx_cnt = self._sig("tx_cnt", HBits(5))
+        rx_reg = self._sig("rx_reg", HBits(9))
+        rx_sample_cnt = self._sig("rx_sample_cnt", HBits(5))
+        rx_cnt = self._sig("rx_cnt", HBits(5))
         rx_frame_err = self._sig("rx_frame_err")
         rx_over_run = self._sig("rx_over_run")
         rx_d1 = self._sig("rx_d1")

tests/verilog/simple_subunit.v

@@ -1,4 +1,4 @@
-module subunit0(input a,
+module submodule0(input a,
         output b
     );
 
@@ -9,13 +9,13 @@ module SimpleSubunit(input a,
         output b
     );
 
-    wire sig_subunit0_a;
-    wire sig_subunit0_b;
-    subunit0 subunit0_inst (.a(sig_subunit0_a),
-        .b(sig_subunit0_b)
+    wire sig_submodule0_a;
+    wire sig_submodule0_b;
+    submodule0 submodule0_inst (.a(sig_submodule0_a),
+        .b(sig_submodule0_b)
         );
 
 
-    assign b = sig_subunit0_b;
-    assign sig_subunit0_a = a;
+    assign b = sig_submodule0_b;
+    assign sig_submodule0_a = a;
 endmodule