GitHub - SimulationEverywhere-Models/CDPP-ALFA1: Alfa-1 simulated computer. A complete computer based on the SPARC Integer Unit. It is possible to test each of the isolated components. Performance improvements to the computer can be analyzed using these models. ALFA-1 Project (visit this link for more information).

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Alfa-1 simulated computer. A complete computer based on the SPARC Integer Unit. It is possible to test each of the isolated components. Performance improvements to the computer can be analyzed using these models. ALFA-1 Project (visit this link for more information).

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Name		Name	Last commit message	Last commit date
Latest commit History 1 Commit
ALU.cpp		ALU.cpp
ALU.h		ALU.h
AND.cpp		AND.cpp
AND.h		AND.h
Adder.cpp		Adder.cpp
Adder.h		Adder.h
Alfa1_model.doc		Alfa1_model.doc
AlignL.cpp		AlignL.cpp
AlignL.h		AlignL.h
AlignS.cpp		AlignS.cpp
AlignS.h		AlignS.h
Bus.cpp		Bus.cpp
Bus.h		Bus.h
CCLogic.cpp		CCLogic.cpp
CCLogic.cpp~		CCLogic.cpp~
CCLogic.h		CCLogic.h
CCLogic.h~		CCLogic.h~
CS.cpp		CS.cpp
CS.h		CS.h
CWPlogic.cpp		CWPlogic.cpp
CWPlogic.h		CWPlogic.h
Clock.cpp		Clock.cpp
Clock.h		Clock.h
Cmp.cpp		Cmp.cpp
Cmp.h		Cmp.h
FromDeci.cpp		FromDeci.cpp
FromDeci.h		FromDeci.h
IRQLogic.cpp		IRQLogic.cpp
IRQLogic.h		IRQLogic.h
Inc4.cpp		Inc4.cpp
Inc4.h		Inc4.h
IncDec.cpp		IncDec.cpp
IncDec.h		IncDec.h
Latch.cpp		Latch.cpp
Latch.h		Latch.h
Mem.cpp		Mem.cpp
Mem.h		Mem.h
MulDiv.cpp		MulDiv.cpp
MulDiv.h		MulDiv.h
Mux.cpp		Mux.cpp
Mux.h		Mux.h
MuxN.cpp		MuxN.cpp
MuxN.h		MuxN.h
NOT.cpp		NOT.cpp
NOT.h		NOT.h
RegBlock.cpp		RegBlock.cpp
RegBlock.h		RegBlock.h
RegGlob.cpp		RegGlob.cpp
RegGlob.h		RegGlob.h
Shifter.cpp		Shifter.cpp
Shifter.h		Shifter.h
SignExtN.cpp		SignExtN.cpp
SignExtN.h		SignExtN.h
TestIn.cpp		TestIn.cpp
TestIn.h		TestIn.h
TestOut.cpp		TestOut.cpp
TestOut.h		TestOut.h
ToDeci.cpp		ToDeci.cpp
ToDeci.h		ToDeci.h
TrapLogic.cpp		TrapLogic.cpp
TrapLogic.h		TrapLogic.h
UC.cpp		UC.cpp
UC.h		UC.h
UCTest.cpp		UCTest.cpp
UCTest.h		UCTest.h
WIMCheck.cpp		WIMCheck.cpp
WIMCheck.h		WIMCheck.h
bits.cpp		bits.cpp
bits.h		bits.h
events.ev		events.ev
iu.bat		iu.bat
iu.log		iu.log
iu.ma		iu.ma
iu.out		iu.out
memoria.mem		memoria.mem
memory.map		memory.map
register.cpp		register.cpp
system_wr.ev		system_wr.ev
system_wr.ma		system_wr.ma