removing call to dump_attributes to remove possibility of generating …

…invalid verilog Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
YosysHQ · Jan 30, 2024 · 3076875 · 3076875
1 parent 33fe2e4
commit 3076875
Showing 1 changed file with 0 additions and 1 deletion.
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
@@ -1058,7 +1058,6 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		f << stringf("%s" "assign ", indent.c_str());
 		dump_sigspec(f, cell->getPort(ID::Y));
 		f << stringf(" = ");
-		dump_attributes(f, "", cell->attributes, " ");
 		dump_cell_expr_port(f, cell, "A", false);
 		f << stringf(";\n");
 		return true;