Topology: NHLT: Intel: Add support for blob format v3.0 #276
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This patch adds the 3.0 format the is used for the PTL ACE3.x platform. Blob 3.0 is based on blob 1.5 has changes to adds some DMA control registers and has some changes in registers bitfields. This patch also fixes some compile warnings when NHLT_DEBUG is set for comparing int with unsigned in ssp-debug.c for code for all blobs variants. Signed-off-by: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
The MOD = 1 is the only allowed setting for SSC0(31) bit for cAVS 2.x and all ACE versions 1.x, 2.x, and 3.x Signed-off-by: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
- The SSC1 bits 21 and 20, TSRE and RSRE, do not exist. - The SSC0 bit 30 ACS does not exist. - The SSC0 bit 6 ECS does not exist but needs to be set, add note. - The MDIVXCTRL bits 20:21 MNDSS does not exist. Signed-off-by: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
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| blob30->gateway_attributes = blob->gateway_attributes; | ||
| blob30->version = SSP_BLOB_VER_3_0; |
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wow now I am really confused, I though the blobs 3.0 did NOT include the version and size?
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This is what the FW team decided. It might be still necessary to support in firmware the BIOS NHLT format (no header) if it's not aligned with this (I2S BT offload in PCs as possible application, currently not supported). But in topology embedded NHLT this is the format to use.
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if there are two formats for the blobs, then effectively anything designed for Windows will not be supported by SOF firmware.
It's problematic mainly for devices using HDMI inputs over SSP.
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Yep, the firmware may need to support two formats for all SSP scenarios. It's possible technically. In PTL platform build a blob 1.0 is treated as headerderless blob 3.0 registers setup. And this format is detected normally from headers as 3.0. With merge of zephyrproject-rtos/zephyr#77916 into Zephyr. The blob 3.0 format with header created by this PR is the default format.
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@plbossart Do you still have concerns for this?
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