Skip to content

Commit

Permalink
It's siliconcompiler
Browse files Browse the repository at this point in the history
  • Loading branch information
rseac committed Jan 24, 2024
1 parent 1bd8044 commit 65889b5
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion README.rst
View file
Original file line number Diff line number Diff line change
Expand Up @@ -50,7 +50,7 @@ For information about running verilog conversion tests, see `this file <tests/ve
ASIC flow
----------

We have successfully been able to use the open-source ASIC flow in `systemcompiler <https://www.siliconcompiler.com/>`_ to generate the chip for ZFP's encoder. The input to siliconcompiler is the RTL generated by SCCL. Below is what we got.
We have successfully been able to use the open-source ASIC flow in `siliconcompiler <https://www.siliconcompiler.com/>`_ to generate the chip for ZFP's encoder. The input to siliconcompiler is the RTL generated by SCCL. Below is what we got.

.. image:: docs/zhw_encode.png
:width: 400
Expand Down

0 comments on commit 65889b5

Please sign in to comment.