Update tests and script for new constructs

plugins/xlat/convert.py

@@ -1,6 +1,7 @@
 from lark import Lark, Transformer, Visitor
 import sys
 import logging
+import warnings
 logging.basicConfig(level=logging.DEBUG)
 
 l = Lark('''
@@ -25,11 +26,12 @@
         inportdecl: "(" "hPortin" ID ")"
         outportdecl: "(" "hPortout" ID ")"
         vardecltype: hvardecl "[" htype "]" 
+                   | hvardecl "[" htype htype "]"
 
         // can be no process at all in the module
         processlist: ("[" hprocess "]") *
         // could be nothing
-        hprocess: "(" "hProcess" ID ")" "[" hsensvars "]"  "[" hcstmt "]"
+        hprocess: "(" "hProcess" ID ")" hsenslist  "[" hcstmt "]"
 
         // can be just an empty statement
         hcstmt: "(" "hCStmt" ")" hlitdecl stmts
@@ -39,19 +41,25 @@
         ?stmt : exprwrapper
              | ifstmtwrapper
              | hvardefwrapper
+             | forstmtwrapper
              | htemptrigger
 
         exprwrapper: "[" expression "]"
         ?ifstmtwrapper: "[" ifstmt "]"
         hvardefwrapper: "[" "[" hvardef "]" "]"
+        forstmtwrapper: "[" forstmt "]"
 
+        hsenslist: "[" (hsensvar hsensedge)* "]"
+                 | "[" "[" (hsensvar hsensedge)* "]" "]"
         hsensvar : "(" "hSensvar" ID ")"
         hsensvars : hsensvar*
+        hsensedge : "(" "hSensedge"  EDGE ")"
 
 
         // if and if-else, not handling if-elseif case
         ifstmt: ifcond "[" (hcstmt|exprinif|ifstmt) "]"
               | ifcond "[" (hcstmt|exprinif|ifstmt) "]" "[" (hcstmt|exprinif|ifstmt) "]"
+        forstmt: "(" "hForStmt" ")" "[" "[" hvardef "]" "]" "[" expression "]" "[" expression "]" stmts
         exprinif: expression
 
         ifcond: "(" "hIfStmt" ")" expression
@@ -64,18 +72,22 @@
                   | hunop
                   | hliteral
                   | hvardecl
+                  | hvarref
                   | hunimp
                   | syscread
                   | syscwrite
                   | "[" expression "]"
 
         syscread : hsigassignr hliteral
+                 | hsigassignr exprwrapper
         syscwrite : hsigassignl hliteral expression
+                 | hsigassignl exprwrapper (hliteral|"[" syscread "]")
         ?hsigassignr : "(" "hSigAssignR" "read" ")"
         ?hsigassignl : "(" "hSigAssignL" "write" ")"
         // function call
         fcall : "[" hliteral hvardecl "]"
 
+        hvarref: "(" "hVarref" ID ")"
         hunimp: "(" "hUnimpl" ID ")"
         hbinop: "(" "hBinop" BINOP ")" (expression|fcall) (expression|fcall)
         hunop: "(" "hUnop" UNOP ")" expression
@@ -93,8 +105,9 @@
         htype: "(" "hType" ID ")"
 
         ID: /[a-zA-Z_0-9]+/
-        BINOP: "==" | "&&" | "=" | "||" | "-" | ">" | "+" | "*" | "^"
-        UNOP: "!"
+        BINOP: "==" | "&&" | "=" | "||" | "-" | ">" | "+" | "*" | "^" | "[]" | "<=" | "<"
+        UNOP: "!" | "++"
+        EDGE: "pos" | "neg"
         %import common.WS
         %ignore WS
         ''', parser='lalr', debug=True)
@@ -141,6 +154,7 @@ def hcstmt(self, args):
             else:
                 stmt_list.append(stmt)
         # currently it's ok to append a comma
+        print(stmt_list)
         res = '\n'.join(x for x in stmt_list)
         return res
 
@@ -154,6 +168,8 @@ def hbinop(self, args):
         op = str(args[0])
         if op == '=':
             return f'{args[1]} {args[0]} {args[2]}'
+        elif op == '[]':
+            return f'({args[1]})[(args[2])]'
         else:
             return f'({args[1]}) {args[0]} ({args[2]})'
 
@@ -162,6 +178,8 @@ def hunop(self, args):
             return f'{args[0]}'
         elif len(args) == 2:
             op = str(args[0])
+            if op == '++':
+                warnings.warn('++ may result in ambiguity in Verilog')
             return f'{args[0]}({args[1]})'
 
     def stmts(self, args):
@@ -285,15 +303,39 @@ def exprinif(self, args):
     def hsensvar(self, args):
         return str(args[0])
 
+    def hsenslist(self, args):
+        if len(args) == 2:
+            if args[1] == 'pos':
+                return 'posedge {}'.format(args[0])
+            elif args[1] == 'neg':
+                return 'negedge {}'.format(args[0])
+            else:
+                assert False, 'Cannot convert'
+        assert False
+
+    def hsensedge(self, args):
+        return str(args[0])
+
     def hsigassignl(self, args):
-        return None
+        return 'hsigassignl'
     def hsigassignr(self, args):
-        return None
+        return 'hsigassignr'
     def syscwrite(self, args):
+        print('syscwrite: ', args)
         return f'{args[1]} <= {args[2]}'
     def syscread(self, args):
+        print('syscread: ', args)
         return f'{args[1]}'
 
+    def forstmtwrapper(self, args):
+        return args[0]
+
+    def forstmt(self, args):
+        res = f'for({args[0]}; {args[1]}; {args[2]}) begin\n'
+        res += f'  {args[3]}\n'
+        res += f'end\n'
+        return res
+
     def vardecltype(self, args):
         return ('var', f'{args[1]} {args[0]}')
 
@@ -306,6 +348,9 @@ def htemptrigger(self, args):
     def hsensvars(self, args):
         return ' or '.join(args)
 
+    def hvarref(self, args):
+        return str(args[0])
+
     def fcall(self, args):
         fname = str(args[0])
         caller = str(args[1])

tests/verilog-conversion/conftest.py

@@ -1,7 +1,9 @@
 """Fixtures for testing"""
+import os
 import pytest
 from util.conf import LLNLExampleTestingConfigurations
 from util.conf import ExampleTestingConfigurations
+from util.conf import TestingConfigurations
 import driver as drv
 
 
@@ -21,6 +23,19 @@ def exdriver(request):
     ex_driver = drv.SystemCClangDriver(conf)
     return ex_driver
 
+@pytest.fixture
+def testfolderdriver():
+    """fixture for running tests in the test folder of
+    the systemc-clang"""
+    root_folder = os.environ['SYSTEMC_CLANG_BUILD_DIR'] + '../systemc-clang/tests/'
+    conf = TestingConfigurations(
+            root_folder=root_folder, 
+            golden_folder=[],
+            header_folders=[]
+    )
+    testfolder_driver = drv.SystemCClangDriver(conf)
+    return testfolder_driver
+
 
 def pytest_addoption(parser):
     """add options for controlling the running of tests"""

tests/verilog-conversion/test_member_variable_sc_buffer.py

@@ -0,0 +1,34 @@
+"""test for test_member_variable_sc_buffer.cpp"""
+import os
+from shutil import copy
+
+
+def test_member_variable_sc_buffer_verilog(tmpdir, testfolderdriver, tool_output):
+    """testing the conversion from cpp to sexp"""
+    conf = testfolderdriver.conf
+    output_folder = tmpdir
+    # copy the file to tmpfolder
+    copy(conf.get_module_name('member-variable-sc-buffer.cpp'), output_folder)
+
+    filename = str(output_folder) + '/' + 'member-variable-sc-buffer.cpp'
+
+    res, filename = testfolderdriver.generate_sexp(
+        path=filename,
+        output_folder=output_folder,
+        verbose=tool_output,
+        keep_sexp=True
+    )
+
+    with open(filename, 'r') as f:
+        print(''.join(f.readlines()))
+
+    assert res, 'should convert to sexpression'
+
+    res, filename = testfolderdriver.generate_verilog_from_sexp(
+        path=filename,  # sexp name
+        output_folder=output_folder,
+        verbose=tool_output,
+        keep_v=True
+    )
+
+    assert res, 'should convert from sexpression to verilog'

tests/verilog-conversion/util/conf.py

@@ -12,6 +12,10 @@ def extra_header_folders(self):
         # SystemC Clang build llnl-examples
         return self.header_folders
 
+    @extra_header_folders.setter
+    def set_extra_header_folders(self, value):
+        self._extra_header_folders = value
+
     @property
     def positional_arguments(self):
         """positional arguments for the systemc-clang command"""