[ARM] Fix NCHWc int8 dot product schedule lowering

[masahi]

The code path

tvm/python/tvm/topi/arm_cpu/conv2d_int8.py

Lines 154 to 155 in 6c6e873

	if is_dotprod_available():
	intrin = dot_int8_int8_int32_neon_82(int32_lanes=4)

is broken because (1) we are not passing dtype and (2) the intrin description has a bug in the number of arguments to sdot/udot. For example I get this error if I try to run it:

  File "/home/masa/projects/dev/tvm/src/target/llvm/codegen_llvm.cc", line 981
TVMError: 
---------------------------------------------------------------
An error occurred during the execution of TVM.
For more information, please see: https://tvm.apache.org/docs/errors.html
---------------------------------------------------------------
  Check failed: (f) is false: Cannot find intrinsic declaration, possible type mismatch: llvm.aarch64.neon.udot

The PR that added this intrin, #3978, didn't add a test so this code path was never tested. The PR added something under apps/topi_recipe/conv, https://github.com/apache/tvm/blob/main/apps/topi_recipe/conv/test_conv_int8_arm.py, but this script is broken and needs fixing too.

@tkonolige

[masahi]

schedule_conv2d_nchw_spatial_pack has tophub entries, so they are always picked up based on "time cost" even if topi.arm_cpu.is_int8_hw_support path is taken and the NCHWc int8 schedule is surely faster.

[tkonolige]

Seems like another good argument for removing tophub. You can disable it for the test by putting it all in an empty ApplyHistoryBest.

[masahi]

The annoying thing is this happens on only specific input or filter sizes. It took me some time to figure out why the NCHWc schedule is not used when the input shape is (56, 56) and filter size is 3x3. If I use (128, 128) shape or 1x1 filter, I didn't see this issue.

[tkonolige]

Thanks @masahi

[junrushao]

@vinx13 would you mind taking a look? Thanks a lot!

[u99127]

Looks good to add this test - thank you for finding and fixing this. ]

[Mousius]

LGTM, I'll wait for @vinx13 to take a look 😸