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AArch64 base algorithm refactoring in LLVM #6907

Merged
merged 6 commits into from
Nov 23, 2020
Merged

AArch64 base algorithm refactoring in LLVM #6907

merged 6 commits into from
Nov 23, 2020

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giuseros
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  • I refactored the assembly in arm_cpu/tensor_intrin.py to use LLVM+TIR
  • Removed the interleave boolean parameter in the intrinsic to switch
    among two different interleaving modes. LLVM will now take care of
    interleaving the instructions
  • Applied the changes accordingly to conv2d_gemm.py to call the right
    instrinsic

Note: I found LLVM very sensible to the choice of the -mcpu.
So, in order to preserve performance, it is important to specify the
right -mcpu when creating the LLVM target

@giuseros
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cc @mbaret @u99127 @anijain2305

@mbaret mbaret self-assigned this Nov 16, 2020
mbaret
mbaret reviewed Nov 17, 2020
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Perhaps slightly more explanation on the add-pair part of the intrinsic, otherwise looks like a significant improvement.

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mbaret commented Nov 17, 2020

cc @FrozenGene @yzhliu if you're interested

giuseros pushed a commit to giuseros/incubator-tvm that referenced this pull request Nov 19, 2020
Fix tir allocatio with multiple lanes
d60c93e 
This PR stemmed from apache#6907
and it is fixing a small error in the getter and setter of a buffer for
the case where `t.lanes > 1`. I also added a test to stress the issue.
giuseros pushed a commit to giuseros/incubator-tvm that referenced this pull request Nov 19, 2020
Fix tir allocation with multiple lanes
b3139c3 
This PR stemmed from apache#6907
and it is fixing a small error in the getter and setter of a buffer for
the case where `t.lanes > 1`. I also added a test to stress the issue.
giuseros pushed a commit to giuseros/incubator-tvm that referenced this pull request Nov 19, 2020
Bug-fix] Fix tir allocation with multiple lanes
de9b4c9 
This PR stemmed from apache#6907
and it is fixing a small error in the getter and setter of a buffer for
the case where `t.lanes > 1`. I also added a test to stress the issue.
@giuseros giuseros mentioned this pull request Nov 19, 2020
Merged
giuseros pushed a commit to giuseros/incubator-tvm that referenced this pull request Nov 19, 2020
Bug-fix] Fix tir allocation with multiple lanes
b1fa427 
This PR stemmed from apache#6907
and it is fixing a small error in the getter and setter of a buffer for
the case where `t.lanes > 1`. I also added a test to stress the issue.
tqchen pushed a commit that referenced this pull request Nov 20, 2020
Bug-fix] Fix tir allocation with multiple lanes (#6941)
712663e 
* Bug-fix] Fix tir allocation with multiple lanes

This PR stemmed from #6907
and it is fixing a small error in the getter and setter of a buffer for
the case where `t.lanes > 1`. I also added a test to stress the issue.

* Address dtyped vs non-dtyped constant cases
Giuseppe Rossini added 4 commits November 20, 2020 10:55
AArch64 base algorithm refactoring in LLVM
9985b11 
- I refactored the assembly in arm_cpu/tensor_intrin.py to use LLVM+TIR
- Removed the `interleave` boolean parameter in the intrinsic to switch
among two different interleaving modes. LLVM will now take care of
interleaving the instructions
- Applied the changes accordingly to conv2d_gemm.py to call the right
instrinsic

Note: I found LLVM very sensible to the choice of the `-mcpu`.
So, in order to preserve performance, it is important to specify the
right `-mcpu` when creating the LLVM target
Fix linting
b9a971a
Fix linting -2
40664b0
Fixing comments
d54e73a
mbaret
mbaret reviewed Nov 23, 2020
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Just some final comments on the docstrings.

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mbaret
mbaret approved these changes Nov 23, 2020
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lgtm

@mbaret mbaret merged commit 5423ffe into apache:main Nov 23, 2020
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mbaret commented Nov 23, 2020

This is now merged, thanks @giuseros !

trevor-m pushed a commit to trevor-m/tvm that referenced this pull request Dec 2, 2020
Bug-fix] Fix tir allocation with multiple lanes (apache#6941)
eed88cb 
* Bug-fix] Fix tir allocation with multiple lanes

This PR stemmed from apache#6907
and it is fixing a small error in the getter and setter of a buffer for
the case where `t.lanes > 1`. I also added a test to stress the issue.

* Address dtyped vs non-dtyped constant cases
trevor-m pushed a commit to trevor-m/tvm that referenced this pull request Dec 2, 2020
AArch64 base algorithm refactoring in LLVM (apache#6907)
c640285 
* AArch64 base algorithm refactoring in LLVM

- I refactored the assembly in arm_cpu/tensor_intrin.py to use LLVM+TIR
- Removed the `interleave` boolean parameter in the intrinsic to switch
among two different interleaving modes. LLVM will now take care of
interleaving the instructions
- Applied the changes accordingly to conv2d_gemm.py to call the right
instrinsic

Note: I found LLVM very sensible to the choice of the `-mcpu`.
So, in order to preserve performance, it is important to specify the
right `-mcpu` when creating the LLVM target

* Fix linting

* Fix linting -2

* Fixing comments

* Address review comments

* Fix spaces around ':' in docstrings
trevor-m pushed a commit to trevor-m/tvm that referenced this pull request Dec 4, 2020
Bug-fix] Fix tir allocation with multiple lanes (apache#6941)
5ec48f5 
* Bug-fix] Fix tir allocation with multiple lanes

This PR stemmed from apache#6907
and it is fixing a small error in the getter and setter of a buffer for
the case where `t.lanes > 1`. I also added a test to stress the issue.

* Address dtyped vs non-dtyped constant cases
trevor-m pushed a commit to trevor-m/tvm that referenced this pull request Dec 4, 2020
AArch64 base algorithm refactoring in LLVM (apache#6907)
c9a3efb 
* AArch64 base algorithm refactoring in LLVM

- I refactored the assembly in arm_cpu/tensor_intrin.py to use LLVM+TIR
- Removed the `interleave` boolean parameter in the intrinsic to switch
among two different interleaving modes. LLVM will now take care of
interleaving the instructions
- Applied the changes accordingly to conv2d_gemm.py to call the right
instrinsic

Note: I found LLVM very sensible to the choice of the `-mcpu`.
So, in order to preserve performance, it is important to specify the
right `-mcpu` when creating the LLVM target

* Fix linting

* Fix linting -2

* Fixing comments

* Address review comments

* Fix spaces around ':' in docstrings
trevor-m pushed a commit to neo-ai/tvm that referenced this pull request Dec 4, 2020
@trevor-m
Bug-fix] Fix tir allocation with multiple lanes (apache#6941)
54d2fbb 
* Bug-fix] Fix tir allocation with multiple lanes

This PR stemmed from apache#6907
and it is fixing a small error in the getter and setter of a buffer for
the case where `t.lanes > 1`. I also added a test to stress the issue.

* Address dtyped vs non-dtyped constant cases
trevor-m pushed a commit to neo-ai/tvm that referenced this pull request Dec 4, 2020
@trevor-m
AArch64 base algorithm refactoring in LLVM (apache#6907)
f92c046 
* AArch64 base algorithm refactoring in LLVM

- I refactored the assembly in arm_cpu/tensor_intrin.py to use LLVM+TIR
- Removed the `interleave` boolean parameter in the intrinsic to switch
among two different interleaving modes. LLVM will now take care of
interleaving the instructions
- Applied the changes accordingly to conv2d_gemm.py to call the right
instrinsic

Note: I found LLVM very sensible to the choice of the `-mcpu`.
So, in order to preserve performance, it is important to specify the
right `-mcpu` when creating the LLVM target

* Fix linting

* Fix linting -2

* Fixing comments

* Address review comments

* Fix spaces around ':' in docstrings
@junrushao junrushao mentioned this pull request Nov 1, 2021
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