The System Verilog and VHDL parser, preprocessor and code generator for Python/C++ written in C++. The lower layers are ANTLR4 generated parsers with full language support. Next layer converts this raw Verilog/VHDL AST to simple universal AST (Classes defined in hdlConvertor::hdlObjects and it's python equivalent.). So your project does not not have to care about Verilog/VHDL differences and deprecated ridiculous features. It is also possible to convert this AST back to original HDL or access the comments from HDL.
- IEEE 1076-2008 (VHDL 2008) and all previous standard, (currently without
tool_directiveandPSL) - [IEEE 1076-2019] WIP
- IEEE 1800-2017 (SystemVerilog 2017) and all previous standards.
Linux: Installing dependencies (Ubuntu 19.04)
# use up to date compiler, gcc>=7
# on old systems without libantlr4-runtime-dev you have to add apt repo manually, see .travis.yml
sudo apt install build-essential uuid-dev cmake default-jre python3 python3-dev python3-pip libantlr4-runtime-dev antlr4
Installing this library
# note this may be older version than you see in repo
sudo pip3 install hdlConvertor
# or download repository and run
sudo pip3 install -r requirements.txt
sudo python3 setup.py install
Installer also supports other options which may be usefull
python setup.py install --prefix /tmp/python_install/ -j 8 --build-type Debug -- -DANTLR_JAR_LOCATION=/antlr-4.7.1-complete.jar -- VERBOSE=1
You can also install only C++ library/generate .deb package (nothing specific, just normal cmake-based library)
mkdir build && cd build
cmake .. && cmake . --build
cpack # to generate .deb package
Windows:
Take a look at appveyor.yml. It is required to download antlr4 first and have visual studio or other c++ compiler installed.
The HDL AST (the parsed code) is represented by objects from hdlConvertor.hdlAst.
There are classes for objects in HDL langues and there is also type specified for every property in anotations. This allows IDEs to advise and it is also a part of doc.
Example of usage:
import sys
from hdlConvertor.language import Language
from hdlConvertor.toVerilog import ToVerilog
from hdlConvertor import HdlConvertor
filenames = ["your.v", ]
include_dirs = []
c = HdlConvertor()
d = c.parse(filenames, Language.VERILOG, include_dirs, hierarchyOnly=False, debug=True)
tv = ToVerilog(sys.stdout)
tv.print_context(d)
for o in d.objs:
print(o)
(Tell us If you know about some other project!)
- cl-vhdl - lisp, Parser of VHDL into lisp-expressions
- HDL_ANTLR4 - C# projects that use ANTLR4 library to analyse VHDL and Verilog code
- hdlparse - vhdl/verilog parser in python
- ieee1800_2017 - Java, SystemVerilog preprocessor
- Pyverilog - python verilog toolkit
- pyVHDLParser - python vhdl parser with 2008 support
- rust_hdl - rust vhdl 2008 parser
- slang - Parser and compiler library for SystemVerilog.
- sv-parser - Rust, SystemVerilog parser library fully complient with IEEE 1800-2017
- systemc-clang - SystemC Parser using the Clang Front-end
- v2sc - vhdl to systemc
- veelox - Java+ANTLR, An experiment in SystemVerilog Preprocessing
- verilog-parser - A Flex/Bison Parser for the IEEE 1364-2001 Verilog Standard.
- vbpp - C, Verilog PreProcessor
- tree-sitter-verilog - JS, Verilog grammar for tree-sitter
- Verilog-Perl
- vpp.pl - verilog preprocessor with integrated Perl
- sv2v- Haskell, SystemVerilog to Verilog
- Surelog - C++, System Verilog 2017 Pre-processor and parser
- verible - C++, System Verilog 2017 parser