Example for Kintex7 on Digilent Genesys2 board (stub)

common/common.mk

@@ -13,6 +13,10 @@ else ifeq ($(TARGET),arty_100)
   DEVICE := xc7a100t_test
   BITSTREAM_DEVICE := artix7
   PARTNAME := xc7a100tcsg324-1
+else ifeq ($(TARGET),genesys2)
+  DEVICE := xc7k325t_test
+  BITSTREAM_DEVICE := kintex7
+  PARTNAME := xc7k325tffg900-2
 else ifeq ($(TARGET),nexys4ddr)
   DEVICE := xc7a100t_test
   BITSTREAM_DEVICE := artix7

docs/building-examples.rst

@@ -15,7 +15,7 @@ Select your FPGA family:
 
 .. tabs::
 
-   .. group-tab:: Artix-7
+   .. group-tab:: Artix-7, Kintex-7
 
       .. code-block:: bash
          :name: fpga-fam-xc7
@@ -33,7 +33,7 @@ Next, prepare the environment:
 
 .. tabs::
 
-   .. group-tab:: Artix-7
+   .. group-tab:: Artix-7, Kintex-7
 
       .. code-block:: bash
          :name: conda-prep-env-xc7
@@ -104,6 +104,19 @@ Enter the directory that contains examples for Xilinx 7-Series FPGAs:
    :file: templates/example.jinja
 
 
+
+Additional Examples
+-------------------
+
+In addition to the designs we have gone over here, you can also find several other exciting designs
+for the basys3 board in the additional_examples directory:
+
+.. code-block:: bash
+   :name: additional_examples
+
+   cd additional_examples
+
+
 QuickLogic EOS S3
 =================
 

docs/collect_readmes.py

@@ -4,6 +4,7 @@
 full_name_lut = {
     'a35t': 'Arty 35T',
     'a100t': 'Arty 100T',
+    'genesys2': 'Genesys 2',
     'nexys4ddr': 'Nexys 4 DDR',
     'basys3': 'Basys 3',
     'eos_s3': 'EOS S3',

docs/customizing-makefiles.rst

@@ -121,6 +121,8 @@ is from lines 9-39 of :gh:`the Makefile from counter test <chipsalliance/f4pga-e
       XDC := ${current_dir}/arty.xdc
    else ifeq ($(TARGET),arty_100)
       XDC := ${current_dir}/arty.xdc
+   else ifeq ($(TARGET),genesys2)
+      XDC := ${current_dir}/genesys2.xdc
    else ifeq ($(TARGET),nexys4ddr)
       XDC := ${current_dir}/nexys4ddr.xdc
    else ifeq ($(TARGET),zybo)

docs/getting.rst

@@ -93,7 +93,7 @@ Select your target FPGA family:
 
 .. tabs::
 
-   .. group-tab:: Artix-7
+   .. group-tab:: Artix-7, Kintex-7
 
       .. code-block:: bash
          :name: fpga-fam-xc7
@@ -120,7 +120,7 @@ Download architecture definitions:
 
 .. tabs::
 
-   .. group-tab:: Artix-7
+   .. group-tab:: Artix-7, Kintex-7
 
       .. code-block:: bash
          :name: download-arch-def-xc7
@@ -145,5 +145,5 @@ If the above commands exited without errors, you have successfully installed and
   With the toolchain installed, you are ready to build the example designs!
   Examples are provided in separated directories:
 
-  * Subdir :ghsrc:`xc7` for the Artix-7 devices
+  * Subdir :ghsrc:`xc7` for the Artix-7 and Kintex-7 devices
   * Subdir :ghsrc:`eos-s3` for the EOS S3 devices

docs/index.rst

@@ -5,7 +5,7 @@ This guide explains how to get started with F4PGA and build example designs from
 GitHub repository.
 It currently focuses on the following FPGA families:
 
-- Artix-7 from Xilinx,
+- Artix-7 and Kintex-7 from Xilinx,
 - EOS S3 from QuickLogic.
 
 Follow this guide to:

docs/personal-designs.rst

@@ -79,6 +79,13 @@ Then, depending on your board type run:
 
          TARGET="arty_100" make -C .
 
+   .. group-tab:: Genesys2
+
+      .. code-block:: bash
+         :name: example-counter-genesys2-group
+
+         TARGET="genesys2" make -C .
+
    .. group-tab:: Nexus4
 
       .. code-block:: bash
@@ -115,7 +122,7 @@ If your design builds without error, the bitstream can be found in the following
    cd build/<board>
 
 Once you navigate to the directory containing the bitstream, use the following commands on the
-**Arty and Basys3** to upload the design to your board. Make sure to change ``top.bit`` to the
+**Arty, Basys3, and Genesys2** to upload the design to your board. Make sure to change ``top.bit`` to the
 name you used for your top level module:
 
 .. code-block:: bash

xc7/README.rst

@@ -1,7 +1,7 @@
 F4PGA Toolchain Examples for Xilinx 7 Series
 ============================================
 
-#. ``counter`` - simple 4-bit counter driving LEDs. The design targets the `Basys3 board <https://store.digilentinc.com/basys-3-artix-7-fpga-trainer-board-recommended-for-introductory-users/>`__, the `Arty boards <https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists/>`__, and the `Zybo Z7 board <https://store.digilentinc.com/zybo-z7-zynq-7000-arm-fpga-soc-development-board/>`__
+#. ``counter`` - simple counter driving LEDs. The design targets the `Basys3 board <https://store.digilentinc.com/basys-3-artix-7-fpga-trainer-board-recommended-for-introductory-users/>`__, the `Arty boards <https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists/>`__, the `Genesys2 boards <https://digilent.com/shop/genesys-2-kintex-7-fpga-development-board/>`__, and the `Zybo Z7 board <https://store.digilentinc.com/zybo-z7-zynq-7000-arm-fpga-soc-development-board/>`__
 #. ``picosoc`` - `picorv32 <https://github.com/cliffordwolf/picorv32>`__ based SoC. The design targets the `Basys3 board <https://store.digilentinc.com/basys-3-artix-7-fpga-trainer-board-recommended-for-introductory-users/>`__.
 #. ``litex`` - Series of `LiteX-based <https://github.com/enjoy-digital/litex>`__ designs, that feature different CPU types and LiteX modules.
 #. ``linux_litex`` - `LiteX <https://github.com/enjoy-digital/litex>`__ based system with Linux capable `VexRiscv core <https://github.com/SpinalHDL/VexRiscv>`__. The design includes `DDR <https://github.com/enjoy-digital/litedram>`__ and `Ethernet <https://github.com/enjoy-digital/liteeth>`__ controllers. The design targets the `Arty boards <https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists/>`__.

xc7/counter_test/Makefile

@@ -6,6 +6,9 @@ ifeq ($(TARGET),arty_35)
   XDC := ${current_dir}/arty.xdc
 else ifeq ($(TARGET),arty_100)
   XDC := ${current_dir}/arty.xdc
+else ifeq ($(TARGET),genesys2)
+  XDC := ${current_dir}/genesys2.xdc
+  SOURCES := ${current_dir}/counter_genesys2.v
 else ifeq ($(TARGET),nexys4ddr)
   XDC := ${current_dir}/nexys4ddr.xdc
 else ifeq ($(TARGET),zybo)

xc7/counter_test/README.rst

@@ -15,6 +15,10 @@ counter example, depending on your hardware, run:
 
    TARGET="arty_100" make -C counter_test
 
+.. code-block:: bash
+   :name: example-counter-genesys2-group
+
+   TARGET="genesys2" make -C counter_test
 
 .. code-block:: bash
    :name: example-counter-nexys4ddr-group
@@ -45,7 +49,7 @@ At completion, the bitstreams are located in the build directory:
 
    counter_test/build/<board>
 
-Now, for **Arty and Basys3**, you can upload the design with:
+Now, for **Arty, Basys3, and Genesys2**, you can upload the design with:
 
 .. code-block:: bash
 

xc7/counter_test/counter_genesys2.v

@@ -0,0 +1,26 @@
+`default_nettype none //enforce explicit declaration of nets
+
+module top (
+    input  wire       clk_p,
+    input  wire       clk_n,
+    output wire [7:0] led
+);
+
+  localparam BITS = 8;
+  localparam LOG2DELAY = 22;
+
+  wire clk_ibufg;
+  IBUFGDS clk_ibufgds_inst(
+    .I(clk_p),
+    .IB(clk_n),
+    .O(clk_ibufg)
+  );
+
+  reg [BITS+LOG2DELAY-1:0] counter = 0;
+
+  always @(posedge clk_ibufg) begin
+    counter <= counter + 1;
+  end
+
+  assign led[7:0] = counter >> LOG2DELAY;
+endmodule

xc7/counter_test/genesys2.xdc

@@ -0,0 +1,17 @@
+# Clock pin
+set_property -dict { PACKAGE_PIN AD11  IOSTANDARD LVDS     } [get_ports { clk_n }]; #IO_L12N_T1_MRCC_33 Sch=sysclk_n
+set_property -dict { PACKAGE_PIN AD12  IOSTANDARD LVDS     } [get_ports { clk_p }]; #IO_L12P_T1_MRCC_33 Sch=sysclk_p
+
+# LEDs
+set_property -dict { PACKAGE_PIN T28   IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L11N_T1_SRCC_14 Sch=led[0]
+set_property -dict { PACKAGE_PIN V19   IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L19P_T3_A10_D26_14 Sch=led[1]
+set_property -dict { PACKAGE_PIN U30   IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[2]
+set_property -dict { PACKAGE_PIN U29   IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=led[3]
+set_property -dict { PACKAGE_PIN V20   IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=led[4]
+set_property -dict { PACKAGE_PIN V26   IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L16P_T2_CSI_B_14 Sch=led[5]
+set_property -dict { PACKAGE_PIN W24   IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L20N_T3_A07_D23_14 Sch=led[6]
+set_property -dict { PACKAGE_PIN W23   IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L20P_T3_A08_D24_14 Sch=led[7]
+
+# Clock constraints
+create_clock -period 10.0 [get_ports {clk_n}]
+create_clock -period 10.0 [get_ports {clk_p}]