Ryzen 9 7950X #378
Labels
Comments
|
|
|
|
Need a 7000 owner to test this version: Buid,run, and post the output of |
|
Getting the Line 1571 in aa3d63e For example, Zen2 case Using zencli need someone to read SMU at address |
cyring
added a commit
that referenced
this issue
Dec 9, 2022
Voltage Core issue
EDIT: Incoming tests
|
|
7950x : Is it possible to find the DIMM temperatures somewhere? |
|
@Jon0 Thank you very much, I'm processing your data.
It's not implemented in CoreFreq. |
Thanks to your dump, I'm attempting to better compute Memory Clocks.
make ARCH_PMC=UMC clean all
You may or not get the
Thank you! |
|
I had some issues with the develop branch when starting the daemon - compile works and insmod reported success: Tested with stock arch kernel: Also note master does the same thing when I build with |
Is this something you didn't have in your previous runs using the Do you have another driver which could also make use of PS: I'm back with the stock arch kernel So I will suggest you remove the HSMP capability for 7950X, changing this block as below. Line 6663 in 1d9e27e {
.Brand = ZLIST("AMD Ryzen 9 7950X"),
.Boost = {+12, +1},
.Param.Offset = {0, 0, 0},
.CodeNameIdx = CN_RAPHAEL,
.TgtRatioUnlocked = 1,
.ClkRatioUnlocked = 0b10,
.TurboUnlocked = 1,
.UncoreUnlocked = 0,
.HSMP_Capable = 0,
.Latch=LATCH_TGT_RATIO_UNLOCK|LATCH_CLK_RATIO_UNLOCK|LATCH_TURBO_UNLOCK\
|LATCH_HSMP_CAPABLE
}, |
|
I found the issue was I ran Here is the screenshots: |
|
|
|
Frequency is not quite right, I tested a few settings in bios: Actual Bios Setting -> CoreFreq Display Freq Don't see Data Fabric in bios unless its hidden somewhere... |
Do CPU-Z, HWINFO, or OCCT reports the Mem Clock as left in BIOS : screenshots please ? |
|
@Jon0 The first 16 bits of hexadecimal value This is the major change with Zen versions 1, 2, and 3 where DDR4 is encoded as a frequency ratio of 2 digits within bits [6-0] |
# ./zencli smu 0x50200
[0x00050200] READ(smu) = 0x40010960 (1073809760)
60 56 52 48 44 40 36 32 28 24 20 16 12 08 04 00
0000 0000 0000 0000 0000 0000 0000 0000 0100 0000 0000 0001 0000 1001 0110 0000Mistake is mine: So we can use the same algorithm when DRAM is unconditionally of DDR5 kind. |
|
Yep heres another when I set 2000M/T in bios (lowest it can go) I don't have a windows install available right now to check other software, but the above formula does look correct |
Thanks, You can now pull and try the latest code of The impacted items are the followings in "Processor" window:
in "Package cycles" view
in "Memory Controller" window
For your information, my Zen3+ decoded results I have searched some 7900X BIOS screenshots and found that |
|
|
Sure. Here you go. |
|
So is the primary terminal view supposed to show voltage? All mine shows is 0.0 in the bottom right corner.
|
This voltage aggregation is not programmed yet for Zen4 About the UMC something is odd, it has been working with @Jon0 @Jon0 : can you please pull latest |
|
@KeithMyers : can you build as below and tell if UMC is showing up ? make ARCH_PMC=UMC clean all |
I guess I need to go reread the docs. What menu?? I don't see any menu or prompts for keystrokes to pull up a menu from the cli view. I know you can use a command parameter to show voltages. But haven't figured out how to do anything in the cli terminal "top"- like view. |
Maybe doesn't work because of all the build errors? |
|
Menus are opened using function keys Except the To avoid API mismatch, you have to uninstall any previous CoreFreq package of your distribution, if any. Using the For the driver
For the daemon
For the client
In Github, use 3 anti-quotes before and after the code you're pasting. |
|
Actually disabling SMT is what I want because I am working in an enviroment which is required to be low latency.that is why I also disable cpu-idle driver So you think it is just problem about reading UMC sensors or memory controller not working properly. |
|
I haven't seen any indications of memory instability at stock EXPO II timings using a G.Skill 2 X 16GB kit at 6000Mhz. I just think the Corefreq driver just doesn't see the UMC with kernels less than 6.x |
|
I finally found the latency problem is about iommu , absolutely need to disable it . |
Raphael UMC entry is the function Line 6756 in 509ab79 Callflow is a low level access, direct to Registers, kernel can't beat with that. You can try to dump the UMC from zencli but this user-space software still needs adaptations to support 7950X.
const unsigned int CHIP_BAR[2][2] = {
[0] = {
[0] = UMC_BAR[cha] + 0x0,
[1] = UMC_BAR[cha] + 0x20
},
[1] = {
[0] = UMC_BAR[cha] + 0x10,
[1] = UMC_BAR[cha] + 0x30
}
};
cc zencli.c -o zencli
./zencli umc |
|
Here is zencli with the modified code in UMC_Read at line 630. |
Thank you. If it was run with kernel 5, is it now possible to run it with kernel 6 ? |
|
I'd have to load one of the 6.x kernels again. Hit and miss finding a kernel with Nvidia driver support. Just a FYI. I also ran with the unmodified zencli and the original mask at 0x28 has more output. Still doesn't find any DIMMS though with kernel 5. |
|
Here is the modified zencli output on kernel 6.3.0-rc6 |
|
Here is the master built on kernel 6.3.5. Wouldn't insert the driver built on the previous make built on kernel 5.19. Said the symbols were incorrect. |
|
So somehow corefreq can't access the UMC properly on 5.x kernels, yet can on 6.x kernels |
I have to refactor UMC decoding in zencli to match the CoreFreq driver one. |
|
What's new in kernel 6 which allows the SMU to provide more bits to help decoding the UMC ? That's what I'm looking for. |
|
With kernel 6, do you have an |
No, I don't. |
|
CoreFreq is really similar to Does it make a difference with and without |
|
I tried blacklisting that for you once or twice before and it never made a difference. |
|
Do you have in kernel log, something about the following base address |
I couldn't find any elements related to ANY term in your post in my kern.logs. In fact, couldn't find any of your terms in ANY log. |
|
Thank you. Keeping track in Wiki 7950X About new topology from CPUID extension, it's too early to program it in CoreFreq, data don't show something about E-core(s) yet. |
|
Thank you for your amazing work. |
#378 (comment) is where we started digging for voltages from known addresses.
|
|
@cyring well how can i help with the first item "Scan and read addresses"? |
|
Hello, I have a null temperature issue among Zen4 models. Line 208 in 87344fa and replace code with this one: #define SMU_AMD_THM_TCTL_CCD_REGISTER_F19H_61H \
(SMU_AMD_THM_TCTL_REGISTER_F17H + 0x300)Next rebuild, unload, reload and test for temperature of your 7950X Thanks |
|
Hello @cyring I get constant temperature 27C with the patch. But it works just fine without the patch |
Thank you for your attempts
In CoreFreq, with EPYC Genoa, the Thermal register address differs of an |
|
Genoa temperature function is now working. |
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
zerofixed.Architecture is Zen4The text was updated successfully, but these errors were encountered: