Updated to create modelsim.ini file such that VHDL files also works with libraries #93
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The purpose of this PR is to make it possible to compile VHDL files too when using libraries. For Verilog files the libraries can simply be listed using the
-Loption to thevlogcommand. Unfortunately, such functionality does not exist when compiling VHDL files. Instead, it is necessary to use amodelsim.inifile where the library mapping is specified.The change introduces a new command to the Questa flow that creates a
modelsim.inifile by calling thevmapcommand specifying the absolute path to the compiled library as well as the symbolic name.