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JIT ARM64-SVE: Add BitwiseClear and BooleanNot #101853

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May 7, 2024
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JIT ARM64-SVE: Add BitwiseClear and BooleanNot #101853

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25 changes: 20 additions & 5 deletions src/coreclr/jit/emitarm64sve.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3602,12 +3602,7 @@ void emitter::emitInsSve_R_R_R(instruction ins,
fmt = IF_SVE_GW_3A;
break;

case INS_sve_clz:
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The asserts for these instructions were wrong - it allowed cases that don't exist.

case INS_sve_cls:
case INS_sve_cnt:
case INS_sve_cnot:
case INS_sve_not:
case INS_sve_nots:
if (isPredicateRegister(reg1) && sopt != INS_SCALABLE_OPTS_UNPREDICATED)
{
assert(opt == INS_OPTS_SCALABLE_B);
Expand All @@ -3627,6 +3622,26 @@ void emitter::emitInsSve_R_R_R(instruction ins,
}
break;

case INS_sve_nots:
assert(opt == INS_OPTS_SCALABLE_B);
assert(isPredicateRegister(reg1)); // DDDD
assert(isPredicateRegister(reg2)); // gggg
assert(isPredicateRegister(reg3)); // NNNN
fmt = IF_SVE_CZ_4A;
break;

case INS_sve_clz:
case INS_sve_cls:
case INS_sve_cnt:
case INS_sve_cnot:
assert(isVectorRegister(reg1));
assert(isLowPredicateRegister(reg2));
assert(isVectorRegister(reg3));
assert(insOptsScalableStandard(opt));
assert(insScalableOptsNone(sopt));
fmt = IF_SVE_AP_3A;
break;

case INS_sve_fabs:
case INS_sve_fneg:
assert(isVectorRegister(reg1));
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2 changes: 2 additions & 0 deletions src/coreclr/jit/hwintrinsiclistarm64sve.h
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Expand Up @@ -22,6 +22,8 @@ HARDWARE_INTRINSIC(Sve, Add,
HARDWARE_INTRINSIC(Sve, AddAcross, -1, 1, true, {INS_sve_saddv, INS_sve_uaddv, INS_sve_saddv, INS_sve_uaddv, INS_sve_saddv, INS_sve_uaddv, INS_sve_uaddv, INS_sve_uaddv, INS_sve_faddv, INS_sve_faddv}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_BaseTypeFromFirstArg|HW_Flag_EmbeddedMaskedOperation)
HARDWARE_INTRINSIC(Sve, And, -1, -1, false, {INS_sve_and, INS_sve_and, INS_sve_and, INS_sve_and, INS_sve_and, INS_sve_and, INS_sve_and, INS_sve_and, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_OptionalEmbeddedMaskedOperation|HW_Flag_HasRMWSemantics|HW_Flag_LowMaskedOperation)
HARDWARE_INTRINSIC(Sve, AndAcross, -1, -1, false, {INS_sve_andv, INS_sve_andv, INS_sve_andv, INS_sve_andv, INS_sve_andv, INS_sve_andv, INS_sve_andv, INS_sve_andv, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_LowMaskedOperation)
HARDWARE_INTRINSIC(Sve, BitwiseClear, -1, -1, false, {INS_sve_bic, INS_sve_bic, INS_sve_bic, INS_sve_bic, INS_sve_bic, INS_sve_bic, INS_sve_bic, INS_sve_bic, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_OptionalEmbeddedMaskedOperation|HW_Flag_HasRMWSemantics|HW_Flag_LowMaskedOperation)
HARDWARE_INTRINSIC(Sve, BooleanNot, -1, -1, false, {INS_sve_cnot, INS_sve_cnot, INS_sve_cnot, INS_sve_cnot, INS_sve_cnot, INS_sve_cnot, INS_sve_cnot, INS_sve_cnot, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_LowMaskedOperation)
HARDWARE_INTRINSIC(Sve, ConditionalSelect, -1, 3, true, {INS_sve_sel, INS_sve_sel, INS_sve_sel, INS_sve_sel, INS_sve_sel, INS_sve_sel, INS_sve_sel, INS_sve_sel, INS_sve_sel, INS_sve_sel}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_ExplicitMaskedOperation|HW_Flag_SupportsContainment)
HARDWARE_INTRINSIC(Sve, Count16BitElements, 0, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_cnth, INS_invalid, INS_invalid, INS_invalid}, HW_Category_Scalar, HW_Flag_Scalable|HW_Flag_HasEnumOperand|HW_Flag_SpecialCodeGen|HW_Flag_NoFloatingPointUsed)
HARDWARE_INTRINSIC(Sve, Count32BitElements, 0, 1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_cntw, INS_invalid, INS_invalid, INS_invalid}, HW_Category_Scalar, HW_Flag_Scalable|HW_Flag_HasEnumOperand|HW_Flag_SpecialCodeGen|HW_Flag_NoFloatingPointUsed)
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158 changes: 158 additions & 0 deletions ...ries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.PlatformNotSupported.cs
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Original file line number Diff line number Diff line change
Expand Up @@ -353,6 +353,164 @@ internal Arm64() { }
public static unsafe Vector<ulong> AndAcross(Vector<ulong> value) { throw new PlatformNotSupportedException(); }


/// BitwiseClear : Bitwise clear

/// <summary>
/// svuint8_t svbic[_u8]_m(svbool_t pg, svuint8_t op1, svuint8_t op2)
/// svuint8_t svbic[_u8]_x(svbool_t pg, svuint8_t op1, svuint8_t op2)
/// svuint8_t svbic[_u8]_z(svbool_t pg, svuint8_t op1, svuint8_t op2)
/// BIC Ztied1.B, Pg/M, Ztied1.B, Zop2.B
/// BIC Zresult.D, Zop1.D, Zop2.D
/// svbool_t svbic[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2)
/// BIC Presult.B, Pg/Z, Pop1.B, Pop2.B
/// </summary>
public static unsafe Vector<byte> BitwiseClear(Vector<byte> left, Vector<byte> right) { throw new PlatformNotSupportedException(); }

/// <summary>
/// svint16_t svbic[_s16]_m(svbool_t pg, svint16_t op1, svint16_t op2)
/// svint16_t svbic[_s16]_x(svbool_t pg, svint16_t op1, svint16_t op2)
/// svint16_t svbic[_s16]_z(svbool_t pg, svint16_t op1, svint16_t op2)
/// BIC Ztied1.H, Pg/M, Ztied1.H, Zop2.H
/// BIC Zresult.D, Zop1.D, Zop2.D
/// svbool_t svbic[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2)
/// BIC Presult.B, Pg/Z, Pop1.B, Pop2.B
/// </summary>
public static unsafe Vector<short> BitwiseClear(Vector<short> left, Vector<short> right) { throw new PlatformNotSupportedException(); }

/// <summary>
/// svint32_t svbic[_s32]_m(svbool_t pg, svint32_t op1, svint32_t op2)
/// svint32_t svbic[_s32]_x(svbool_t pg, svint32_t op1, svint32_t op2)
/// svint32_t svbic[_s32]_z(svbool_t pg, svint32_t op1, svint32_t op2)
/// BIC Ztied1.S, Pg/M, Ztied1.S, Zop2.S
/// BIC Zresult.D, Zop1.D, Zop2.D
/// svbool_t svbic[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2)
/// BIC Presult.B, Pg/Z, Pop1.B, Pop2.B
/// </summary>
public static unsafe Vector<int> BitwiseClear(Vector<int> left, Vector<int> right) { throw new PlatformNotSupportedException(); }

/// <summary>
/// svint64_t svbic[_s64]_m(svbool_t pg, svint64_t op1, svint64_t op2)
/// svint64_t svbic[_s64]_x(svbool_t pg, svint64_t op1, svint64_t op2)
/// svint64_t svbic[_s64]_z(svbool_t pg, svint64_t op1, svint64_t op2)
/// BIC Ztied1.D, Pg/M, Ztied1.D, Zop2.D
/// BIC Zresult.D, Zop1.D, Zop2.D
/// svbool_t svbic[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2)
/// BIC Presult.B, Pg/Z, Pop1.B, Pop2.B
/// </summary>
public static unsafe Vector<long> BitwiseClear(Vector<long> left, Vector<long> right) { throw new PlatformNotSupportedException(); }

/// <summary>
/// svint8_t svbic[_s8]_m(svbool_t pg, svint8_t op1, svint8_t op2)
/// svint8_t svbic[_s8]_x(svbool_t pg, svint8_t op1, svint8_t op2)
/// svint8_t svbic[_s8]_z(svbool_t pg, svint8_t op1, svint8_t op2)
/// BIC Ztied1.B, Pg/M, Ztied1.B, Zop2.B
/// BIC Zresult.D, Zop1.D, Zop2.D
/// svbool_t svbic[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2)
/// BIC Presult.B, Pg/Z, Pop1.B, Pop2.B
/// </summary>
public static unsafe Vector<sbyte> BitwiseClear(Vector<sbyte> left, Vector<sbyte> right) { throw new PlatformNotSupportedException(); }

/// <summary>
/// svuint16_t svbic[_u16]_m(svbool_t pg, svuint16_t op1, svuint16_t op2)
/// svuint16_t svbic[_u16]_x(svbool_t pg, svuint16_t op1, svuint16_t op2)
/// svuint16_t svbic[_u16]_z(svbool_t pg, svuint16_t op1, svuint16_t op2)
/// BIC Ztied1.H, Pg/M, Ztied1.H, Zop2.H
/// BIC Zresult.D, Zop1.D, Zop2.D
/// svbool_t svbic[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2)
/// BIC Presult.B, Pg/Z, Pop1.B, Pop2.B
/// </summary>
public static unsafe Vector<ushort> BitwiseClear(Vector<ushort> left, Vector<ushort> right) { throw new PlatformNotSupportedException(); }

/// <summary>
/// svuint32_t svbic[_u32]_m(svbool_t pg, svuint32_t op1, svuint32_t op2)
/// svuint32_t svbic[_u32]_x(svbool_t pg, svuint32_t op1, svuint32_t op2)
/// svuint32_t svbic[_u32]_z(svbool_t pg, svuint32_t op1, svuint32_t op2)
/// BIC Ztied1.S, Pg/M, Ztied1.S, Zop2.S
/// BIC Zresult.D, Zop1.D, Zop2.D
/// svbool_t svbic[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2)
/// BIC Presult.B, Pg/Z, Pop1.B, Pop2.B
/// </summary>
public static unsafe Vector<uint> BitwiseClear(Vector<uint> left, Vector<uint> right) { throw new PlatformNotSupportedException(); }

/// <summary>
/// svuint64_t svbic[_u64]_m(svbool_t pg, svuint64_t op1, svuint64_t op2)
/// svuint64_t svbic[_u64]_x(svbool_t pg, svuint64_t op1, svuint64_t op2)
/// svuint64_t svbic[_u64]_z(svbool_t pg, svuint64_t op1, svuint64_t op2)
/// BIC Ztied1.D, Pg/M, Ztied1.D, Zop2.D
/// BIC Zresult.D, Zop1.D, Zop2.D
/// svbool_t svbic[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2)
/// BIC Presult.B, Pg/Z, Pop1.B, Pop2.B
/// </summary>
public static unsafe Vector<ulong> BitwiseClear(Vector<ulong> left, Vector<ulong> right) { throw new PlatformNotSupportedException(); }


/// BooleanNot : Logically invert boolean condition

/// <summary>
/// svuint8_t svcnot[_u8]_m(svuint8_t inactive, svbool_t pg, svuint8_t op)
/// svuint8_t svcnot[_u8]_x(svbool_t pg, svuint8_t op)
/// svuint8_t svcnot[_u8]_z(svbool_t pg, svuint8_t op)
/// CNOT Ztied.B, Pg/M, Zop.B
/// </summary>
public static unsafe Vector<byte> BooleanNot(Vector<byte> value) { throw new PlatformNotSupportedException(); }

/// <summary>
/// svint16_t svcnot[_s16]_m(svint16_t inactive, svbool_t pg, svint16_t op)
/// svint16_t svcnot[_s16]_x(svbool_t pg, svint16_t op)
/// svint16_t svcnot[_s16]_z(svbool_t pg, svint16_t op)
/// CNOT Ztied.H, Pg/M, Zop.H
/// </summary>
public static unsafe Vector<short> BooleanNot(Vector<short> value) { throw new PlatformNotSupportedException(); }

/// <summary>
/// svint32_t svcnot[_s32]_m(svint32_t inactive, svbool_t pg, svint32_t op)
/// svint32_t svcnot[_s32]_x(svbool_t pg, svint32_t op)
/// svint32_t svcnot[_s32]_z(svbool_t pg, svint32_t op)
/// CNOT Ztied.S, Pg/M, Zop.S
/// </summary>
public static unsafe Vector<int> BooleanNot(Vector<int> value) { throw new PlatformNotSupportedException(); }

/// <summary>
/// svint64_t svcnot[_s64]_m(svint64_t inactive, svbool_t pg, svint64_t op)
/// svint64_t svcnot[_s64]_x(svbool_t pg, svint64_t op)
/// svint64_t svcnot[_s64]_z(svbool_t pg, svint64_t op)
/// CNOT Ztied.D, Pg/M, Zop.D
/// </summary>
public static unsafe Vector<long> BooleanNot(Vector<long> value) { throw new PlatformNotSupportedException(); }

/// <summary>
/// svint8_t svcnot[_s8]_m(svint8_t inactive, svbool_t pg, svint8_t op)
/// svint8_t svcnot[_s8]_x(svbool_t pg, svint8_t op)
/// svint8_t svcnot[_s8]_z(svbool_t pg, svint8_t op)
/// CNOT Ztied.B, Pg/M, Zop.B
/// </summary>
public static unsafe Vector<sbyte> BooleanNot(Vector<sbyte> value) { throw new PlatformNotSupportedException(); }

/// <summary>
/// svuint16_t svcnot[_u16]_m(svuint16_t inactive, svbool_t pg, svuint16_t op)
/// svuint16_t svcnot[_u16]_x(svbool_t pg, svuint16_t op)
/// svuint16_t svcnot[_u16]_z(svbool_t pg, svuint16_t op)
/// CNOT Ztied.H, Pg/M, Zop.H
/// </summary>
public static unsafe Vector<ushort> BooleanNot(Vector<ushort> value) { throw new PlatformNotSupportedException(); }

/// <summary>
/// svuint32_t svcnot[_u32]_m(svuint32_t inactive, svbool_t pg, svuint32_t op)
/// svuint32_t svcnot[_u32]_x(svbool_t pg, svuint32_t op)
/// svuint32_t svcnot[_u32]_z(svbool_t pg, svuint32_t op)
/// CNOT Ztied.S, Pg/M, Zop.S
/// </summary>
public static unsafe Vector<uint> BooleanNot(Vector<uint> value) { throw new PlatformNotSupportedException(); }

/// <summary>
/// svuint64_t svcnot[_u64]_m(svuint64_t inactive, svbool_t pg, svuint64_t op)
/// svuint64_t svcnot[_u64]_x(svbool_t pg, svuint64_t op)
/// svuint64_t svcnot[_u64]_z(svbool_t pg, svuint64_t op)
/// CNOT Ztied.D, Pg/M, Zop.D
/// </summary>
public static unsafe Vector<ulong> BooleanNot(Vector<ulong> value) { throw new PlatformNotSupportedException(); }


/// ConditionalSelect : Conditionally select elements

/// <summary>
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