Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Optimize Vector128<long> multiplication for arm64 #104177

Merged
merged 8 commits into from
Jul 2, 2024

Conversation

EgorBo
Copy link
Member

@EgorBo EgorBo commented Jun 28, 2024

Follow up to #103555 for arm64

@dotnet-issue-labeler dotnet-issue-labeler bot added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label Jun 28, 2024
@EgorBo
Copy link
Member Author

EgorBo commented Jun 28, 2024

@EgorBot -arm64 -profiler

using System.IO.Hashing;
using BenchmarkDotNet.Attributes;

public class Bench
{
    static readonly byte[] Data = new byte[1000000];

    [Benchmark]
    public byte[] BenchXxHash128()
    {
        XxHash128 hash = new();
        hash.Append(Data);
        return hash.GetHashAndReset();
    }
}

Copy link
Contributor

Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch
See info in area-owners.md if you want to be subscribed.

Comment on lines 21932 to 21957
case TYP_LONG:
case TYP_ULONG:
{
assert(simdSize == 16);

// Make op1 and op2 multi-use:
GenTree* op1Dup = fgMakeMultiUse(&op1);
GenTree* op2Dup = fgMakeMultiUse(&op2);

// long left0 = op1.GetElement(0)
// long left1 = op1.GetElement(1)
GenTree* left0 = gtNewSimdGetElementNode(TYP_LONG, op1, gtNewIconNode(0), simdBaseJitType, 16);
GenTree* left1 = gtNewSimdGetElementNode(TYP_LONG, op1Dup, gtNewIconNode(1), simdBaseJitType, 16);

// long right0 = op2.GetElement(0)
// long right1 = op2.GetElement(1)
GenTree* right0 = gtNewSimdGetElementNode(TYP_LONG, op2, gtNewIconNode(0), simdBaseJitType, 16);
GenTree* right1 = gtNewSimdGetElementNode(TYP_LONG, op2Dup, gtNewIconNode(1), simdBaseJitType, 16);

// Vector128<long> vec = Vector128.Create(left0 * right0, left1 * right1)
op1 = gtNewOperNode(GT_MUL, TYP_LONG, left0, right0);
op2 = gtNewOperNode(GT_MUL, TYP_LONG, left1, right1);
GenTree* vec = gtNewSimdCreateScalarUnsafeNode(TYP_SIMD16, op1, simdBaseJitType, 16);
return gtNewSimdHWIntrinsicNode(TYP_SIMD16, vec, gtNewIconNode(1), op2, NI_AdvSimd_Insert,
simdBaseJitType, 16);
}
Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Is this just avoiding the cost of inlining, unrolling, and simplifying the work the JIT would have to do?

@EgorBot
Copy link

EgorBot commented Jun 28, 2024

Benchmark results on Arm64
BenchmarkDotNet v0.13.12, Ubuntu 22.04.4 LTS (Jammy Jellyfish)
Unknown processor
  Job-OMCIXQ : .NET 9.0.0 (42.42.42.42424), Arm64 RyuJIT AdvSIMD
  Job-KTSNVH : .NET 9.0.0 (42.42.42.42424), Arm64 RyuJIT AdvSIMD
Method Toolchain Mean Error Ratio
BenchXxHash128 Main 116.9 μs 0.05 μs 1.00
BenchXxHash128 PR 109.8 μs 0.04 μs 0.94

BDN_Artifacts.zip

Flame graphs: Main vs PR 🔥
Hot asm: Main vs PR
Hot functions: Main vs PR

For clean perf results, make sure you have just one [Benchmark] in your app.

@neon-sunset
Copy link
Contributor

neon-sunset commented Jul 1, 2024

I wanted to ask is there a reason LLVM's codegen variant did not work? On some cores, UMOV/SMOV has pretty bad latency vs code that avoids a round-trip to scalar registers.

Comment on lines 22005 to 22006
return gtNewSimdHWIntrinsicNode(type, vec, gtNewIconNode(1), op2, NI_AdvSimd_Insert,
simdBaseJitType, 16);
Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

nit: Use gtNewSimdWithElementNode(type, vec, gtNewIconNode(1), op2, simdBaseJitType, simdSize) which ensures all the optimal handling takes place.

Copy link
Member Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Thanks! Applied

@EgorBo EgorBo marked this pull request as ready for review July 2, 2024 18:03
@EgorBo EgorBo merged commit 6e039a8 into dotnet:main Jul 2, 2024
104 of 107 checks passed
@EgorBo EgorBo deleted the mul-long-arm64 branch July 2, 2024 18:03
Comment on lines +21981 to +21982
op1 = gtNewBitCastNode(TYP_LONG, op1);
op2 = gtNewBitCastNode(TYP_LONG, op2);
Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Why bitcast instead of ToScalar? If this is generating better code, it seems like a pretty "core" scenario we're not handling from the ToScalar path

Copy link
Member Author

@EgorBo EgorBo Jul 2, 2024

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

@tannergooding because op2 can be either 8-byte TYP_SIMD8 or 8-byte scalar (TYP_LONG) so bitcast allowed me to simplify handling. In my initial version I forgot that this path is used for both MUL(vector, vector) and MUL(vector, scalar) (where scalar is broadcasted)

Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Ah, that makes sense, 👍

@github-actions github-actions bot locked and limited conversation to collaborators Aug 2, 2024
Sign up for free to subscribe to this conversation on GitHub. Already have an account? Sign in.
Labels
area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI
Projects
None yet
Development

Successfully merging this pull request may close these issues.

4 participants