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Implement Shift and Inserts scalar and SIMD intrinsics. #36818

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Jun 11, 2020
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Implement Shift and Inserts scalar and SIMD intrinsics. #36818

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2 changes: 1 addition & 1 deletion src/coreclr/src/jit/hwintrinsic.h
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Expand Up @@ -104,7 +104,7 @@ enum HWIntrinsicFlag : unsigned int
HW_Flag_NoRMWSemantics = 0x4000,

// NoContainment
// the intrinsic cannot be handled by comtainment,
// the intrinsic cannot be handled by containment,
// all the intrinsic that have explicit memory load/store semantics should have this flag
HW_Flag_NoContainment = 0x8000,

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4 changes: 4 additions & 0 deletions src/coreclr/src/jit/hwintrinsicarm64.cpp
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Expand Up @@ -218,6 +218,8 @@ void HWIntrinsicInfo::lookupImmBounds(
break;

case NI_AdvSimd_ShiftLeftLogical:
case NI_AdvSimd_ShiftLeftLogicalAndInsert:
case NI_AdvSimd_ShiftLeftLogicalAndInsertScalar:
case NI_AdvSimd_ShiftLeftLogicalSaturate:
case NI_AdvSimd_ShiftLeftLogicalSaturateScalar:
case NI_AdvSimd_ShiftLeftLogicalSaturateUnsigned:
Expand All @@ -231,6 +233,7 @@ void HWIntrinsicInfo::lookupImmBounds(
immUpperBound = BITS_PER_BYTE * genTypeSize(baseType) - 1;
break;

case NI_AdvSimd_ShiftRightAndInsert:
case NI_AdvSimd_ShiftRightArithmetic:
case NI_AdvSimd_ShiftRightArithmeticAdd:
case NI_AdvSimd_ShiftRightArithmeticAddScalar:
Expand All @@ -250,6 +253,7 @@ void HWIntrinsicInfo::lookupImmBounds(
case NI_AdvSimd_ShiftRightLogical:
case NI_AdvSimd_ShiftRightLogicalAdd:
case NI_AdvSimd_ShiftRightLogicalAddScalar:
case NI_AdvSimd_ShiftRightLogicalAndInsertScalar:
case NI_AdvSimd_ShiftRightLogicalNarrowingLower:
case NI_AdvSimd_ShiftRightLogicalNarrowingSaturateLower:
case NI_AdvSimd_ShiftRightLogicalNarrowingSaturateUpper:
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12 changes: 12 additions & 0 deletions src/coreclr/src/jit/hwintrinsiccodegenarm64.cpp
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Expand Up @@ -333,6 +333,14 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
}
break;

case NI_AdvSimd_ShiftLeftLogicalAndInsertScalar:
ins = INS_sli;
break;

case NI_AdvSimd_ShiftRightLogicalAndInsertScalar:
ins = INS_sri;
break;

case NI_AdvSimd_SubtractWideningLower:
assert(varTypeIsIntegral(intrin.baseType));
if (intrin.op1->TypeGet() == TYP_SIMD8)
Expand Down Expand Up @@ -716,9 +724,11 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
}
break;

case NI_AdvSimd_ShiftLeftLogicalAndInsertScalar:
case NI_AdvSimd_ShiftRightArithmeticAddScalar:
case NI_AdvSimd_ShiftRightArithmeticRoundedAddScalar:
case NI_AdvSimd_ShiftRightLogicalAddScalar:
case NI_AdvSimd_ShiftRightLogicalAndInsertScalar:
case NI_AdvSimd_ShiftRightLogicalRoundedAddScalar:
opt = INS_OPTS_NONE;
emitSize = emitTypeSize(intrin.baseType);
Expand All @@ -736,6 +746,8 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
case NI_AdvSimd_ShiftRightLogicalRoundedAdd:
case NI_AdvSimd_ShiftRightLogicalRoundedNarrowingSaturateUpper:
case NI_AdvSimd_ShiftRightLogicalRoundedNarrowingUpper:
case NI_AdvSimd_ShiftLeftLogicalAndInsert:
case NI_AdvSimd_ShiftRightAndInsert:
{
assert(isRMW);

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4 changes: 4 additions & 0 deletions src/coreclr/src/jit/hwintrinsiclistarm64.h
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Expand Up @@ -179,6 +179,8 @@ HARDWARE_INTRINSIC(AdvSimd, ShiftArithmeticSaturate,
HARDWARE_INTRINSIC(AdvSimd, ShiftArithmeticSaturateScalar, 8, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sqshl, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMDScalar, HW_Flag_NoFlag)
HARDWARE_INTRINSIC(AdvSimd, ShiftArithmeticScalar, 8, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sshl, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMDScalar, HW_Flag_NoFlag)
HARDWARE_INTRINSIC(AdvSimd, ShiftLeftLogical, -1, 2, {INS_shl, INS_shl, INS_shl, INS_shl, INS_shl, INS_shl, INS_shl, INS_shl, INS_invalid, INS_invalid}, HW_Category_IMM, HW_Flag_SupportsContainment|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AdvSimd, ShiftLeftLogicalAndInsert, -1, 3, {INS_sli, INS_sli, INS_sli, INS_sli, INS_sli, INS_sli, INS_sli, INS_sli, INS_sli, INS_sli}, HW_Category_IMM, HW_Flag_SupportsContainment|HW_Flag_SpecialCodeGen|HW_Flag_HasRMWSemantics)
HARDWARE_INTRINSIC(AdvSimd, ShiftLeftLogicalAndInsertScalar, 8, 3, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sli, INS_sli, INS_invalid, INS_invalid}, HW_Category_IMM, HW_Flag_SupportsContainment|HW_Flag_SpecialCodeGen|HW_Flag_HasRMWSemantics)
HARDWARE_INTRINSIC(AdvSimd, ShiftLeftLogicalSaturate, -1, 2, {INS_sqshl, INS_uqshl, INS_sqshl, INS_uqshl, INS_sqshl, INS_uqshl, INS_sqshl, INS_uqshl, INS_invalid, INS_invalid}, HW_Category_IMM, HW_Flag_SupportsContainment|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AdvSimd, ShiftLeftLogicalSaturateScalar, 8, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sqshl, INS_uqshl, INS_invalid, INS_invalid}, HW_Category_IMM, HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AdvSimd, ShiftLeftLogicalSaturateUnsigned, -1, 2, {INS_sqshlu, INS_invalid, INS_sqshlu, INS_invalid, INS_sqshlu, INS_invalid, INS_sqshlu, INS_invalid, INS_invalid, INS_invalid}, HW_Category_IMM, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SupportsContainment|HW_Flag_SpecialCodeGen)
Expand All @@ -194,6 +196,8 @@ HARDWARE_INTRINSIC(AdvSimd, ShiftLogicalRoundedScalar,
HARDWARE_INTRINSIC(AdvSimd, ShiftLogicalSaturate, -1, 2, {INS_uqshl, INS_uqshl, INS_uqshl, INS_uqshl, INS_uqshl, INS_uqshl, INS_uqshl, INS_uqshl, INS_invalid, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_NoFlag)
HARDWARE_INTRINSIC(AdvSimd, ShiftLogicalSaturateScalar, 8, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_uqshl, INS_uqshl, INS_invalid, INS_invalid}, HW_Category_SIMDScalar, HW_Flag_NoFlag)
HARDWARE_INTRINSIC(AdvSimd, ShiftLogicalScalar, 8, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_ushl, INS_ushl, INS_invalid, INS_invalid}, HW_Category_SIMDScalar, HW_Flag_NoFlag)
HARDWARE_INTRINSIC(AdvSimd, ShiftRightAndInsert, -1, 3, {INS_sri, INS_sri, INS_sri, INS_sri, INS_sri, INS_sri, INS_sri, INS_sri, INS_sri, INS_sri}, HW_Category_IMM, HW_Flag_SupportsContainment|HW_Flag_SpecialCodeGen|HW_Flag_HasRMWSemantics)
HARDWARE_INTRINSIC(AdvSimd, ShiftRightLogicalAndInsertScalar, 8, 3, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sri, INS_sri, INS_invalid, INS_invalid}, HW_Category_IMM, HW_Flag_SupportsContainment|HW_Flag_SpecialCodeGen|HW_Flag_HasRMWSemantics)
HARDWARE_INTRINSIC(AdvSimd, ShiftRightArithmetic, -1, 2, {INS_sshr, INS_invalid, INS_sshr, INS_invalid, INS_sshr, INS_invalid, INS_sshr, INS_invalid, INS_invalid, INS_invalid}, HW_Category_IMM, HW_Flag_SupportsContainment|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AdvSimd, ShiftRightArithmeticAdd, -1, 3, {INS_ssra, INS_invalid, INS_ssra, INS_invalid, INS_ssra, INS_invalid, INS_ssra, INS_invalid, INS_invalid, INS_invalid}, HW_Category_IMM, HW_Flag_SupportsContainment|HW_Flag_SpecialCodeGen|HW_Flag_HasRMWSemantics)
HARDWARE_INTRINSIC(AdvSimd, ShiftRightArithmeticAddScalar, 8, 3, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_ssra, INS_invalid, INS_invalid, INS_invalid}, HW_Category_IMM, HW_Flag_SupportsContainment|HW_Flag_SpecialCodeGen|HW_Flag_HasRMWSemantics)
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4 changes: 4 additions & 0 deletions src/coreclr/src/jit/lowerarmarch.cpp
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Expand Up @@ -1426,6 +1426,9 @@ void Lowering::ContainCheckHWIntrinsic(GenTreeHWIntrinsic* node)

case NI_AdvSimd_ExtractVector64:
case NI_AdvSimd_ExtractVector128:
case NI_AdvSimd_ShiftLeftLogicalAndInsert:
case NI_AdvSimd_ShiftLeftLogicalAndInsertScalar:
case NI_AdvSimd_ShiftRightAndInsert:
case NI_AdvSimd_ShiftRightArithmeticAdd:
case NI_AdvSimd_ShiftRightArithmeticAddScalar:
case NI_AdvSimd_ShiftRightArithmeticNarrowingSaturateUnsignedUpper:
Expand All @@ -1436,6 +1439,7 @@ void Lowering::ContainCheckHWIntrinsic(GenTreeHWIntrinsic* node)
case NI_AdvSimd_ShiftRightArithmeticRoundedNarrowingSaturateUpper:
case NI_AdvSimd_ShiftRightLogicalAdd:
case NI_AdvSimd_ShiftRightLogicalAddScalar:
case NI_AdvSimd_ShiftRightLogicalAndInsertScalar:
case NI_AdvSimd_ShiftRightLogicalNarrowingSaturateUpper:
case NI_AdvSimd_ShiftRightLogicalNarrowingUpper:
case NI_AdvSimd_ShiftRightLogicalRoundedAdd:
Expand Down
4 changes: 4 additions & 0 deletions src/coreclr/src/jit/lsraarm64.cpp
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Expand Up @@ -1050,6 +1050,9 @@ int LinearScan::BuildHWIntrinsic(GenTreeHWIntrinsic* intrinsicTree)

case NI_AdvSimd_ExtractVector64:
case NI_AdvSimd_ExtractVector128:
case NI_AdvSimd_ShiftLeftLogicalAndInsert:
case NI_AdvSimd_ShiftLeftLogicalAndInsertScalar:
case NI_AdvSimd_ShiftRightAndInsert:
case NI_AdvSimd_ShiftRightArithmeticAdd:
case NI_AdvSimd_ShiftRightArithmeticAddScalar:
case NI_AdvSimd_ShiftRightArithmeticNarrowingSaturateUnsignedUpper:
Expand All @@ -1060,6 +1063,7 @@ int LinearScan::BuildHWIntrinsic(GenTreeHWIntrinsic* intrinsicTree)
case NI_AdvSimd_ShiftRightArithmeticRoundedNarrowingSaturateUpper:
case NI_AdvSimd_ShiftRightLogicalAdd:
case NI_AdvSimd_ShiftRightLogicalAddScalar:
case NI_AdvSimd_ShiftRightLogicalAndInsertScalar:
case NI_AdvSimd_ShiftRightLogicalNarrowingSaturateUpper:
case NI_AdvSimd_ShiftRightLogicalNarrowingUpper:
case NI_AdvSimd_ShiftRightLogicalRoundedAdd:
Expand Down
32 changes: 32 additions & 0 deletions src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_r.csproj
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Expand Up @@ -752,6 +752,38 @@
<Compile Include="PopCount.Vector128.SByte.cs" />
<Compile Include="ReciprocalEstimate.Vector64.Single.cs" />
<Compile Include="ReciprocalEstimate.Vector64.UInt32.cs" />
<Compile Include="ShiftLeftLogicalAndInsert.Vector64.Byte.cs" />
<Compile Include="ShiftLeftLogicalAndInsert.Vector64.Int16.cs" />
<Compile Include="ShiftLeftLogicalAndInsert.Vector64.Int32.cs" />
<Compile Include="ShiftLeftLogicalAndInsert.Vector64.SByte.cs" />
<Compile Include="ShiftLeftLogicalAndInsert.Vector64.UInt16.cs" />
<Compile Include="ShiftLeftLogicalAndInsert.Vector64.UInt32.cs" />
<Compile Include="ShiftLeftLogicalAndInsert.Vector128.Byte.cs" />
<Compile Include="ShiftLeftLogicalAndInsert.Vector128.Int16.cs" />
<Compile Include="ShiftLeftLogicalAndInsert.Vector128.Int32.cs" />
<Compile Include="ShiftLeftLogicalAndInsert.Vector128.Int64.cs" />
<Compile Include="ShiftLeftLogicalAndInsert.Vector128.SByte.cs" />
<Compile Include="ShiftLeftLogicalAndInsert.Vector128.UInt16.cs" />
<Compile Include="ShiftLeftLogicalAndInsert.Vector128.UInt32.cs" />
<Compile Include="ShiftLeftLogicalAndInsert.Vector128.UInt64.cs" />
<Compile Include="ShiftLeftLogicalAndInsertScalar.Vector64.Int64.cs" />
<Compile Include="ShiftLeftLogicalAndInsertScalar.Vector64.UInt64.cs" />
<Compile Include="ShiftRightAndInsert.Vector64.Byte.cs" />
<Compile Include="ShiftRightAndInsert.Vector64.Int16.cs" />
<Compile Include="ShiftRightAndInsert.Vector64.Int32.cs" />
<Compile Include="ShiftRightAndInsert.Vector64.SByte.cs" />
<Compile Include="ShiftRightAndInsert.Vector64.UInt16.cs" />
<Compile Include="ShiftRightAndInsert.Vector64.UInt32.cs" />
<Compile Include="ShiftRightAndInsert.Vector128.Byte.cs" />
<Compile Include="ShiftRightAndInsert.Vector128.Int16.cs" />
<Compile Include="ShiftRightAndInsert.Vector128.Int32.cs" />
<Compile Include="ShiftRightAndInsert.Vector128.Int64.cs" />
<Compile Include="ShiftRightAndInsert.Vector128.SByte.cs" />
<Compile Include="ShiftRightAndInsert.Vector128.UInt16.cs" />
<Compile Include="ShiftRightAndInsert.Vector128.UInt32.cs" />
<Compile Include="ShiftRightAndInsert.Vector128.UInt64.cs" />
<Compile Include="ShiftRightLogicalAndInsertScalar.Vector64.Int64.cs" />
<Compile Include="ShiftRightLogicalAndInsertScalar.Vector64.UInt64.cs" />
<Compile Include="ReciprocalEstimate.Vector128.Single.cs" />
<Compile Include="ReciprocalEstimate.Vector128.UInt32.cs" />
<Compile Include="ReciprocalSquareRootEstimate.Vector64.Single.cs" />
Expand Down
32 changes: 32 additions & 0 deletions src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_ro.csproj
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Expand Up @@ -752,6 +752,38 @@
<Compile Include="PopCount.Vector128.SByte.cs" />
<Compile Include="ReciprocalEstimate.Vector64.Single.cs" />
<Compile Include="ReciprocalEstimate.Vector64.UInt32.cs" />
<Compile Include="ShiftLeftLogicalAndInsert.Vector64.Byte.cs" />
<Compile Include="ShiftLeftLogicalAndInsert.Vector64.Int16.cs" />
<Compile Include="ShiftLeftLogicalAndInsert.Vector64.Int32.cs" />
<Compile Include="ShiftLeftLogicalAndInsert.Vector64.SByte.cs" />
<Compile Include="ShiftLeftLogicalAndInsert.Vector64.UInt16.cs" />
<Compile Include="ShiftLeftLogicalAndInsert.Vector64.UInt32.cs" />
<Compile Include="ShiftLeftLogicalAndInsert.Vector128.Byte.cs" />
<Compile Include="ShiftLeftLogicalAndInsert.Vector128.Int16.cs" />
<Compile Include="ShiftLeftLogicalAndInsert.Vector128.Int32.cs" />
<Compile Include="ShiftLeftLogicalAndInsert.Vector128.Int64.cs" />
<Compile Include="ShiftLeftLogicalAndInsert.Vector128.SByte.cs" />
<Compile Include="ShiftLeftLogicalAndInsert.Vector128.UInt16.cs" />
<Compile Include="ShiftLeftLogicalAndInsert.Vector128.UInt32.cs" />
<Compile Include="ShiftLeftLogicalAndInsert.Vector128.UInt64.cs" />
<Compile Include="ShiftLeftLogicalAndInsertScalar.Vector64.Int64.cs" />
<Compile Include="ShiftLeftLogicalAndInsertScalar.Vector64.UInt64.cs" />
<Compile Include="ShiftRightAndInsert.Vector64.Byte.cs" />
<Compile Include="ShiftRightAndInsert.Vector64.Int16.cs" />
<Compile Include="ShiftRightAndInsert.Vector64.Int32.cs" />
<Compile Include="ShiftRightAndInsert.Vector64.SByte.cs" />
<Compile Include="ShiftRightAndInsert.Vector64.UInt16.cs" />
<Compile Include="ShiftRightAndInsert.Vector64.UInt32.cs" />
<Compile Include="ShiftRightAndInsert.Vector128.Byte.cs" />
<Compile Include="ShiftRightAndInsert.Vector128.Int16.cs" />
<Compile Include="ShiftRightAndInsert.Vector128.Int32.cs" />
<Compile Include="ShiftRightAndInsert.Vector128.Int64.cs" />
<Compile Include="ShiftRightAndInsert.Vector128.SByte.cs" />
<Compile Include="ShiftRightAndInsert.Vector128.UInt16.cs" />
<Compile Include="ShiftRightAndInsert.Vector128.UInt32.cs" />
<Compile Include="ShiftRightAndInsert.Vector128.UInt64.cs" />
<Compile Include="ShiftRightLogicalAndInsertScalar.Vector64.Int64.cs" />
<Compile Include="ShiftRightLogicalAndInsertScalar.Vector64.UInt64.cs" />
<Compile Include="ReciprocalEstimate.Vector128.Single.cs" />
<Compile Include="ReciprocalEstimate.Vector128.UInt32.cs" />
<Compile Include="ReciprocalSquareRootEstimate.Vector64.Single.cs" />
Expand Down
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