[RISC-V] Port Mono for RISC-V 64 Arch (3/3) IL Lowering & Outputting

src/mono/mono/mini/cpu-riscv64.mdesc

@@ -26,3 +26,156 @@
 #
 #     a    a0
 #     c    all caller-saved registers
+
+nop: len:4
+not_reached: len:0
+not_null: src1:i len:0
+dummy_use: src1:i len:0
+il_seq_point: len:0
+seq_point: len:0
+
+check_this: src1:b len:4
+get_ex_obj: dest:i len:4
+gc_safe_point: src1:i len:12 clob:c
+start_handler: len:8 clob:c
+call_handler: len:4 clob:c
+endfinally: len:32
+localloc: dest:i src1:i len:52
+localloc_imm: dest:i len:28
+generic_class_init: src1:a len:12 clob:c
+
+throw: src1:i len:4
+rethrow: src1:i len:4
+
+br: len:4
+br_reg: src1:i len:4
+jump_table: dest:i len:16
+call: dest:a len:4 clob:c
+call_reg: dest:a src1:i len:4 clob:c
+call_membase: dest:a src1:b len:8 clob:c
+voidcall: len:4 clob:c
+voidcall_reg: src1:i len:4 clob:c
+voidcall_membase: src1:b len:8 clob:c
+vcall2: len:16 clob:c
+vcall2_membase: src1:b len:20 clob:c
+fcall: dest:f len:8 clob:c
+
+# Note: in RV32, it shoule be 
+# lcall: dest:l ...
+lcall: dest:a len:16 clob:c
+lcall_membase: dest:a src1:b len:8 clob:c
+
+store_membase_reg: dest:b src1:i len:4
+storei1_membase_reg: dest:b src1:i len:4
+storei2_membase_reg: dest:b src1:i len:4
+storei4_membase_reg: dest:b src1:i len:4
+storei8_membase_reg: dest:b src1:i len:4
+storer4_membase_reg: dest:b src1:f len:4
+storer8_membase_reg: dest:b src1:f len:4
+
+load_membase: dest:i src1:b len:24
+loadu1_membase: dest:i src1:b len:16
+loadi1_membase: dest:i src1:b len:16
+loadu2_membase: dest:i src1:b len:16
+loadi2_membase: dest:i src1:b len:16
+loadu4_membase: dest:i src1:b len:16
+loadi4_membase: dest:i src1:b len:16
+loadi8_membase: dest:i src1:b len:16
+loadr4_membase: dest:f src1:b len:16
+loadr8_membase: dest:f src1:b len:16
+
+memory_barrier: len:4
+atomic_add_i4: dest:i src1:i src2:i len:4
+atomic_store_u1: dest:b src1:i len:8
+atomic_store_i4: dest:b src1:i len:8
+atomic_store_u8: dest:b src1:i len:8
+atomic_load_i4: dest:b src1:i len:12
+atomic_load_i8: dest:b src1:i len:12
+atomic_load_u8: dest:b src1:i len:12
+atomic_cas_i4: dest:i src1:i src2:i src3:i len:24
+atomic_cas_i8: dest:i src1:i src2:i src3:i len:24
+atomic_exchange_i4: dest:i src1:i src2:i len:4
+atomic_exchange_i8: dest:i src1:i src2:i len:4
+
+move: dest:i src1:i len:4
+lmove: dest:i src1:i len:4
+fmove: dest:f src1:f len:4
+rmove: dest:f src1:f len:4
+
+iconst: dest:i len:16
+i8const: dest:i len:16
+int_add: dest:i src1:i src2:i len:4
+long_add: dest:i src1:i src2:i len:4
+int_sub: dest:i src1:i src2:i len:4
+long_sub: dest:i src1:i src2:i len:4
+int_mul: dest:i src1:i src2:i len:4
+float_mul: dest:f src1:f src2:f len:4
+long_div: dest:i src1:i src2:i len:32
+long_div_un: dest:i src1:i src2:i len:32
+int_rem: dest:i src1:i src2:i len:32
+long_rem: dest:i src1:i src2:i len:32
+int_rem_un: dest:i src1:i src2:i len:32
+long_rem_un: dest:i src1:i src2:i len:32
+
+r4const: dest:f len:16
+r8const: dest:f len:16
+int_conv_to_r4: dest:f src1:i len:4
+int_conv_to_r8: dest:f src1:i len:4
+r4_conv_to_r8: dest:f src1:f len:4
+float_conv_to_i4: dest:i src1:f len:4
+float_conv_to_r4: dest:f src1:f len:4
+float_ceq: dest:i src1:f src2:f len:4
+float_clt: dest:i src1:f src2:f len:4
+float_clt_un: dest:i src1:f src2:f len:4
+
+add_imm: dest:i src1:i len:4
+int_add_imm: dest:i src1:i len:4
+long_add_imm: dest:i src1:i len:4
+
+and_imm: dest:i src1:i len:4
+xor_imm: dest:i src1:i len:4
+shl_imm: dest:i src1:i len:4
+shr_imm: dest:i src1:i len:4
+shr_un_imm: dest:i src1:i len:4
+
+int_and: dest:i src1:i src2:i len:4
+int_and_imm: dest:i src1:i len:4
+int_or: dest:i src1:i src2:i len:4
+int_or_imm: dest:i src1:i len:4
+int_xor: dest:i src1:i src2:i len:4
+int_xor_imm: dest:i src1:i len:4
+int_shl: dest:i src1:i src2:i len:4
+int_shl_imm: dest:i src1:i len:4
+int_shr_un: dest:i src1:i src2:i len:4
+int_shr_imm: dest:i src1:i len:4
+int_shr_un_imm: dest:i src1:i len:4
+
+long_and: dest:i src1:i src2:i len:4
+long_and_imm: dest:i src1:i len:4
+long_or: dest:i src1:i src2:i len:4
+long_xor: dest:i src1:i src2:i len:4
+long_or_imm: dest:i src1:i len:4
+long_shl_imm: dest:i src1:i len:4
+long_shr_un: dest:i src1:i src2:i len:4
+long_shr_imm: dest:i src1:i len:4
+long_shr_un_imm: dest:i src1:i len:4
+
+
+riscv_setfreg_r4: dest:f src1:f len:4
+
+riscv_beq: src1:i src2:i len:8
+riscv_bne: src1:i src2:i len:8
+riscv_bge: src1:i src2:i len:8
+riscv_bgeu: src1:i src2:i len:8
+riscv_blt: src1:i src2:i len:8
+riscv_bltu: src1:i src2:i len:8
+riscv_exc_beq: src1:i src2:i len:32
+riscv_exc_bne: src1:i src2:i len:32
+riscv_exc_bgeu: src1:i src2:i len:32
+riscv_exc_blt: src1:i src2:i len:32
+riscv_exc_bltu: src1:i src2:i len:32
+riscv_slt: dest:i src1:i src2:i len:4
+riscv_sltu: dest:i src1:i src2:i len:4
+riscv_slti: dest:i src1:i len:4
+riscv_sltiu: dest:i src1:i len:4
+riscv_addiw: dest:i src1:i len:4

src/mono/mono/mini/mini-codegen.c

@@ -479,7 +479,8 @@ mono_print_ins_index_strbuf (int i, MonoInst *ins)
 			if (!ins->inst_false_bb)
 				g_string_append_printf (sbuf, " [B%d]", ins->inst_true_bb->block_num);
 			else
-				g_string_append_printf (sbuf, " [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
+				g_string_append_printf (sbuf, " [T:B%d F:B%d]", ins->inst_true_bb->block_num,
+				                        ins->inst_false_bb->block_num);
 			break;
 		case OP_PHI:
 		case OP_VPHI:
@@ -683,10 +684,16 @@ mono_print_ins_index_strbuf (int i, MonoInst *ins)
 	case OP_LBGE_UN:
 	case OP_LBLE:
 	case OP_LBLE_UN:
+#if defined(TARGET_RISCV64) || defined(TARGET_RISCV32)
+	case OP_RISCV_BNE:
+	case OP_RISCV_BEQ:
+	case OP_RISCV_BGE:
+#endif
 		if (!ins->inst_false_bb)
 			g_string_append_printf (sbuf, " [B%d]", ins->inst_true_bb->block_num);
 		else
-			g_string_append_printf (sbuf, " [B%dB%d]", ins->inst_true_bb->block_num, ins->inst_false_bb->block_num);
+			g_string_append_printf (sbuf, " [T:B%d F:B%d]", ins->inst_true_bb->block_num,
+			                        ins->inst_false_bb->block_num);
 		break;
 	case OP_LIVERANGE_START:
 	case OP_LIVERANGE_END:
@@ -1827,7 +1834,7 @@ mono_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
 
 					sreg_masks [0] &= ~(regmask (hreg));
 
-					DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_arch_regname (hreg), reg));
+					DEBUG (printf ("\tassigned arg ireg %s to R%d\n", mono_arch_regname (hreg), reg));
 
 					list = g_slist_next (list);
 				}
@@ -1845,7 +1852,7 @@ mono_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
 
 					assign_reg (cfg, rs, reg, hreg, 1);
 
-					DEBUG (printf ("\tassigned arg reg %s to R%d\n", mono_regname_full (hreg, 1), reg));
+					DEBUG (printf ("\tassigned arg freg %s to R%d\n", mono_regname_full (hreg, 1), reg));
 
 					list = g_slist_next (list);
 				}

src/mono/mono/mini/mini-ops.h

@@ -1793,3 +1793,32 @@ MINI_OP(OP_CVT_SI_FP_SCALAR, "convert_si_to_fp_scalar", XREG, XREG, NONE)
 #if defined(TARGET_ARM64) || defined(TARGET_AMD64) || defined(TARGET_WASM)
 MINI_OP3(OP_BSL,            "bitwise_select", XREG, XREG, XREG, XREG)
 #endif // TARGET_ARM64 || TARGET_AMD64 || TARGET_WASM
+
+#if defined(TARGET_RISCV64) || defined(TARGET_RISCV32)
+MINI_OP(OP_RISCV_EXC_BEQ, "riscv_exc_beq", NONE, IREG, IREG)
+MINI_OP(OP_RISCV_EXC_BNE, "riscv_exc_bne", NONE, IREG, IREG)
+MINI_OP(OP_RISCV_EXC_BGEU, "riscv_exc_bgeu", NONE, IREG, IREG)
+MINI_OP(OP_RISCV_EXC_BLT, "riscv_exc_blt", NONE, IREG, IREG)
+MINI_OP(OP_RISCV_EXC_BLTU, "riscv_exc_bltu", NONE, IREG, IREG)
+
+MINI_OP(OP_RISCV_BEQ, "riscv_beq", NONE, IREG, IREG)
+MINI_OP(OP_RISCV_BNE, "riscv_bne", NONE, IREG, IREG)
+MINI_OP(OP_RISCV_BGE, "riscv_bge", NONE, IREG, IREG)
+MINI_OP(OP_RISCV_BGEU, "riscv_bgeu", NONE, IREG, IREG)
+MINI_OP(OP_RISCV_BLT, "riscv_blt", NONE, IREG, IREG)
+MINI_OP(OP_RISCV_BLTU, "riscv_bltu", NONE, IREG, IREG)
+
+MINI_OP(OP_RISCV_ADDIW, "riscv_addiw", IREG, IREG, NONE)
+
+MINI_OP(OP_RISCV_SLT, "riscv_slt", IREG, IREG, IREG)
+MINI_OP(OP_RISCV_SLTU, "riscv_sltu", IREG, IREG, IREG)
+MINI_OP(OP_RISCV_SLTI, "riscv_slti", IREG, IREG, NONE)
+MINI_OP(OP_RISCV_SLTIU, "riscv_sltiu", IREG, IREG, NONE)
+
+// used for cfg->r4fp == FALSE
+MINI_OP(OP_RISCV_SETFREG_R4,"riscv_setfreg_r4", FREG, FREG, NONE)
+#endif
+
+#if defined(TARGET_RISCV64)
+MINI_OP(OP_RISCV_ADDUW, "riscv_adduw", IREG, IREG, IREG)
+#endif