Anything I can do to help to get ddr3 working on tang primer 20k? #1649
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Hi @bentwire, thanks for the help. @trabucayre has been working on this and created a simulation environment for it. He provided me a patch that already improve things (without fully fixing the issue): litedram_gowin.patch.txt I've not been able to test yet, but you can provide feedback without and with this patch applied if you want, it should reduce number of reported errors. The next steps are probably to continue doing test with the hardware and with the simulation environment. |
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@enjoy-digital I should be able to test this weekend. I will let you know! Thanks! |
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Wow its much better! Build your hardware, easily! (c) Copyright 2012-2023 Enjoy-Digital BIOS built on Mar 17 2023 23:06:13 LiteX git sha1: 6ee39b4 --=============== SoC ==================-- --========== Initialization ============-- --============= Console ================-- litex> litex> sdram_test litex> I will try at 48MHz clock (I've been using 50MHz) and see if its any dufferent. |
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It seems a little less stable at 48MHz maybe? 2-3 runs probably aren't really enough to tell... Build your hardware, easily! (c) Copyright 2012-2023 Enjoy-Digital BIOS built on Mar 17 2023 23:12:20 LiteX git sha1: 6ee39b4 --=============== SoC ==================-- --========== Initialization ============-- --============= Console ================-- litex> sdram_test litex> sdram_test litex> sdram_test litex> It does not work at all at 60MHz. (100% bus errors) |
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Another update... What core I use seems to matter. It works better with the Vex than the pico RV: --=============== SoC ==================-- --========== Initialization ============-- --============= Console ================-- litex> litex> sdram_test |
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Sorry to have missed this issue and thanks! The results difference between picoRV and Vex is maybe related to the placement for some ressources. With simulation (took a really long time due to One thing where I'm not clear is about |
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I have also do:
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@trabucayre Thank you for the response! I did notice that in the examples from gowin they want to use the 1:4 clock ratio and the MEM_{I,O}SER8 primitives. I wonder if the DDR stuff does not work right at 1:2 for these particular RAM chips (The micron and others)? Just a guess, not sure why they chose that ratio. Again thanks for all the hard work. This is an awesome project! |
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Moving (or trying) to an 1:4 ratio is an idea I have. |
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Ok cool. Let me know if there are any patches you want me to test. I've been reading the gowin IO docs but they aren't very detailed... They kind of explain how to connect the DQS block to the SERDES but don't fully explain all the settings... |
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I like a lot the "they aren't very detailed" ;-) It's an understatement I have started to add 1:4 but all timings have to be check before having something usable/publishable. My idea is to adapt code according to |
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Yeah, pretty big understatement! Thanks for the updates! Can't wait to test your changes! |
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@trabucayre Have anything for me to test yet? Just checking in to see how things are going. :) |
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Currently nothing stable to be tested.
read: TBD |
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Hi, @trabucayre May be it will give an idea. |
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check your DDR3 part nums, surprise! |
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Interesting @e-yes, do you have more info? |
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It isn't the part on the schematic... Its an SK Hynix chip, H5TQ1G63EFR, and I don't think the timings are exactly the same as the Micron part. |
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@e-yes: Was it what you wanted to say? Or have you been able to get it working with a specific part number (if so, can you share it). The initial prototype from Sipeed and the production version are not using the same DDR chip, so current part number use in LiteX-Board is probably the one from the prototype (or with similar geometry/timings). |
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@enjoy-digital absolutely. Hynix is at my side. |
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@e-yes What timings have you tried so far? I may join you :) |
I can confirm this is the part on my production board that I just got off of AliExpress as well. I took a look at the geometry, and it first glance I think it was fine. Also AFAIK the timings are running it at 800MHz with very conervative timings. Maybe it just needs to be refreshed more often at those timings? Would be great to get this running. I think price/performance wise this is hands-down the best FPGA board on the market at the moment. |
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@trabucayre I just tried your 4phases branch and also rebasing your commit onto I think there's a chance the other Hynix H5XXX part + your patch may work and wanted to try them together. |
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Thanks to point this issue. I have updated my branch/fork with a fix I have simply forget to push. |
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I'm still getting the exact same issue with your litedram branch. It's not building: |
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I tried a bunch of permuations to no avail. AFIAIK the memory is 1Gb and not 4Gb. So the Geometry will need adapting for sure. Also I'm not sure why the assertion happens. I commented it out for now. |
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It's weird: I have retried my branch and I have no more this issue. |
It compiles for me. Timing is still off somehow but I got it to compile. Need to check the docs for the actual chip on the board to get the timings. |
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The real chip is H5TQ1G63EFR, and the BIOS output SDRAM size should not be 256.0MiB, but 128.0MiB. |
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@verilogzhou did changing the size fix it for you? |
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Received my board as well, same issue. With 1/4th it is bus errors: 192/256, addr erros: 0/8192, data errors: 393216/524288. |
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What I have tried so far: class H5TQ1G63EFR(DDR3Module):
# geometry
nbanks = 8
nrows = 8192
ncols = 1024
# timings
technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(4, 7.5), tCCD=(4, None), tRRD=(4, 6), tZQCS=(64, 80))
speedgrade_timings = {
"1600": _SpeedgradeTimings(tRP=13.75, tRCD=13.75, tWR=15, tRFC=(160, None), tFAW=(None, 40), tRAS=35),
}
speedgrade_timings["default"] = speedgrade_timings["1600"]Don't pay too much attention to timings, this is the intermediate version from backup. I've tried 800 timings as well, but no luck:/ Along with @trabucayre changes. |
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Here is the schematic. Maybe the pinout is incorrect? Update: Why are the adress lines A14 and A15 disconnected? |
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I went through the pinout. It looks correct. Did anyone try the sipeed examples just to make sure it actually works in the gowin toolchain? |
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I have tried the DDR3 tests against the Gowin toolchain within the Sipeed example repo, and I can confirm it does work. |
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I'll maybe have time to try this out this weekend. But this pure gowin example exists: LicheeTang20K_DDR_Test. At the very least we can cross check the resulting constraint file against that and check if it's insantiating the macro correctly. |
Ah perfect. Good to know. |
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I tried @trabucayre's |
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I think someone mentioned constraints. I was checking it out today, here's the resulting code versus the sipeed example: Litex: Sipeed/Gowin Toolchian: I'd see if the drive strength in particular makes a difference. I may have sometime to try again this weekend. |
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Hi, Thanks for the tests @nedos. Just for info, we've planned to work together on this in end August/early September with @trabucayre if this is not solved before. |
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As mentionned previously: |
Those appear to refer to the balls T7 and M7 which are no connect according to the 96 ball diagram in the H5TQ1G63EFR datasheet. So I guess that is ok as well. I am also looking forward to seeing the DDR3 work, although I am probably of no help at this point, but I did not find an answer to @DatanoiseTV 's question in the comments, so I decided to state it here. EDIT: Also, note that the schematic connects the A13 (DDR3 ball T3, C8 on FPGA), which is not used for the H5TQ1G63EFR which is 64M x 16, so I think that is a possible error in the configuration. I have no idea if that would case stuff to behave as it does though. |
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We have pushed a fix to compensate extra cycle introduced by gowin primitives. Now memtest pass successfully. |
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This seems to be working great! Thanks for all the hard work! |
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i'm so confused that the same issue occurred in tang_mega_138k , Is it only the ddr of Gowin that has this problem? |
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Can you tell me how to solve it? Because I am currently starting the new board 138k of Gowin and have also encountered a problem with mem initialization failure |
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We can probaby close this issue now that it's implemented. It still seems there are some variations between boards but we can discuss this in #1848. For the Tang Mega 138K, the development/support is still not finished and things can be discussed in litex-hub/litex-boards#549. Any help/support for this work is welcome. |
I'm interested in getting litex to work fully with the tang primer 20k, so I can try some riscv rust programming on it. Without the dram things are kinda limited (the dram is way overkill, but I want to put a framebuffer in there as well...) so I would like to get that working first...
I'm really new to migen and all this, and FPGAs in general, but I would really like to help, even if its just testing various configurations.
Litex is pretty amazing!
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