Sipeed Tang Mega 138k : SDRAM test failed.

[agv100]

Hello,
I'm trying to build litex bytestream with DDR3 support.
Previously, on-board DDR3 wa checked with GAO/simple example in sipeed github examples, so, should be operational.

But, when I load litex bitstream, build with --with-ddr3 support, I see, initially ddr3 could be seen:

      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2023 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Nov 21 2023 15:36:50
 BIOS CRC passed (dabbc66a)

 LiteX git sha1: 02277680

--=============== SoC ==================--
CPU:            VexRiscv @ 50MHz
BUS:            WISHBONE 32-bit @ 4GiB
CSR:            32-bit data
ROM:            128.0KiB
SRAM:           8.0KiB
SDRAM:          1.0GiB 32-bit @ 200MT/s (CL-6 CWL-5)
MAIN-RAM:       1.0GiB

--========== Initialization ============--

But it's tests are failed:

litex> sdram_init
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Read leveling:
  m0, b00: |00000000| delays: -
  m0, b01: |00000000| delays: -
  m0, b02: |00000000| delays: -
  m0, b03: |00000000| delays: -
  best: m0, b00 delays: -
  m1, b00: |00000000| delays: -
  m1, b01: |00000000| delays: -
  m1, b02: |00000000| delays: -
  m1, b03: |00000000| delays: -
  best: m1, b00 delays: -
  m2, b00: |00000000| delays: -
  m2, b01: |00000000| delays: -
  m2, b02: |00000000| delays: -
  m2, b03: |00000000| delays: -
  best: m2, b00 delays: -
  m3, b00: |00000000| delays: -
  m3, b01: |00000000| delays: -
  m3, b02: |00000000| delays: -
  m3, b03: |00000000| delays: -
  best: m3, b00 delays: -
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
  Write: 0x40000000-0x40200000 2.0MiB
   Read: 0x40000000-0x40200000 2.0MiB
  bus errors:  256/256
  addr errors: 0/8192
  data errors: 524288/524288
Memtest KO

And, when I try to access memory manually, it looks not working:

litex> mem_write 0x40000010 0xff 1

litex> mem_read 0x40000010 1
Memory dump:
0x40000010  00   

What could be a problem?

[trabucayre]

Hello,
Yes DDR3 is not working and is a WIP.
Sipeed example uses Gowin's DDR3 encrypted IP. But since Gowin doesn't provides real documentation about primitives required to add this support it's more difficult/long to have a working support.
If you need SDRAM it's possible to plug a Mister SDRAM extension into SDRAM dock's connector.

[enjoy-digital]

@agv100: We've planned some to work on this in the following weeks/months. This will probably happen soon but we are working on others features in priority on other features for now.

[enjoy-digital]

While continuing this work, it could be worth checking if a specific LOC constraint is required to get the DDR3 working, as it is for the AE350 SOC:

[briansune]

@enjoy-digital
@trabucayre

I would like to give it a try on the modified board.
The background is because before 19.9 is released the DDR3 IP cannot run AE350 with non-Micron DDR.
You can read more on here about what we had done:
https://github.com/briansune/Tang-Mega-138K-AE350-Demo

If such design is based on the default official board hardware then my current hardware is 100% aligned.

Meanwhile from the generated verilog file.
I can see the DDR clock is using a 1:2 rather than 1:4?
GW5AST do not support 1:2 physical timing it will fail surely.

[agv100]

Hello,
Just found new commit, adding both sipeed and mister SDRAMs.
So, if I build (without today commit on litedram/litedram/frontend/wishbone.py as it fails on assertion assert wishbone.addressing == "byte" ), with options:

I still can see sdram init failed, but, when I manually read-write upto 4-byte words, it works well:

Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
  Write: 0x40000000-0x40200000 2.0MiB
   Read: 0x40000000-0x40200000 2.0MiB
  bus errors:  128/256
  addr errors: 0/8192
  data errors: 524288/524288
Memtest KO

litex> mem_write 0x40100000 0xabcd

litex> mem_read 0x40100000
Memory dump:
0x40100000  cd ab 00 00                                      ....

litex>

Anything I have to do to get it fully working?

[briansune]

@agv100

I think you had an misunderstand on what the last commission.

Read and think is what you need. The commit is for external SDRAM PMOD.
Not the default DDR3 memory.

End of story.

Bests,
Brian