IDF master

tools/sdk/esp32/include/app_update/include/esp_ota_ops.h

@@ -14,6 +14,7 @@
 #include "esp_partition.h"
 #include "esp_image_format.h"
 #include "esp_flash_partitions.h"
+#include "soc/soc_caps.h"
 
 #ifdef __cplusplus
 extern "C"

tools/sdk/esp32/include/bootloader_support/include/bootloader_common.h

@@ -8,7 +8,8 @@
 #include "esp_flash_partitions.h"
 #include "esp_image_format.h"
 #include "esp_app_format.h"
-// RESET_REASON is declared in rom/rtc.h
+// [refactor-todo]: we shouldn't expose ROM header files in a public API header, remove them in v5.0
+// Tracked in IDF-1968
 #if CONFIG_IDF_TARGET_ESP32
 #include "esp32/rom/rtc.h"
 #elif CONFIG_IDF_TARGET_ESP32S2
@@ -62,18 +63,37 @@ bool bootloader_common_ota_select_valid(const esp_ota_select_entry_t *s);
 bool bootloader_common_ota_select_invalid(const esp_ota_select_entry_t *s);
 
 /**
- * @brief Check if the GPIO input is a long hold or a short hold.
+ * @brief Check if a GPIO input is held low for a long period, short period, or not
+ * at all.
+ *
+ * This function will configure the specified GPIO as an input with internal pull-up enabled.
  *
- * Number of the GPIO input will be configured as an input with internal pull-up enabled.
  * If the GPIO input is held low continuously for delay_sec period then it is a long hold.
  * If the GPIO input is held low for less period then it is a short hold.
  *
  * @param[in] num_pin Number of the GPIO input.
  * @param[in] delay_sec Input must be driven low for at least this long, continuously.
- * @return esp_comm_gpio_hold_t Defines type of hold a GPIO in low state.
+ * @return esp_comm_gpio_hold_t Type of low level hold detected, if any.
  */
 esp_comm_gpio_hold_t bootloader_common_check_long_hold_gpio(uint32_t num_pin, uint32_t delay_sec);
 
+/**
+ * @brief Check if a GPIO input is held low or high for a long period, short period, or not
+ * at all.
+ *
+ * This function will configure the specified GPIO as an input with internal pull-up enabled.
+ *
+ * If the GPIO input is held at 'level' continuously for delay_sec period then it is a long hold.
+ * If the GPIO input is held at 'level' for less period then it is a short hold.
+ *
+ * @param[in] num_pin Number of the GPIO input.
+ * @param[in] delay_sec Input must be driven to 'level' for at least this long, continuously.
+ * @param[in] level Input pin level to trigger on hold
+ * @return esp_comm_gpio_hold_t Type of hold detected, if any.
+ */
+esp_comm_gpio_hold_t bootloader_common_check_long_hold_gpio_level(uint32_t num_pin, uint32_t delay_sec, bool level);
+
+
 /**
  * @brief Erase the partition data that is specified in the transferred list.
  *

tools/sdk/esp32/include/bt/include/esp32/include/esp_bt.h

@@ -25,6 +25,38 @@
 extern "C" {
 #endif
 
+#ifdef CONFIG_BT_ENABLED
+
+#define SOC_MEM_BT_DATA_START               0x3ffae6e0
+#define SOC_MEM_BT_DATA_END                 0x3ffaff10
+#define SOC_MEM_BT_EM_START                 0x3ffb0000
+#define SOC_MEM_BT_EM_END                   0x3ffb7cd8
+#define SOC_MEM_BT_EM_BTDM0_START           0x3ffb0000
+#define SOC_MEM_BT_EM_BTDM0_END             0x3ffb09a8
+#define SOC_MEM_BT_EM_BLE_START             0x3ffb09a8
+#define SOC_MEM_BT_EM_BLE_END               0x3ffb1ddc
+#define SOC_MEM_BT_EM_BTDM1_START           0x3ffb1ddc
+#define SOC_MEM_BT_EM_BTDM1_END             0x3ffb2730
+#define SOC_MEM_BT_EM_BREDR_START           0x3ffb2730
+#define SOC_MEM_BT_EM_BREDR_NO_SYNC_END     0x3ffb6388  //Not calculate with synchronize connection support
+#define SOC_MEM_BT_EM_BREDR_END             0x3ffb7cd8  //Calculate with synchronize connection support
+#define SOC_MEM_BT_EM_SYNC0_START           0x3ffb6388
+#define SOC_MEM_BT_EM_SYNC0_END             0x3ffb6bf8
+#define SOC_MEM_BT_EM_SYNC1_START           0x3ffb6bf8
+#define SOC_MEM_BT_EM_SYNC1_END             0x3ffb7468
+#define SOC_MEM_BT_EM_SYNC2_START           0x3ffb7468
+#define SOC_MEM_BT_EM_SYNC2_END             0x3ffb7cd8
+#define SOC_MEM_BT_BSS_START                0x3ffb8000
+#define SOC_MEM_BT_BSS_END                  0x3ffb9a20
+#define SOC_MEM_BT_MISC_START               0x3ffbdb28
+#define SOC_MEM_BT_MISC_END                 0x3ffbdb5c
+
+#define SOC_MEM_BT_EM_PER_SYNC_SIZE         0x870
+
+#define SOC_MEM_BT_EM_BREDR_REAL_END        (SOC_MEM_BT_EM_BREDR_NO_SYNC_END + CONFIG_BTDM_CTRL_BR_EDR_MAX_SYNC_CONN_EFF * SOC_MEM_BT_EM_PER_SYNC_SIZE)
+
+#endif //CONFIG_BT_ENABLED
+
 #define ESP_BT_CONTROLLER_CONFIG_MAGIC_VAL  0x20200622
 
 /**

tools/sdk/esp32/include/config/sdkconfig.h

@@ -327,6 +327,8 @@
 #define CONFIG_FMB_SERIAL_ASCII_BITS_PER_SYMB 8
 #define CONFIG_FMB_SERIAL_ASCII_TIMEOUT_RESPOND_MS 1000
 #define CONFIG_FMB_PORT_TASK_PRIO 10
+#define CONFIG_FMB_PORT_TASK_AFFINITY_CPU0 1
+#define CONFIG_FMB_PORT_TASK_AFFINITY 0x0
 #define CONFIG_FMB_CONTROLLER_NOTIFY_TIMEOUT 20
 #define CONFIG_FMB_CONTROLLER_NOTIFY_QUEUE_SIZE 20
 #define CONFIG_FMB_CONTROLLER_STACK_SIZE 4096
@@ -454,6 +456,8 @@
 #define CONFIG_MBEDTLS_SSL_PROTO_DTLS 1
 #define CONFIG_MBEDTLS_SSL_ALPN 1
 #define CONFIG_MBEDTLS_CLIENT_SSL_SESSION_TICKETS 1
+#define CONFIG_MBEDTLS_X509_CHECK_KEY_USAGE 1
+#define CONFIG_MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE 1
 #define CONFIG_MBEDTLS_SERVER_SSL_SESSION_TICKETS 1
 #define CONFIG_MBEDTLS_AES_C 1
 #define CONFIG_MBEDTLS_RC4_DISABLED 1
@@ -686,5 +690,5 @@
 #define CONFIG_ULP_COPROC_ENABLED CONFIG_ESP32_ULP_COPROC_ENABLED
 #define CONFIG_ULP_COPROC_RESERVE_MEM CONFIG_ESP32_ULP_COPROC_RESERVE_MEM
 #define CONFIG_WARN_WRITE_STRINGS CONFIG_COMPILER_WARN_WRITE_STRINGS
-#define CONFIG_ARDUINO_IDF_COMMIT "d93887f9f"
+#define CONFIG_ARDUINO_IDF_COMMIT "c69f0ec32"
 #define CONFIG_ARDUINO_IDF_BRANCH "master"

tools/sdk/esp32/include/console/esp_console.h

@@ -48,6 +48,7 @@ typedef struct {
     uint32_t task_stack_size;      //!< repl task stack size
     uint32_t task_priority;        //!< repl task priority
     const char *prompt;            //!< prompt (NULL represents default: "esp> ")
+    size_t max_cmdline_length;     //!< maximum length of a command line. If 0, default value will be used
 } esp_console_repl_config_t;
 
 /**
@@ -61,6 +62,7 @@ typedef struct {
         .task_stack_size = 4096,          \
         .task_priority = 2,               \
         .prompt = NULL,                   \
+        .max_cmdline_length = 0,          \
 }
 
 /**

tools/sdk/esp32/include/console/linenoise/linenoise.h

@@ -72,6 +72,7 @@ void linenoiseSetDumbMode(int set);
 bool linenoiseIsDumbMode(void);
 void linenoisePrintKeyCodes(void);
 void linenoiseAllowEmpty(bool);
+int linenoiseSetMaxLineLen(size_t len);
 
 #ifdef __cplusplus
 }

tools/sdk/esp32/include/driver/include/driver/i2c.h

@@ -74,14 +74,15 @@ typedef struct{
 
     union {
         struct {
-            uint32_t clk_speed;     /*!< I2C clock frequency for master mode, (no higher than 1MHz for now) */
-        } master;                   /*!< I2C master config */
+            uint32_t clk_speed;      /*!< I2C clock frequency for master mode, (no higher than 1MHz for now) */
+        } master;                    /*!< I2C master config */
         struct {
-            uint8_t addr_10bit_en;  /*!< I2C 10bit address mode enable for slave mode */
-            uint16_t slave_addr;    /*!< I2C address for slave mode */
-        } slave;                    /*!< I2C slave config */
+            uint8_t addr_10bit_en;   /*!< I2C 10bit address mode enable for slave mode */
+            uint16_t slave_addr;     /*!< I2C address for slave mode */
+            uint32_t maximum_speed;  /*!< I2C expected clock speed from SCL. */
+        } slave;                     /*!< I2C slave config */
     };
-    uint32_t clk_flags;             /*!< Bitwise of ``I2C_SCLK_SRC_FLAG_**FOR_DFS**`` for clk source choice*/
+    uint32_t clk_flags;              /*!< Bitwise of ``I2C_SCLK_SRC_FLAG_**FOR_DFS**`` for clk source choice*/
 } i2c_config_t;
 
 

tools/sdk/esp32/include/driver/include/driver/spi_master.h

@@ -105,7 +105,7 @@ typedef struct {
 #define SPI_TRANS_VARIABLE_ADDR       (1<<6)  ///< Use the ``address_bits`` in ``spi_transaction_ext_t`` rather than default value in ``spi_device_interface_config_t``.
 #define SPI_TRANS_VARIABLE_DUMMY      (1<<7)  ///< Use the ``dummy_bits`` in ``spi_transaction_ext_t`` rather than default value in ``spi_device_interface_config_t``.
 #define SPI_TRANS_SET_CD              (1<<7)  ///< Set the CD pin
-
+#define SPI_TRANS_CS_KEEP_ACTIVE      (1<<8)  ///< Keep CS active after data transfer
 /**
  * This structure describes one SPI transaction. The descriptor should not be modified until the transaction finishes.
  */
@@ -194,7 +194,8 @@ esp_err_t spi_bus_remove_device(spi_device_handle_t handle);
  * @param ticks_to_wait Ticks to wait until there's room in the queue; use portMAX_DELAY to
  *                      never time out.
  * @return
- *         - ESP_ERR_INVALID_ARG   if parameter is invalid
+ *         - ESP_ERR_INVALID_ARG   if parameter is invalid. This can happen if SPI_DEVICE_CS_KEEP_LOW flag is specified while
+ *                                 the bus was not acquired (`spi_device_acquire_bus()` should be called first)
  *         - ESP_ERR_TIMEOUT       if there was no room in the queue before ticks_to_wait expired
  *         - ESP_ERR_NO_MEM        if allocating DMA-capable temporary buffer failed
  *         - ESP_ERR_INVALID_STATE if previous transactions are not finished
@@ -257,7 +258,8 @@ esp_err_t spi_device_transmit(spi_device_handle_t handle, spi_transaction_t *tra
  *              currently only portMAX_DELAY is supported.
  *
  * @return
- *         - ESP_ERR_INVALID_ARG   if parameter is invalid
+ *         - ESP_ERR_INVALID_ARG   if parameter is invalid. This can happen if SPI_DEVICE_CS_KEEP_LOW flag is specified while
+ *                                 the bus was not acquired (`spi_device_acquire_bus()` should be called first)
  *         - ESP_ERR_TIMEOUT       if the device cannot get control of the bus before ``ticks_to_wait`` expired
  *         - ESP_ERR_NO_MEM        if allocating DMA-capable temporary buffer failed
  *         - ESP_ERR_INVALID_STATE if previous transactions are not finished

tools/sdk/esp32/include/driver/include/esp_private/gdma.h

@@ -38,7 +38,8 @@ typedef enum {
     GDMA_TRIG_PERIPH_ADC,  /*!< GDMA trigger peripheral: ADC */
     GDMA_TRIG_PERIPH_DAC,  /*!< GDMA trigger peripheral: DAC */
     GDMA_TRIG_PERIPH_LCD,  /*!< GDMA trigger peripheral: LCD */
-    GDMA_TRIG_PERIPH_CAM   /*!< GDMA trigger peripheral: CAM */
+    GDMA_TRIG_PERIPH_CAM,  /*!< GDMA trigger peripheral: CAM */
+    GDMA_TRIG_PERIPH_RMT,  /*!< GDMA trigger peripheral: RMT */
 } gdma_trigger_peripheral_t;
 
 /**
@@ -58,10 +59,23 @@ typedef struct {
     gdma_channel_handle_t sibling_chan; /*!< DMA sibling channel handle (NULL means having sibling is not necessary) */
     gdma_channel_direction_t direction; /*!< DMA channel direction */
     struct {
-        int reserve_sibling: 1;   /*!< If set, DMA channel allocator would prefer to allocate new channel in a new pair, and reserve sibling channel for future use */
+        int reserve_sibling: 1; /*!< If set, DMA channel allocator would prefer to allocate new channel in a new pair, and reserve sibling channel for future use */
     } flags;
 } gdma_channel_alloc_config_t;
 
+/**
+ * @brief GDMA transfer ability
+ *
+ * @note The alignment set in this structure is **not** a guarantee that gdma driver will take care of the nonalignment cases.
+ *       Actually the GDMA driver has no knowledge about the DMA buffer (address and size) used by upper layer.
+ *       So it's the responsibility of the **upper layer** to take care of the buffer address and size.
+ *
+ */
+typedef struct {
+    size_t sram_trans_align;  /*!< DMA transfer alignment for memory in SRAM, in bytes. The driver enables/disables burst mode based on this value. 0 means no alignment is required */
+    size_t psram_trans_align; /*!< DMA transfer alignment for memory in PSRAM, in bytes. The driver sets proper burst block size based on the alignment value. 0 means no alignment is required */
+} gdma_transfer_ability_t;
+
 /**
  * @brief Type of GDMA event data
  *
@@ -79,6 +93,9 @@ typedef struct {
  * @param event_data GDMA event data
  * @param user_data User registered data from `gdma_register_tx_event_callbacks` or `gdma_register_rx_event_callbacks`
  *
+ * @return Whether a task switch is needed after the callback function returns,
+ *         this is usually due to the callback wakes up some high priority task.
+ *
  */
 typedef bool (*gdma_event_callback_t)(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data);
 
@@ -171,6 +188,18 @@ esp_err_t gdma_connect(gdma_channel_handle_t dma_chan, gdma_trigger_t trig_perip
  */
 esp_err_t gdma_disconnect(gdma_channel_handle_t dma_chan);
 
+/**
+ * @brief Set DMA channel transfer ability
+ *
+ * @param[in] dma_chan GDMA channel handle, allocated by `gdma_new_channel`
+ * @param[in] ability Transfer ability, e.g. alignment
+ * @return
+ *      - ESP_OK: Set DMA channel transfer ability successfully
+ *      - ESP_ERR_INVALID_ARG: Set DMA channel transfer ability failed because of invalid argument
+ *      - ESP_FAIL: Set DMA channel transfer ability failed because of other error
+ */
+esp_err_t gdma_set_transfer_ability(gdma_channel_handle_t dma_chan, const gdma_transfer_ability_t *ability);
+
 /**
  * @brief Apply channel strategy for GDMA channel
  *