WIP: Clock Connection and Fabric key Generation

.gitignore

@@ -134,4 +134,5 @@ examples/**/_*
 FM_WORK*
 *.lck
 runOpenFPGA
-docs/source/_SDN_DOC_SOURCE
+docs/source/_SDN_DOC_SOURCE
+*.pickle

docs/Makefile

@@ -11,7 +11,7 @@ SOURCEDIR         = source
 BUILDDIR          = build
 AUTO_BUILD_DIR    = "auto_.*\/.*"
 PYTHON_EXEC       ?= "python3.8"
-RUN_EXAMPLE_WC    ?= 
+RUN_EXAMPLE_WC    ?= OpenFPGA_*
 
 .SILENT:
 .ONESHELL:
@@ -25,7 +25,7 @@ install:
 
 reload:
 	@$(SPHINXRELOAD) "$(SOURCEDIR)" "${BUILDDIR}" \
-	--watch "../examples/**" \
+	--watch "../examples/**/*.py" \
 	--watch "../spydrnet_physical/support_files/**" \
 	--re-ignore ${AUTO_BUILD_DIR} $(SPHINXRELOADOPTS) $(SPHINXOPTS) $(O)
 
@@ -54,6 +54,13 @@ run_examples: generate_schematics
 	echo "ERROR" {}; fi;'
 	if [[ -f $${log_dir}/failed.log ]]; then return 1; fi
 
+design_examples:
+# Write a script to run a  design example before documentation
+# mainly every design project will consist of a shell script to execute code
+# design_examples execution is different from run_examples execution because the 
+# each script is not independent, and it needs to executed sequentially 
+	echo "Not implemented yet"
+
 # run_examples:
 # 	find ../examples -type f -name "*.py" \
 # 	-exec echo "Running : " "$$? {} " \; \

docs/source/fpga44/index.rst

@@ -27,7 +27,6 @@ The following figure illustrates the structure of an FPGA tile.
    :align: center
    :width: 80%
 
-
 Generating Netlist from OpenFPGA
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 

docs/source/index.rst

@@ -54,6 +54,12 @@ Table of Contents
    fpga44/index
    example
 
+.. toctree::
+   :maxdepth: 2
+   :caption: Design examples
+
+   ./auto_design_examples/*/index.rst
+
 .. toctree::
    :maxdepth: 1
    :caption: Developeres Content

examples/OpenFPGA_tiling/12_Hetero_Tile01.py

@@ -22,32 +22,31 @@
 from itertools import chain
 
 import spydrnet as sdn
-from spydrnet_physical.util import (FloorPlanViz, FPGAGridGen, Tile02,
-                                    GridFloorplanGen, OpenFPGA)
+from spydrnet_physical.util import (FPGAGridGen, Tile02, OpenFPGA)
 
-logger = logging.getLogger('spydrnet_logs')
-sdn.enable_file_logging(LOG_LEVEL='INFO')
+logger = logging.getLogger("spydrnet_logs")
+sdn.enable_file_logging(LOG_LEVEL="INFO")
 
 PROP = "VERILOG.InlineConstraints"
 
 
-CBX_COLOR = '#d9d9f3'
-CBY_COLOR = '#a8d0db'
-SB_COLOR = '#ceefe4'
-GRID_COLOR = '#ddd0b1'
+CBX_COLOR = "#d9d9f3"
+CBY_COLOR = "#a8d0db"
+SB_COLOR = "#ceefe4"
+GRID_COLOR = "#ddd0b1"
 
 
 def main():
     proj = "../hetrogeneous_fabric"
-    source_files = glob.glob(f'{proj}/*_Verilog/lb/*.v')
-    source_files += glob.glob(f'{proj}/*_Verilog/routing/*.v')
-    source_files += glob.glob(f'{proj}/*_Verilog/sub_module/*.v')
-    source_files += glob.glob(f'{proj}/*_Verilog/fpga_top.v')
+    source_files = glob.glob(f"{proj}/*_Verilog/lb/*.v")
+    source_files += glob.glob(f"{proj}/*_Verilog/routing/*.v")
+    source_files += glob.glob(f"{proj}/*_Verilog/sub_module/*.v")
+    source_files += glob.glob(f"{proj}/*_Verilog/fpga_top.v")
 
     # Temporary fix to read multiple verilog files
     with tempfile.NamedTemporaryFile(suffix=".v") as fp:
         for eachV in source_files:
-            with open(eachV, "r") as fpv:
+            with open(eachV, "r", encoding="UTF-8") as fpv:
                 fp.write(str.encode(" ".join(fpv.readlines())))
         fp.seek(0)
         netlist = sdn.parse(fp.name)
@@ -62,9 +61,11 @@ def main():
     fpga.merge_all_grid_ios()
 
     # Convert top level independent nets to bus
-    for i in chain(fpga.top_module.get_instances("grid_clb*"),
-                   fpga.top_module.get_instances("grid_io*"),
-                   fpga.top_module.get_instances("sb_*")):
+    for i in chain(
+        fpga.top_module.get_instances("grid_clb*"),
+        fpga.top_module.get_instances("grid_io*"),
+        fpga.top_module.get_instances("sb_*"),
+    ):
         for p in filter(lambda x: True, i.reference.ports):
             if p.size > 1 and (i.check_all_scalar_connections(p)):
                 cable_list = []

examples/OpenFPGA_tiling/13_Hetero_Tile01_render.py

@@ -9,57 +9,58 @@
 
 This script can be used for shaping and placement of the modules before place and route.
 
-.. image:: ../../../examples/OpenFPGA_tiling/_classic_tile_hetero_floorplan.svg
+.. image:: ../../../examples/OpenFPGA_tiling/_fpga_auto_initial_heterogeneous_placement.svg
    :width: 70%
    :align: center
 
 """
-#sphinx_gallery_thumbnail_path = '../../examples/OpenFPGA_tiling/_classic_tile_hetero_floorplan.svg'
+# sphinx_gallery_thumbnail_path = '../../examples/OpenFPGA_tiling/_fpga_auto_initial_heterogeneous_placement.svg'
 import glob
 import logging
-import os
 import tempfile
+from copy import deepcopy
 from itertools import chain
-import seaborn as sns
 
+import seaborn as sns
 import spydrnet as sdn
-from copy import deepcopy
-from spydrnet_physical.util import (FloorPlanViz, FPGAGridGen, Tile02,
-                                    GridFloorplanGen, OpenFPGA,
-                                    initial_hetero_placement)
+from spydrnet_physical.util import (FloorPlanViz, FPGAGridGen, OpenFPGA,
+                                    Tile02, initial_hetero_placement)
 
-logger = logging.getLogger('spydrnet_logs')
-sdn.enable_file_logging(LOG_LEVEL='INFO')
+logger = logging.getLogger("spydrnet_logs")
+sdn.enable_file_logging(LOG_LEVEL="INFO")
 
 PROP = "VERILOG.InlineConstraints"
 
 
-CBX_COLOR = '#d9d9f3'
-CBY_COLOR = '#a8d0db'
-SB_COLOR = '#ceefe4'
-GRID_COLOR = '#ddd0b1'
+CBX_COLOR = "#d9d9f3"
+CBY_COLOR = "#a8d0db"
+SB_COLOR = "#ceefe4"
+GRID_COLOR = "#ddd0b1"
 
 
-STYLE_SHEET = '''
+STYLE_SHEET = """
     .over_util {fill:#b22222 !important}
     text{font-family: Lato; font-size: 8px}
-'''
+"""
 
 CPP = 2
 SC_HEIGHT = 10
 
 
 def main():
+    """
+    Main routine
+    """
     proj = "../hetrogeneous_fabric"
-    source_files = glob.glob(f'{proj}/*_Verilog/lb/*.v')
-    source_files += glob.glob(f'{proj}/*_Verilog/routing/*.v')
-    source_files += glob.glob(f'{proj}/*_Verilog/sub_module/*.v')
-    source_files += glob.glob(f'{proj}/*_Verilog/fpga_top.v')
+    source_files = glob.glob(f"{proj}/*_Verilog/lb/*.v")
+    source_files += glob.glob(f"{proj}/*_Verilog/routing/*.v")
+    source_files += glob.glob(f"{proj}/*_Verilog/sub_module/*.v")
+    source_files += glob.glob(f"{proj}/*_Verilog/fpga_top.v")
 
     # Temporary fix to read multiple verilog files
     with tempfile.NamedTemporaryFile(suffix=".v") as fp:
-        for eachV in source_files:
-            with open(eachV, "r") as fpv:
+        for each_file in source_files:
+            with open(each_file, "r", encoding="UTF-8") as fpv:
                 fp.write(str.encode(" ".join(fpv.readlines())))
         fp.seek(0)
         netlist = sdn.parse(fp.name)
@@ -74,9 +75,11 @@ def main():
     fpga.merge_all_grid_ios()
 
     # Convert top level independent nets to bus
-    for i in chain(fpga.top_module.get_instances("grid_clb*"),
-                   fpga.top_module.get_instances("grid_io*"),
-                   fpga.top_module.get_instances("sb_*")):
+    for i in chain(
+        fpga.top_module.get_instances("grid_clb*"),
+        fpga.top_module.get_instances("grid_io*"),
+        fpga.top_module.get_instances("sb_*"),
+    ):
         for p in filter(lambda x: True, i.reference.ports):
             if p.size > 1 and (i.check_all_scalar_connections(p)):
                 cable_list = []
@@ -91,48 +94,52 @@ def main():
     # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
     #           Floorplan visualization
     # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
-    fpga_grid = FPGAGridGen(design_name='FPGA8x8', layout="8x8",
-                            arch_file=f"{proj}/FPGA88_hetero_Task/arch/k6_N10_tileable.xml",
-                            release_root=None)
+    fpga_grid = FPGAGridGen(
+        design_name="FPGA8x8",
+        layout="8x8",
+        arch_file=f"{proj}/FPGA88_hetero_Task/arch/k6_N10_tileable.xml",
+        release_root=None,
+    )
     fpga_grid.enumerate_grid()
     fpga.load_grid(fpga_grid)
-    fpga.register_placement_creator(initial_hetero_placement,
-                                    areaFile={
-                                        "grid_clb": [2500, 24*8, 24],
-                                        "cbx_1__1_": [2500*0.6, 0, 0]})
+    fpga.register_placement_creator(
+        initial_hetero_placement,
+        areaFile={"grid_clb": [2500, 24 * 8, 24],
+                  "cbx_1__1_": [2500 * 0.6, 0, 0]},
+    )
     # print(set(inst.keys()))
     # print(set(fpga.placement_creator.module_shapes.keys()))
     shapes = fpga.placement_creator.module_shapes
     s_param = fpga.placement_creator.s_param
-    print(set(inst.keys())-set(shapes.keys()))
+    print(set(inst.keys()) - set(shapes.keys()))
 
-    shapes['cbx_2__0_'] = shapes['cbx_1__0_']
-    shapes['cbx_2__2_'] = shapes['cbx_1__1_']
-    shapes['cbx_2__8_'] = shapes['cbx_1__8_']
+    shapes["cbx_2__0_"] = shapes["cbx_1__0_"]
+    shapes["cbx_2__2_"] = shapes["cbx_1__1_"]
+    shapes["cbx_2__8_"] = shapes["cbx_1__8_"]
 
-    shapes['cby_2__1_'] = shapes['cby_3__1_'] = deepcopy(shapes['cby_1__1_'])
+    shapes["cby_2__1_"] = shapes["cby_3__1_"] = deepcopy(shapes["cby_1__1_"])
 
-    shapes['sb_2__0_'] = shapes['sb_3__0_'] = deepcopy(shapes['sb_1__0_'])
-    shapes['sb_2__8_'] = shapes['sb_3__8_'] = deepcopy(shapes['sb_1__8_'])
-    shapes['sb_2__2_'] = deepcopy(shapes['sb_1__1_'])
-    shapes['sb_3__1_'] = deepcopy(shapes['sb_1__1_'])
-    shapes['sb_2__1_'] = deepcopy(shapes['sb_1__1_'])
-    shapes['sb_1__2_'] = deepcopy(shapes['sb_1__1_'])
+    shapes["sb_2__0_"] = shapes["sb_3__0_"] = deepcopy(shapes["sb_1__0_"])
+    shapes["sb_2__8_"] = shapes["sb_3__8_"] = deepcopy(shapes["sb_1__8_"])
+    shapes["sb_2__2_"] = deepcopy(shapes["sb_1__1_"])
+    shapes["sb_3__1_"] = deepcopy(shapes["sb_1__1_"])
+    shapes["sb_2__1_"] = deepcopy(shapes["sb_1__1_"])
+    shapes["sb_1__2_"] = deepcopy(shapes["sb_1__1_"])
 
-    shapes['sb_8__2_'] = deepcopy(shapes['sb_8__1_'])
-    shapes['grid_mult_8'] = deepcopy(shapes['grid_clb'])
+    shapes["sb_8__2_"] = deepcopy(shapes["sb_8__1_"])
+    shapes["grid_mult_8"] = deepcopy(shapes["grid_clb"])
 
-    shapes['grid_mult_8']["POINTS"][1] += s_param["clb_h"] + s_param["cbx11_h"]
-    shapes['sb_1__1_']["POINTS"][4] = 0
-    p = shapes['sb_2__1_']["PLACEMENT"]
-    shapes['sb_2__1_']["PLACEMENT"] = (p[0] + shapes['sb_2__1_']["POINTS"][1],
-                                       p[1])
-    shapes['sb_2__1_']["POINTS"][1] = 0
+    shapes["grid_mult_8"]["POINTS"][1] += s_param["clb_h"] + s_param["cbx11_h"]
+    shapes["sb_1__1_"]["POINTS"][4] = 0
+    p = shapes["sb_2__1_"]["PLACEMENT"]
+    shapes["sb_2__1_"]["PLACEMENT"] = (
+        p[0] + shapes["sb_2__1_"]["POINTS"][1], p[1])
+    shapes["sb_2__1_"]["POINTS"][1] = 0
 
-    p = shapes['sb_8__1_']["PLACEMENT"]
-    shapes['sb_8__1_']["PLACEMENT"] = (p[0] + shapes['sb_8__1_']["POINTS"][1],
-                                       p[1])
-    shapes['sb_8__1_']["POINTS"][1] = 0
+    p = shapes["sb_8__1_"]["PLACEMENT"]
+    shapes["sb_8__1_"]["PLACEMENT"] = (
+        p[0] + shapes["sb_8__1_"]["POINTS"][1], p[1])
+    shapes["sb_8__1_"]["POINTS"][1] = 0
 
     fpga.create_placement()
     fpga.show_placement_data("*_0__*")
@@ -142,7 +149,7 @@ def main():
     fpga.register_tile_generator(Tile02)
     fpga.create_tiles()
 
-    palette = sns.color_palette('pastel', 15).as_hex()
+    palette = sns.color_palette("pastel", 15).as_hex()
     for indx, tile in enumerate(fpga.top_module.get_definitions("*tile*")):
         tile.data[PROP]["COLOR"] = palette[indx]
 
@@ -159,10 +166,10 @@ def main():
     dwg = fp.get_svg()
     dwg.add(fpga.placement_creator.design_grid.render_grid(return_group=True))
 
-    pattern = dwg.pattern(size=(4*CPP, 2*SC_HEIGHT),
+    pattern = dwg.pattern(size=(4 * CPP, 2 * SC_HEIGHT),
                           patternUnits="userSpaceOnUse")
     pattern.add(dwg.circle(center=(2, 2), r=1, fill="black"))
-    pattern.add(dwg.circle(center=(2, SC_HEIGHT+2), r=1, fill="red"))
+    pattern.add(dwg.circle(center=(2, SC_HEIGHT + 2), r=1, fill="red"))
     dwg.defs.add(pattern)
     dwg.defs.elements[0].elements[0].attribs["fill"] = pattern.get_funciri()
 

examples/basic/merge_multiple_instances.py

@@ -11,5 +11,17 @@
 import spydrnet as sdn
 import spydrnet_physical as sdnphy
 
-# TODO
-print("NotImplemented")
+netlist = sdnphy.load_netlist_by_name('basic_hierarchy')
+
+top = netlist.top_instance.reference
+inst1 = next(top.get_instances('inst_1_0'))
+inst2 = next(top.get_instances('inst_2_0'))
+inst3= next(top.get_instances('inst_1_1'))
+inst4 = next(top.get_instances('inst_2_1'))
+
+inst_tup_list = ([inst1, inst2], "merged_inst1"), ([inst3, inst4], "merged_inst2")
+
+top.merge_multiple_instance(inst_tup_list, new_definition_name = "merged_insts")
+
+sdn.compose(netlist, '_merged_mul_inst_design.v', skip_constraints=True)
+