gateware.interface.psram: add HyperRAM implementation using ECP5 DQS …

…logic
greatscottgadgets · Apr 22, 2024 · 340a99c · 340a99c
1 parent 2935c7d
commit 340a99c
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Showing 2 changed files with 512 additions and 10 deletions.
diff --git a/applets/hyperram_diagnostic.py b/applets/hyperram_diagnostic.py
@@ -18,14 +18,15 @@
 from luna                             import top_level_cli
 from apollo_fpga                      import ApolloDebugger
 from luna.gateware.interface.jtag     import JTAGRegisterInterface
-from luna.gateware.interface.psram    import HyperRAMPHY, HyperRAMInterface
+from luna.gateware.interface.psram    import HyperRAMGenericPHY, HyperRAMGenericInterface, HyperRAMDQSInterface, HyperRAMDQSPHY
 
 REGISTER_RAM_REGISTER_SPACE = 1
 REGISTER_RAM_ADDR           = 2
 REGISTER_RAM_READ_LENGTH    = 3
 REGISTER_RAM_FIFO           = 4
 REGISTER_RAM_START          = 5
 
+DQS = True
 
 class HyperRAMDiagnostic(Elaboratable):
     """
@@ -52,9 +53,14 @@ def elaborate(self, platform):
         #
         # HyperRAM test connections.
         #
-        ram_bus = platform.request('ram', dir={'cs': '-'})
-        psram_phy = HyperRAMPHY(bus=ram_bus)
-        psram = HyperRAMInterface(phy=psram_phy.phy)
+        if DQS:
+            ram_bus = platform.request('ram', dir={'rwds':'-', 'dq':'-', 'cs':'-'})
+            psram_phy = HyperRAMDQSPHY(bus=ram_bus)
+            psram = HyperRAMDQSInterface(phy=psram_phy.phy)
+        else:
+            ram_bus = platform.request('ram', dir={'cs': '-'})
+            psram_phy = HyperRAMGenericPHY(bus=ram_bus)
+            psram = HyperRAMGenericInterface(phy=psram_phy.phy)
         m.submodules += [psram_phy, psram]