gateware.interface.psram: add HyperRAM implementation using ECP5 DQS …

…logic
greatscottgadgets · Apr 22, 2024 · e1e1a2c · e1e1a2c
1 parent 2935c7d
commit e1e1a2c
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Showing 3 changed files with 518 additions and 16 deletions.
diff --git a/applets/hyperram_diagnostic.py b/applets/hyperram_diagnostic.py
@@ -18,14 +18,15 @@
 from luna                             import top_level_cli
 from apollo_fpga                      import ApolloDebugger
 from luna.gateware.interface.jtag     import JTAGRegisterInterface
-from luna.gateware.interface.psram    import HyperRAMPHY, HyperRAMInterface
+from luna.gateware.interface.psram    import HyperRAMGenericPHY, HyperRAMGenericInterface, HyperRAMDQSInterface, HyperRAMDQSPHY
 
 REGISTER_RAM_REGISTER_SPACE = 1
 REGISTER_RAM_ADDR           = 2
 REGISTER_RAM_READ_LENGTH    = 3
 REGISTER_RAM_FIFO           = 4
 REGISTER_RAM_START          = 5
 
+DQS = True
 
 class HyperRAMDiagnostic(Elaboratable):
     """
@@ -52,9 +53,14 @@ def elaborate(self, platform):
         #
         # HyperRAM test connections.
         #
-        ram_bus = platform.request('ram', dir={'cs': '-'})
-        psram_phy = HyperRAMPHY(bus=ram_bus)
-        psram = HyperRAMInterface(phy=psram_phy.phy)
+        if DQS:
+            ram_bus = platform.request('ram', dir={'rwds':'-', 'dq':'-', 'cs':'-'})
+            psram_phy = HyperRAMDQSPHY(bus=ram_bus)
+            psram = HyperRAMDQSInterface(phy=psram_phy.phy)
+        else:
+            ram_bus = platform.request('ram', dir={'cs': '-'})
+            psram_phy = HyperRAMGenericPHY(bus=ram_bus)
+            psram = HyperRAMGenericInterface(phy=psram_phy.phy)
         m.submodules += [psram_phy, psram]
 
 

diff --git a/applets/interactive-test.py b/applets/interactive-test.py
@@ -16,13 +16,13 @@
 from luna.gateware.architecture.car   import LunaECP5DomainGenerator
 from luna.gateware.interface.jtag     import JTAGRegisterInterface
 from luna.gateware.interface.ulpi     import ULPIRegisterWindow
-from luna.gateware.interface.psram    import HyperRAMPHY, HyperRAMInterface
+from luna.gateware.interface.psram    import HyperRAMGenericPHY, HyperRAMGenericInterface
 
 from apollo_fpga.support.selftest          import ApolloSelfTestCase, named_test
 
 
 CLOCK_FREQUENCIES = {
-    "fast": 60,
+    "fast": 120,
     "sync": 60,
     "usb":  60
 }
@@ -114,9 +114,9 @@ def elaborate(self, platform):
         #
         # HyperRAM test connections.
         #
-        ram_bus = platform.request('ram')
-        psram_phy = HyperRAMPHY(bus=ram_bus)
-        psram = HyperRAMInterface(phy=psram_phy.phy)
+        ram_bus = platform.request('ram', dir={'cs': '-'})
+        psram_phy = HyperRAMGenericPHY(bus=ram_bus)
+        psram = HyperRAMGenericInterface(phy=psram_phy.phy)
         m.submodules += [psram_phy, psram]
 
         psram_address_changed = Signal()
@@ -259,7 +259,7 @@ def assertHyperRAMRegister(self, address: int, expected_values: int):
         """ Assertion that fails iff a RAM register doesn't hold the expected value. """
 
         self.dut.registers.register_write(REGISTER_RAM_REG_ADDR, address)
-        actual_value =  self.dut.registers.register_read(REGISTER_RAM_VALUE)
+        actual_value =  self.dut.registers.register_read(REGISTER_RAM_VALUE) >> 16
 
         if actual_value not in expected_values:
             raise AssertionError(f"RAM register {address} was {actual_value}, not one of expected {expected_values}")