use from_{ref,mut} to get pointers from references

Using these functions makes the intent clearer and increases readability

src/arch/aarch64/kernel/mod.rs

@@ -13,8 +13,8 @@ pub mod switch;
 pub mod systemtime;
 
 use core::arch::global_asm;
-use core::str;
 use core::sync::atomic::{AtomicU32, AtomicU64, Ordering};
+use core::{ptr, str};
 
 use hermit_entry::boot_info::{BootInfo, RawBootInfo};
 
@@ -52,7 +52,7 @@ pub fn raw_boot_info() -> &'static RawBootInfo {
 }
 
 pub fn get_boot_info_address() -> VirtAddr {
-	VirtAddr(raw_boot_info() as *const _ as u64)
+	VirtAddr(ptr::from_ref(raw_boot_info()).addr() as u64)
 }
 
 pub fn is_uhyve_with_pci() -> bool {

src/arch/aarch64/kernel/switch.rs

@@ -15,7 +15,7 @@ macro_rules! kernel_function_impl {
 						let mut reg = 0_usize;
 						// SAFETY: $A is smaller than usize and directly fits in a register
 						// Since f takes $A as argument via C calling convention, any opper bytes do not matter.
-						ptr::write(&mut reg as *mut _ as _, $arg);
+						ptr::write(ptr::from_mut(&mut reg) as _, $arg);
 						reg
 					};
 				)*

src/arch/aarch64/mm/paging.rs

@@ -517,7 +517,7 @@ where
 
 		// Calculate the address of the subtable.
 		let index = page.table_index::<L>();
-		let table_address = self as *const PageTable<L> as usize;
+		let table_address = core::ptr::from_ref(self).addr();
 		let subtable_address =
 			(table_address << PAGE_MAP_BITS) & !(usize::MAX << 48) | (index << PAGE_BITS);
 		unsafe { &mut *(subtable_address as *mut PageTable<L::SubtableLevel>) }

src/arch/x86_64/kernel/acpi.rs

@@ -140,7 +140,7 @@ impl<'a> AcpiTable<'a> {
 	}
 
 	pub fn header_start_address(&self) -> usize {
-		self.header as *const _ as usize
+		ptr::from_ref(self.header).addr()
 	}
 
 	pub fn table_start_address(&self) -> usize {
@@ -395,7 +395,7 @@ fn parse_fadt(fadt: AcpiTable<'_>) {
 	// In that case, it shall be preferred over the I/O port specified in pm1a_cnt_blk.
 	// As all PM1 control registers are supposed to be in I/O space, we can simply check the address_space field
 	// of x_pm1a_cnt_blk to determine the validity of x_pm1a_cnt_blk.
-	let x_pm1a_cnt_blk_field_address = &fadt_table.x_pm1a_cnt_blk as *const _ as usize;
+	let x_pm1a_cnt_blk_field_address = ptr::from_ref(&fadt_table.x_pm1a_cnt_blk).addr();
 	let pm1a_cnt_blk = if x_pm1a_cnt_blk_field_address < fadt.table_end_address()
 		&& fadt_table.x_pm1a_cnt_blk.address_space == GENERIC_ADDRESS_IO_SPACE
 	{

src/arch/x86_64/kernel/apic.rs

@@ -729,7 +729,7 @@ pub fn boot_application_processors() {
 		);
 		ptr::write_unaligned(
 			(SMP_BOOT_CODE_ADDRESS + SMP_BOOT_CODE_OFFSET_BOOTINFO).as_mut_ptr(),
-			raw_boot_info() as *const _ as u64,
+			ptr::from_ref(raw_boot_info()).addr() as u64,
 		);
 	}
 

src/arch/x86_64/kernel/processor.rs

@@ -8,7 +8,7 @@ use core::convert::Infallible;
 use core::hint::spin_loop;
 use core::num::NonZeroU32;
 use core::sync::atomic::{AtomicU64, Ordering};
-use core::{fmt, u32};
+use core::{fmt, ptr, u32};
 
 use hermit_entry::boot_info::PlatformInfo;
 use hermit_sync::Lazy;
@@ -221,7 +221,7 @@ impl FPUState {
 	pub fn restore(&self) {
 		if supports_xsave() {
 			unsafe {
-				_xrstor(self as *const _ as _, u64::MAX);
+				_xrstor(ptr::from_ref(self) as _, u64::MAX);
 			}
 		} else {
 			self.restore_common();
@@ -231,7 +231,7 @@ impl FPUState {
 	pub fn save(&mut self) {
 		if supports_xsave() {
 			unsafe {
-				_xsave(self as *mut _ as _, u64::MAX);
+				_xsave(ptr::from_mut(self) as _, u64::MAX);
 			}
 		} else {
 			self.save_common();
@@ -240,13 +240,13 @@ impl FPUState {
 
 	pub fn restore_common(&self) {
 		unsafe {
-			_fxrstor(self as *const _ as _);
+			_fxrstor(ptr::from_ref(self) as _);
 		}
 	}
 
 	pub fn save_common(&mut self) {
 		unsafe {
-			_fxsave(self as *mut _ as _);
+			_fxsave(ptr::from_mut(self) as _);
 			asm!("fnclex", options(nomem, nostack));
 		}
 	}

src/arch/x86_64/kernel/scheduler.rs

@@ -342,7 +342,7 @@ impl TaskFrame for Task {
 			ptr::write_bytes(stack.as_mut_ptr::<u8>(), 0, mem::size_of::<State>());
 
 			if let Some(tls) = &self.tls {
-				(*state).fs = tls.thread_ptr() as *const _ as u64;
+				(*state).fs = ptr::from_ref(tls.thread_ptr()).addr() as u64;
 			}
 			(*state).rip = task_start as usize as u64;
 			(*state).rdi = func as usize as u64;

src/arch/x86_64/kernel/switch.rs

@@ -166,7 +166,7 @@ macro_rules! kernel_function_impl {
 						let mut reg = 0_usize;
 						// SAFETY: $A is smaller than usize and directly fits in a register
 						// Since f takes $A as argument via C calling convention, any opper bytes do not matter.
-						ptr::write(&mut reg as *mut _ as _, $arg);
+						ptr::write(ptr::from_mut(&mut reg) as _, $arg);
 						reg
 					};
 				)*

src/drivers/virtio/transport/mmio.rs

@@ -8,7 +8,7 @@ use core::intrinsics::unaligned_volatile_store;
 use core::ptr::{read_volatile, write_volatile};
 use core::result::Result;
 use core::sync::atomic::{fence, Ordering};
-use core::u8;
+use core::{ptr, u8};
 
 #[cfg(any(feature = "tcp", feature = "udp"))]
 use crate::arch::kernel::interrupts::*;
@@ -251,7 +251,7 @@ pub struct NotifCfg {
 
 impl NotifCfg {
 	pub fn new(registers: &mut MmioRegisterLayout) -> Self {
-		let raw = &mut registers.queue_notify as *mut u32;
+		let raw = ptr::from_mut(&mut registers.queue_notify);
 
 		NotifCfg { queue_notify: raw }
 	}
@@ -332,7 +332,7 @@ pub struct IsrStatus {
 
 impl IsrStatus {
 	pub fn new(registers: &mut MmioRegisterLayout) -> Self {
-		let ptr = &mut registers.interrupt_status as *mut _;
+		let ptr = ptr::from_mut(&mut registers.interrupt_status);
 		let raw: &'static mut IsrStatusRaw = unsafe { &mut *(ptr as *mut IsrStatusRaw) };
 
 		IsrStatus { raw }

src/drivers/virtio/virtqueue/mod.rs

@@ -19,6 +19,7 @@ use alloc::rc::Rc;
 use alloc::vec::Vec;
 use core::cell::RefCell;
 use core::ops::{BitAnd, Deref, DerefMut};
+use core::ptr;
 
 use align_address::Align;
 use zerocopy::AsBytes;
@@ -145,8 +146,8 @@ impl Virtq {
 	pub fn check_bounds<T: AsSliceU8>(data: &T) -> bool {
 		let slice = data.as_slice_u8();
 
-		let start_virt = (&slice[0] as *const u8) as usize;
-		let end_virt = (&slice[slice.len() - 1] as *const u8) as usize;
+		let start_virt = ptr::from_ref(slice.first().unwrap()).addr();
+		let end_virt = ptr::from_ref(slice.last().unwrap()).addr();
 		let end_phy_calc = paging::virt_to_phys(VirtAddr::from(start_virt)) + (slice.len() - 1);
 		let end_phy = paging::virt_to_phys(VirtAddr::from(end_virt));
 
@@ -165,8 +166,8 @@ impl Virtq {
 	/// Slices provided to the Queue must pass this test, otherwise the queue
 	/// currently panics.
 	pub fn check_bounds_slice(slice: &[u8]) -> bool {
-		let start_virt = (&slice[0] as *const u8) as usize;
-		let end_virt = (&slice[slice.len() - 1] as *const u8) as usize;
+		let start_virt = ptr::from_ref(slice.first().unwrap()).addr();
+		let end_virt = ptr::from_ref(slice.last().unwrap()).addr();
 		let end_phy_calc = paging::virt_to_phys(VirtAddr::from(start_virt)) + (slice.len() - 1);
 		let end_phy = paging::virt_to_phys(VirtAddr::from(end_virt));
 
@@ -547,7 +548,7 @@ pub trait AsSliceU8 {
 	/// * The slice must serialize the actual structure the device expects, as the queue will use
 	/// the addresses of the slice in order to refer to the structure.
 	fn as_slice_u8(&self) -> &[u8] {
-		unsafe { core::slice::from_raw_parts((self as *const _) as *const u8, self.len()) }
+		unsafe { core::slice::from_raw_parts(ptr::from_ref(self) as *const u8, self.len()) }
 	}
 
 	/// Returns a mutable slice of the given structure.
@@ -557,7 +558,7 @@ pub trait AsSliceU8 {
 	/// * The slice must serialize the actual structure the device expects, as the queue will use
 	/// the addresses of the slice in order to refer to the structure.
 	fn as_slice_u8_mut(&mut self) -> &mut [u8] {
-		unsafe { core::slice::from_raw_parts_mut((self as *const _) as *mut u8, self.len()) }
+		unsafe { core::slice::from_raw_parts_mut(ptr::from_mut(self) as *mut u8, self.len()) }
 	}
 }
 
@@ -2189,8 +2190,8 @@ impl MemPool {
 		assert!(!slice.is_empty());
 
 		// Assert descriptor does not cross a page barrier
-		let start_virt = (&slice[0] as *const u8) as usize;
-		let end_virt = (&slice[slice.len() - 1] as *const u8) as usize;
+		let start_virt = ptr::from_ref(slice.first().unwrap()).addr();
+		let end_virt = ptr::from_ref(slice.last().unwrap()).addr();
 		let end_phy_calc = paging::virt_to_phys(VirtAddr::from(start_virt)) + (slice.len() - 1);
 		let end_phy = paging::virt_to_phys(VirtAddr::from(end_virt));
 
@@ -2231,8 +2232,8 @@ impl MemPool {
 		assert!(!slice.is_empty());
 
 		// Assert descriptor does not cross a page barrier
-		let start_virt = (&slice[0] as *const u8) as usize;
-		let end_virt = (&slice[slice.len() - 1] as *const u8) as usize;
+		let start_virt = ptr::from_ref(slice.first().unwrap()).addr();
+		let end_virt = ptr::from_ref(slice.last().unwrap()).addr();
 		let end_phy_calc = paging::virt_to_phys(VirtAddr::from(start_virt)) + (slice.len() - 1);
 		let end_phy = paging::virt_to_phys(VirtAddr::from(end_virt));
 

src/drivers/virtio/virtqueue/packed.rs

@@ -150,7 +150,7 @@ impl DescriptorRing {
 
 					// Turn the raw pointer into a Pinned again, which will hold ownership of the Token
 					queue.borrow_mut().push_back(Transfer {
-						transfer_tkn: Some(Pinned::from_raw(tkn as *mut TransferToken)),
+						transfer_tkn: Some(Pinned::from_raw(ptr::from_mut(tkn))),
 					});
 				}
 				None => tkn.state = TransferState::Finished,
@@ -542,7 +542,7 @@ impl<'a> ReadCtrl<'a> {
 				(None, None) => unreachable!("Empty Transfers are not allowed..."),
 			}
 
-			Some(tkn as *mut TransferToken)
+			Some(ptr::from_mut(tkn))
 		} else {
 			None
 		}

src/drivers/virtio/virtqueue/split.rs

@@ -220,7 +220,7 @@ impl DescrRing {
 
 					// Turn the raw pointer into a Pinned again, which will hold ownership of the Token
 					queue.borrow_mut().push_back(Transfer {
-						transfer_tkn: Some(Pinned::from_raw(tkn as *mut TransferToken)),
+						transfer_tkn: Some(Pinned::from_raw(ptr::from_mut(tkn))),
 					});
 				}
 				None => tkn.state = TransferState::Finished,

src/fd/mod.rs

@@ -1,5 +1,6 @@
 use alloc::sync::Arc;
 use core::ffi::{c_void, CStr};
+use core::ptr;
 use core::sync::atomic::{AtomicI32, Ordering};
 
 use ahash::RandomState;
@@ -136,7 +137,7 @@ impl SysLseek {
 #[inline]
 #[cfg(target_arch = "x86_64")]
 fn uhyve_send<T>(port: u16, data: &mut T) {
-	let ptr = VirtAddr(data as *mut _ as u64);
+	let ptr = VirtAddr(ptr::from_mut(data).addr() as u64);
 	let physical_address = paging::virtual_to_physical(ptr).unwrap();
 
 	unsafe {
@@ -150,7 +151,7 @@ fn uhyve_send<T>(port: u16, data: &mut T) {
 fn uhyve_send<T>(port: u16, data: &mut T) {
 	use core::arch::asm;
 
-	let ptr = VirtAddr(data as *mut _ as u64);
+	let ptr = VirtAddr(ptr::from_mut(data).addr() as u64);
 	let physical_address = paging::virtual_to_physical(ptr).unwrap();
 
 	unsafe {

src/lib.rs

@@ -18,6 +18,7 @@
 #![feature(noop_waker)]
 #![feature(pointer_byte_offsets)]
 #![feature(pointer_is_aligned)]
+#![feature(ptr_from_ref)]
 #![cfg_attr(target_arch = "aarch64", feature(specialization))]
 #![feature(strict_provenance)]
 #![cfg_attr(target_os = "none", no_std)]

src/scheduler/mod.rs

@@ -4,6 +4,7 @@ use alloc::rc::Rc;
 #[cfg(feature = "smp")]
 use alloc::vec::Vec;
 use core::cell::RefCell;
+use core::ptr;
 use core::sync::atomic::{AtomicU32, Ordering};
 
 use crossbeam_utils::Backoff;
@@ -583,7 +584,7 @@ impl PerCoreScheduler {
 			let mut borrowed = self.current_task.borrow_mut();
 			(
 				borrowed.id,
-				&mut borrowed.last_stack_pointer as *mut _ as *mut usize,
+				ptr::from_mut(&mut borrowed.last_stack_pointer) as *mut usize,
 				borrowed.prio,
 				borrowed.status,
 			)

src/syscalls/interfaces/uhyve.rs

@@ -1,7 +1,7 @@
 use alloc::alloc::{alloc, Layout};
 use alloc::boxed::Box;
 use alloc::vec::Vec;
-use core::mem;
+use core::{mem, ptr};
 
 #[cfg(target_arch = "x86_64")]
 use x86::io::*;
@@ -29,7 +29,7 @@ extern "C" {
 #[inline]
 #[cfg(target_arch = "x86_64")]
 pub(crate) fn uhyve_send<T>(port: u16, data: &mut T) {
-	let ptr = VirtAddr(data as *mut _ as u64);
+	let ptr = VirtAddr(ptr::from_mut(data).addr() as u64);
 	let physical_address = paging::virtual_to_physical(ptr).unwrap();
 
 	unsafe {
@@ -43,7 +43,7 @@ pub(crate) fn uhyve_send<T>(port: u16, data: &mut T) {
 pub(crate) fn uhyve_send<T>(port: u16, data: &mut T) {
 	use core::arch::asm;
 
-	let ptr = VirtAddr(data as *mut _ as u64);
+	let ptr = VirtAddr(ptr::from_mut(data).addr() as u64);
 	let physical_address = paging::virtual_to_physical(ptr).unwrap();
 
 	unsafe {