aarch64: Emit ADD X, Y, Y instead of SHL X, Y, #1 for SVE instructions.

On Neoverse V2, SVE ADD instructions have a throughput of 4, while shift instructions like SHL have a throughput of 2. We can lean on that to emit code like: add z31.b, z31.b, z31.b instead of: lsl z31.b, z31.b, #1 The implementation of this change for SVE vectors is similar to a prior patch <https://gcc.gnu.org/pipermail/gcc-patches/2024-August/659958.html> that adds the above functionality for Neon vectors. Here, the machine descriptor pattern is split up to separately accommodate left and right shifts, so we can specifically emit an add for all left shifts by 1. The patch was bootstrapped and regtested on aarch64-linux-gnu, no regression. OK for mainline? Signed-off-by: Soumya AR <soumyaa@nvidia.com> gcc/ChangeLog: * config/aarch64/aarch64-sve.md (*post_ra_v<optab><mode>3): Split pattern to accomodate left and right shifts separately. (*post_ra_v_ashl<mode>3): Matches left shifts with additional constraint to check for shifts by 1. (*post_ra_v_<optab><mode>3): Matches right shifts. gcc/testsuite/ChangeLog: * gcc.target/aarch64/sve/acle/asm/lsl_s16.c: Updated instances of lsl-1 with corresponding add. * gcc.target/aarch64/sve/acle/asm/lsl_s32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsl_s64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsl_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsl_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsl_u32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsl_u64.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsl_u8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsl_wide_s16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsl_wide_s32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsl_wide_s8.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsl_wide_u16.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsl_wide_u32.c: Likewise. * gcc.target/aarch64/sve/acle/asm/lsl_wide_u8.c: Likewise. * gcc.target/aarch64/sve/adr_1.c: Likewise. * gcc.target/aarch64/sve/adr_6.c: Likewise. * gcc.target/aarch64/sve/cond_mla_7.c: Likewise. * gcc.target/aarch64/sve/cond_mla_8.c: Likewise. * gcc.target/aarch64/sve/shift_2.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/ldnt1sh_gather_s64.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/ldnt1sh_gather_u64.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/ldnt1uh_gather_s64.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/ldnt1uh_gather_u64.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/rshl_s16.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/rshl_s32.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/rshl_s64.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/rshl_s8.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/rshl_u16.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/rshl_u32.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/rshl_u64.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/rshl_u8.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/stnt1h_scatter_s64.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/stnt1h_scatter_u64.c: Likewise. * gcc.target/aarch64/sve/sve_shl_add.c: New test.
iains · Sep 16, 2024 · 4af196b · 4af196b
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commit 4af196b
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diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md
@@ -4816,11 +4816,23 @@
 ;; Unpredicated shift operations by a constant (post-RA only).
 ;; These are generated by splitting a predicated instruction whose
 ;; predicate is unused.
-(define_insn "*post_ra_v<optab><mode>3"
+(define_insn "*post_ra_v_ashl<mode>3"
+  [(set (match_operand:SVE_I 0 "register_operand")
+	(ashift:SVE_I
+	  (match_operand:SVE_I 1 "register_operand")
+	  (match_operand:SVE_I 2 "aarch64_simd_lshift_imm")))]
+  "TARGET_SVE && reload_completed"
+  {@ [ cons: =0 , 1 , 2   ]
+     [ w	, w , vs1 ] add\t%0.<Vetype>, %1.<Vetype>, %1.<Vetype>
+     [ w	, w , Dl  ] lsl\t%0.<Vetype>, %1.<Vetype>, #%2
+  }
+)
+
+(define_insn "*post_ra_v_<optab><mode>3"
   [(set (match_operand:SVE_I 0 "register_operand" "=w")
-	(ASHIFT:SVE_I
+	(SHIFTRT:SVE_I
 	  (match_operand:SVE_I 1 "register_operand" "w")
-	  (match_operand:SVE_I 2 "aarch64_simd_<lr>shift_imm")))]
+	  (match_operand:SVE_I 2 "aarch64_simd_rshift_imm")))]
   "TARGET_SVE && reload_completed"
   "<shift>\t%0.<Vetype>, %1.<Vetype>, #%2"
 )

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_s16.c
@@ -296,7 +296,7 @@ TEST_UNIFORM_ZX (lsl_w0_s16_x_untied, svint16_t, uint16_t,
 
 /*
 ** lsl_1_s16_x_tied1:
-**	lsl	z0\.h, z0\.h, #1
+**	add	z0\.h, z0\.h, z0\.h
 **	ret
 */
 TEST_UNIFORM_Z (lsl_1_s16_x_tied1, svint16_t,
@@ -305,7 +305,7 @@ TEST_UNIFORM_Z (lsl_1_s16_x_tied1, svint16_t,
 
 /*
 ** lsl_1_s16_x_untied:
-**	lsl	z0\.h, z1\.h, #1
+**	add	z0\.h, z1\.h, z1\.h
 **	ret
 */
 TEST_UNIFORM_Z (lsl_1_s16_x_untied, svint16_t,

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_s32.c
@@ -296,7 +296,7 @@ TEST_UNIFORM_ZX (lsl_w0_s32_x_untied, svint32_t, uint32_t,
 
 /*
 ** lsl_1_s32_x_tied1:
-**	lsl	z0\.s, z0\.s, #1
+**	add	z0\.s, z0\.s, z0\.s
 **	ret
 */
 TEST_UNIFORM_Z (lsl_1_s32_x_tied1, svint32_t,
@@ -305,7 +305,7 @@ TEST_UNIFORM_Z (lsl_1_s32_x_tied1, svint32_t,
 
 /*
 ** lsl_1_s32_x_untied:
-**	lsl	z0\.s, z1\.s, #1
+**	add	z0\.s, z1\.s, z1\.s
 **	ret
 */
 TEST_UNIFORM_Z (lsl_1_s32_x_untied, svint32_t,

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_s64.c
@@ -296,7 +296,7 @@ TEST_UNIFORM_ZX (lsl_x0_s64_x_untied, svint64_t, uint64_t,
 
 /*
 ** lsl_1_s64_x_tied1:
-**	lsl	z0\.d, z0\.d, #1
+**	add	z0\.d, z0\.d, z0\.d
 **	ret
 */
 TEST_UNIFORM_Z (lsl_1_s64_x_tied1, svint64_t,
@@ -305,7 +305,7 @@ TEST_UNIFORM_Z (lsl_1_s64_x_tied1, svint64_t,
 
 /*
 ** lsl_1_s64_x_untied:
-**	lsl	z0\.d, z1\.d, #1
+**	add	z0\.d, z1\.d, z1\.d
 **	ret
 */
 TEST_UNIFORM_Z (lsl_1_s64_x_untied, svint64_t,

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_s8.c
@@ -296,7 +296,7 @@ TEST_UNIFORM_ZX (lsl_w0_s8_x_untied, svint8_t, uint8_t,
 
 /*
 ** lsl_1_s8_x_tied1:
-**	lsl	z0\.b, z0\.b, #1
+**	add	z0\.b, z0\.b, z0\.b
 **	ret
 */
 TEST_UNIFORM_Z (lsl_1_s8_x_tied1, svint8_t,
@@ -305,7 +305,7 @@ TEST_UNIFORM_Z (lsl_1_s8_x_tied1, svint8_t,
 
 /*
 ** lsl_1_s8_x_untied:
-**	lsl	z0\.b, z1\.b, #1
+**	add	z0\.b, z1\.b, z1\.b
 **	ret
 */
 TEST_UNIFORM_Z (lsl_1_s8_x_untied, svint8_t,

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_u16.c
@@ -296,7 +296,7 @@ TEST_UNIFORM_ZX (lsl_w0_u16_x_untied, svuint16_t, uint16_t,
 
 /*
 ** lsl_1_u16_x_tied1:
-**	lsl	z0\.h, z0\.h, #1
+**	add	z0\.h, z0\.h, z0\.h
 **	ret
 */
 TEST_UNIFORM_Z (lsl_1_u16_x_tied1, svuint16_t,
@@ -305,7 +305,7 @@ TEST_UNIFORM_Z (lsl_1_u16_x_tied1, svuint16_t,
 
 /*
 ** lsl_1_u16_x_untied:
-**	lsl	z0\.h, z1\.h, #1
+**	add	z0\.h, z1\.h, z1\.h
 **	ret
 */
 TEST_UNIFORM_Z (lsl_1_u16_x_untied, svuint16_t,

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_u32.c
@@ -296,7 +296,7 @@ TEST_UNIFORM_ZX (lsl_w0_u32_x_untied, svuint32_t, uint32_t,
 
 /*
 ** lsl_1_u32_x_tied1:
-**	lsl	z0\.s, z0\.s, #1
+**	add	z0\.s, z0\.s, z0\.s
 **	ret
 */
 TEST_UNIFORM_Z (lsl_1_u32_x_tied1, svuint32_t,
@@ -305,7 +305,7 @@ TEST_UNIFORM_Z (lsl_1_u32_x_tied1, svuint32_t,
 
 /*
 ** lsl_1_u32_x_untied:
-**	lsl	z0\.s, z1\.s, #1
+**	add	z0\.s, z1\.s, z1\.s
 **	ret
 */
 TEST_UNIFORM_Z (lsl_1_u32_x_untied, svuint32_t,

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_u64.c
@@ -296,7 +296,7 @@ TEST_UNIFORM_ZX (lsl_x0_u64_x_untied, svuint64_t, uint64_t,
 
 /*
 ** lsl_1_u64_x_tied1:
-**	lsl	z0\.d, z0\.d, #1
+**	add	z0\.d, z0\.d, z0\.d
 **	ret
 */
 TEST_UNIFORM_Z (lsl_1_u64_x_tied1, svuint64_t,
@@ -305,7 +305,7 @@ TEST_UNIFORM_Z (lsl_1_u64_x_tied1, svuint64_t,
 
 /*
 ** lsl_1_u64_x_untied:
-**	lsl	z0\.d, z1\.d, #1
+**	add	z0\.d, z1\.d, z1\.d
 **	ret
 */
 TEST_UNIFORM_Z (lsl_1_u64_x_untied, svuint64_t,

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_u8.c
@@ -296,7 +296,7 @@ TEST_UNIFORM_ZX (lsl_w0_u8_x_untied, svuint8_t, uint8_t,
 
 /*
 ** lsl_1_u8_x_tied1:
-**	lsl	z0\.b, z0\.b, #1
+**	add	z0\.b, z0\.b, z0\.b
 **	ret
 */
 TEST_UNIFORM_Z (lsl_1_u8_x_tied1, svuint8_t,
@@ -305,7 +305,7 @@ TEST_UNIFORM_Z (lsl_1_u8_x_tied1, svuint8_t,
 
 /*
 ** lsl_1_u8_x_untied:
-**	lsl	z0\.b, z1\.b, #1
+**	add	z0\.b, z1\.b, z1\.b
 **	ret
 */
 TEST_UNIFORM_Z (lsl_1_u8_x_untied, svuint8_t,

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_wide_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_wide_s16.c
@@ -276,7 +276,7 @@ TEST_UNIFORM_ZX (lsl_wide_x0_s16_x_untied, svint16_t, uint64_t,
 
 /*
 ** lsl_wide_1_s16_x_tied1:
-**	lsl	z0\.h, z0\.h, #1
+**	add	z0\.h, z0\.h, z0\.h
 **	ret
 */
 TEST_UNIFORM_Z (lsl_wide_1_s16_x_tied1, svint16_t,
@@ -285,7 +285,7 @@ TEST_UNIFORM_Z (lsl_wide_1_s16_x_tied1, svint16_t,
 
 /*
 ** lsl_wide_1_s16_x_untied:
-**	lsl	z0\.h, z1\.h, #1
+**	add	z0\.h, z1\.h, z1\.h
 **	ret
 */
 TEST_UNIFORM_Z (lsl_wide_1_s16_x_untied, svint16_t,

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_wide_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_wide_s32.c
@@ -276,7 +276,7 @@ TEST_UNIFORM_ZX (lsl_wide_x0_s32_x_untied, svint32_t, uint64_t,
 
 /*
 ** lsl_wide_1_s32_x_tied1:
-**	lsl	z0\.s, z0\.s, #1
+**	add	z0\.s, z0\.s, z0\.s
 **	ret
 */
 TEST_UNIFORM_Z (lsl_wide_1_s32_x_tied1, svint32_t,
@@ -285,7 +285,7 @@ TEST_UNIFORM_Z (lsl_wide_1_s32_x_tied1, svint32_t,
 
 /*
 ** lsl_wide_1_s32_x_untied:
-**	lsl	z0\.s, z1\.s, #1
+**	add	z0\.s, z1\.s, z1\.s
 **	ret
 */
 TEST_UNIFORM_Z (lsl_wide_1_s32_x_untied, svint32_t,

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_wide_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_wide_s8.c
@@ -276,7 +276,7 @@ TEST_UNIFORM_ZX (lsl_wide_x0_s8_x_untied, svint8_t, uint64_t,
 
 /*
 ** lsl_wide_1_s8_x_tied1:
-**	lsl	z0\.b, z0\.b, #1
+**	add	z0\.b, z0\.b, z0\.b
 **	ret
 */
 TEST_UNIFORM_Z (lsl_wide_1_s8_x_tied1, svint8_t,
@@ -285,7 +285,7 @@ TEST_UNIFORM_Z (lsl_wide_1_s8_x_tied1, svint8_t,
 
 /*
 ** lsl_wide_1_s8_x_untied:
-**	lsl	z0\.b, z1\.b, #1
+**	add	z0\.b, z1\.b, z1\.b
 **	ret
 */
 TEST_UNIFORM_Z (lsl_wide_1_s8_x_untied, svint8_t,

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_wide_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_wide_u16.c
@@ -276,7 +276,7 @@ TEST_UNIFORM_ZX (lsl_wide_x0_u16_x_untied, svuint16_t, uint64_t,
 
 /*
 ** lsl_wide_1_u16_x_tied1:
-**	lsl	z0\.h, z0\.h, #1
+**	add	z0\.h, z0\.h, z0\.h
 **	ret
 */
 TEST_UNIFORM_Z (lsl_wide_1_u16_x_tied1, svuint16_t,
@@ -285,7 +285,7 @@ TEST_UNIFORM_Z (lsl_wide_1_u16_x_tied1, svuint16_t,
 
 /*
 ** lsl_wide_1_u16_x_untied:
-**	lsl	z0\.h, z1\.h, #1
+**	add	z0\.h, z1\.h, z1\.h
 **	ret
 */
 TEST_UNIFORM_Z (lsl_wide_1_u16_x_untied, svuint16_t,

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_wide_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_wide_u32.c
@@ -276,7 +276,7 @@ TEST_UNIFORM_ZX (lsl_wide_x0_u32_x_untied, svuint32_t, uint64_t,
 
 /*
 ** lsl_wide_1_u32_x_tied1:
-**	lsl	z0\.s, z0\.s, #1
+**	add	z0\.s, z0\.s, z0\.s
 **	ret
 */
 TEST_UNIFORM_Z (lsl_wide_1_u32_x_tied1, svuint32_t,
@@ -285,7 +285,7 @@ TEST_UNIFORM_Z (lsl_wide_1_u32_x_tied1, svuint32_t,
 
 /*
 ** lsl_wide_1_u32_x_untied:
-**	lsl	z0\.s, z1\.s, #1
+**	add	z0\.s, z1\.s, z1\.s
 **	ret
 */
 TEST_UNIFORM_Z (lsl_wide_1_u32_x_untied, svuint32_t,

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_wide_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/lsl_wide_u8.c
@@ -276,7 +276,7 @@ TEST_UNIFORM_ZX (lsl_wide_x0_u8_x_untied, svuint8_t, uint64_t,
 
 /*
 ** lsl_wide_1_u8_x_tied1:
-**	lsl	z0\.b, z0\.b, #1
+**	add	z0\.b, z0\.b, z0\.b
 **	ret
 */
 TEST_UNIFORM_Z (lsl_wide_1_u8_x_tied1, svuint8_t,
@@ -285,7 +285,7 @@ TEST_UNIFORM_Z (lsl_wide_1_u8_x_tied1, svuint8_t,
 
 /*
 ** lsl_wide_1_u8_x_untied:
-**	lsl	z0\.b, z1\.b, #1
+**	add	z0\.b, z1\.b, z1\.b
 **	ret
 */
 TEST_UNIFORM_Z (lsl_wide_1_u8_x_untied, svuint8_t,

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/adr_1.c b/gcc/testsuite/gcc.target/aarch64/sve/adr_1.c
@@ -29,12 +29,10 @@
 
 TEST_ALL (LOOP)
 
-/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.b,} 2 } } */
-/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.b,} 2 } } */
+/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.b,} 4 } } */
 /* { dg-final { scan-assembler-not {\tadr\tz[0-9]+\.b,} } } */
 
-/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.h,} 2 } } */
-/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.h,} 2 } } */
+/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.h,} 4 } } */
 /* { dg-final { scan-assembler-not {\tadr\tz[0-9]+\.h,} } } */
 
 /* { dg-final { scan-assembler-not {\tadd\tz[0-9]+\.s,} } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/adr_6.c b/gcc/testsuite/gcc.target/aarch64/sve/adr_6.c
@@ -31,8 +31,8 @@ TEST_TYPE (uint16_t, 128)
 TEST_TYPE (int32_t, 128)
 TEST_TYPE (uint32_t, 128)
 
-/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.b,} 6 } } */
-/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.b,} 6 } } */
+/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.b,} 8 } } */
+/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.b,} 4 } } */
 
 /* { dg-final { scan-assembler-times {\tadr\tz[0-9]+\.s, \[z[0-9]+\.s, z[0-9]+\.s, lsl #?1\]\n} 4 } } */
 /* { dg-final { scan-assembler-times {\tadr\tz[0-9]+\.s, \[z[0-9]+\.s, z[0-9]+\.s, lsl #?2\]\n} 4 } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_mla_7.c b/gcc/testsuite/gcc.target/aarch64/sve/cond_mla_7.c
@@ -31,19 +31,19 @@
 
 TEST_ALL (DEF_LOOP)
 
-/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.b, z[0-9]+\.b, #1\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.b, z[0-9]+\.b, z[0-9]+\.b\n} 2 } } */
 /* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.b, z[0-9]+\.b, #2\n} 2 } } */
 /* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.b, z[0-9]+\.b, #7\n} 2 } } */
 
-/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.h, z[0-9]+\.h, #1\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.h, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */
 /* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.h, z[0-9]+\.h, #2\n} 2 } } */
 /* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.h, z[0-9]+\.h, #15\n} 2 } } */
 
-/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.s, z[0-9]+\.s, #1\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.s, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */
 /* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.s, z[0-9]+\.s, #2\n} 2 } } */
 /* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.s, z[0-9]+\.s, #31\n} 2 } } */
 
-/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.d, z[0-9]+\.d, #1\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 2 } } */
 /* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.d, z[0-9]+\.d, #2\n} 2 } } */
 /* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.d, z[0-9]+\.d, #63\n} 2 } } */
 

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_mla_8.c b/gcc/testsuite/gcc.target/aarch64/sve/cond_mla_8.c
@@ -31,19 +31,19 @@
 
 TEST_ALL (DEF_LOOP)
 
-/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.b, z[0-9]+\.b, #1\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.b, z[0-9]+\.b, z[0-9]+\.b\n} 2 } } */
 /* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.b, z[0-9]+\.b, #2\n} 2 } } */
 /* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.b, z[0-9]+\.b, #7\n} 2 } } */
 
-/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.h, z[0-9]+\.h, #1\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.h, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */
 /* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.h, z[0-9]+\.h, #2\n} 2 } } */
 /* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.h, z[0-9]+\.h, #15\n} 2 } } */
 
-/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.s, z[0-9]+\.s, #1\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.s, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */
 /* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.s, z[0-9]+\.s, #2\n} 2 } } */
 /* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.s, z[0-9]+\.s, #31\n} 2 } } */
 
-/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.d, z[0-9]+\.d, #1\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.d, z[0-9]+\.d, z[0-9]+\.d\n} 2 } } */
 /* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.d, z[0-9]+\.d, #2\n} 2 } } */
 /* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.d, z[0-9]+\.d, #63\n} 2 } } */
 

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/shift_2.c b/gcc/testsuite/gcc.target/aarch64/sve/shift_2.c
@@ -44,9 +44,9 @@ TEST_TYPE (uint32_t, 128, 31)
 /* { dg-final { scan-assembler-times {\tasr\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */
 /* { dg-final { scan-assembler-times {\tasr\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */
 
-/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.b, z[0-9]+\.b, #1\n} 6 } } */
-/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.h, z[0-9]+\.h, #1\n} 4 } } */
-/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.s, z[0-9]+\.s, #1\n} 2 } } */
+/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.b, z[0-9]+\.b, z[0-9]+\.b\n} 6 } } */
+/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.h, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */
+/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.s, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */
 
 /* { dg-final { scan-assembler-times {\tlsr\tz[0-9]+\.b, z[0-9]+\.b, #1\n} 3 } } */
 /* { dg-final { scan-assembler-times {\tlsr\tz[0-9]+\.h, z[0-9]+\.h, #1\n} 2 } } */