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aarch64: Don't emit invalid zero/sign-extend syntax
Given the following C function:
double *f(double *p, unsigned x)
{
return p + x;
}
prior to this patch, GCC at -O2 would generate:
f:
add x0, x0, x1, uxtw 3
ret
but this add instruction uses architecturally-invalid syntax: the width
of the third operand conflicts with the width of the extension
specifier. The third operand is only permitted to be an x register when
the extension specifier is (u|s)xtx.
This instruction, and analogous insns for adds, sub, subs, and cmp, are
rejected by clang, but accepted by binutils. Assembling and
disassembling such an insn with binutils gives the architecturally-valid
version in the disassembly:
0: 8b214c00 add x0, x0, w1, uxtw #3
This patch fixes several patterns in the AArch64 backend to use the
standard syntax as specified in the Arm ARM such that GCC's output can
be assembled by assemblers other than GAS.
---
gcc/ChangeLog:
* config/aarch64/aarch64.md
(*adds_<optab><ALLX:mode>_<GPI:mode>): Ensure extended operand
agrees with width of extension specifier.
(*subs_<optab><ALLX:mode>_<GPI:mode>): Likewise.
(*adds_<optab><ALLX:mode>_shift_<GPI:mode>): Likewise.
(*subs_<optab><ALLX:mode>_shift_<GPI:mode>): Likewise.
(*add_<optab><ALLX:mode>_<GPI:mode>): Likewise.
(*add_<optab><ALLX:mode>_shft_<GPI:mode>): Likewise.
(*add_uxt<mode>_shift2): Likewise.
(*sub_<optab><ALLX:mode>_<GPI:mode>): Likewise.
(*sub_<optab><ALLX:mode>_shft_<GPI:mode>): Likewise.
(*sub_uxt<mode>_shift2): Likewise.
(*cmp_swp_<optab><ALLX:mode>_reg<GPI:mode>): Likewise.
(*cmp_swp_<optab><ALLX:mode>_shft_<GPI:mode>): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/adds3.c: Fix test w.r.t. new syntax.
* gcc.target/aarch64/cmp.c: Likewise.
* gcc.target/aarch64/subs3.c: Likewise.
* gcc.target/aarch64/subsp.c: Likewise.
* gcc.target/aarch64/extend-syntax.c: New test.- Loading branch information
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,120 @@ | ||
| /* { dg-do compile } */ | ||
| /* { dg-options "-O2" } */ | ||
|
|
||
| // Hits *add_uxtdi_shift2 (*add_uxt<mode>_shift2). | ||
| /* | ||
| ** add1: | ||
| ** add x0, x0, w1, uxtw 3 | ||
| ** ret | ||
| */ | ||
| unsigned long long *add1(unsigned long long *p, unsigned x) | ||
| { | ||
| return p + x; | ||
| } | ||
|
|
||
| // Hits *add_zero_extendsi_di (*add_<optab><ALLX:mode>_<GPI:mode>). | ||
| /* | ||
| ** add2: | ||
| ** add x0, x0, w1, uxtw | ||
| ** ret | ||
| */ | ||
| unsigned long long add2(unsigned long long x, unsigned y) | ||
| { | ||
| return x + y; | ||
| } | ||
|
|
||
| // Hits *add_extendsi_shft_di (*add_<optab><ALLX:mode>_shft_<GPI:mode>). | ||
| /* | ||
| ** add3: | ||
| ** add x0, x0, w1, sxtw 3 | ||
| ** ret | ||
| */ | ||
| double *add3(double *p, int x) | ||
| { | ||
| return p + x; | ||
| } | ||
|
|
||
| // Hits *sub_zero_extendsi_di (*sub_<optab><ALLX:mode>_<GPI:mode>). | ||
| /* | ||
| ** sub1: | ||
| ** sub x0, x0, w1, uxtw | ||
| ** ret | ||
| */ | ||
| unsigned long long sub1(unsigned long long x, unsigned n) | ||
| { | ||
| return x - n; | ||
| } | ||
|
|
||
| // Hits *sub_uxtdi_shift2 (*sub_uxt<mode>_shift2). | ||
| /* | ||
| ** sub2: | ||
| ** sub x0, x0, w1, uxtw 3 | ||
| ** ret | ||
| */ | ||
| double *sub2(double *x, unsigned n) | ||
| { | ||
| return x - n; | ||
| } | ||
|
|
||
| // Hits *sub_extendsi_shft_di (*sub_<optab><ALLX:mode>_shft_<GPI:mode>). | ||
| /* | ||
| ** sub3: | ||
| ** sub x0, x0, w1, sxtw 3 | ||
| ** ret | ||
| */ | ||
| double *sub3(double *p, int n) | ||
| { | ||
| return p - n; | ||
| } | ||
|
|
||
| // Hits *adds_zero_extendsi_di (*adds_<optab><ALLX:mode>_<GPI:mode>). | ||
| int adds1(unsigned long long x, unsigned y) | ||
| { | ||
| /* { dg-final { scan-assembler-times "adds\tx\[0-9\]+, x\[0-9\]+, w\[0-9\]+, uxtw" 1 } } */ | ||
| unsigned long long l = x + y; | ||
| return !!l; | ||
| } | ||
|
|
||
| // Hits *adds_extendsi_shift_di (*adds_<optab><ALLX:mode>_shift_<GPI:mode>). | ||
| int adds2(long long x, int y) | ||
| { | ||
| /* { dg-final { scan-assembler-times "adds\tx\[0-9\]+, x\[0-9\]+, w\[0-9\]+, sxtw 3" 1 } } */ | ||
| long long t = x + ((long long)y << 3); | ||
| return !!t; | ||
| } | ||
|
|
||
| // Hits *subs_zero_extendsi_di (*subs_<optab><ALLX:mode>_<GPI:mode>). | ||
| unsigned long long z; | ||
| int subs1(unsigned long long x, unsigned y) | ||
| { | ||
| /* { dg-final { scan-assembler-times "subs\tx\[0-9\]+, x\[0-9\]+, w\[0-9\]+, uxtw" 1 } } */ | ||
| unsigned long long t = x - y; | ||
| z = t; | ||
| return !!t; | ||
| } | ||
|
|
||
| // Hits *subs_extendsi_shift_di (*subs_<optab><ALLX:mode>_shift_<GPI:mode>). | ||
| unsigned long long *w; | ||
| int subs2(unsigned long long *x, int y) | ||
| { | ||
| /* { dg-final { scan-assembler-times "subs\tx\[0-9\]+, x\[0-9\]+, w\[0-9\]+, sxtw 3" 1 } } */ | ||
| unsigned long long *t = x - y; | ||
| w = t; | ||
| return !!t; | ||
| } | ||
|
|
||
| // Hits *cmp_swp_zero_extendsi_regdi (*cmp_swp_<optab><ALLX:mode>_reg<GPI:mode>). | ||
| int cmp(unsigned long long x, unsigned y) | ||
| { | ||
| /* { dg-final { scan-assembler-times "cmp\tx\[0-9\]+, w\[0-9\]+, uxtw" 1 } } */ | ||
| return !!(x - y); | ||
| } | ||
|
|
||
| // Hits *cmp_swp_extendsi_shft_di (*cmp_swp_<optab><ALLX:mode>_shft_<GPI:mode>). | ||
| int cmp2(unsigned long long x, int y) | ||
| { | ||
| /* { dg-final { scan-assembler-times "cmp\tx\[0-9\]+, w\[0-9\]+, sxtw 3" 1 } } */ | ||
| return x == ((unsigned long long)y << 3); | ||
| } | ||
|
|
||
| /* { dg-final { check-function-bodies "**" "" "" } } */ |
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