Enabling commits and typo fixs

core/src/main/scala/spinal/core/IODirection.scala

@@ -56,6 +56,12 @@ sealed trait IODirection extends BaseTypeFactory {
     */
   def port[T <: Data](data: HardType[T]): T = port(data())
 
+  /** Declare a port without braces, spaceful syntax
+   *
+   * See [[IODirection]] for other syntax.
+   */
+  def ports[T <: Data](datas: T*): Seq[T] = datas.map(x => port(x))
+
   /** Declare a [[SpinalEnum]] port without braces, spaceful syntax
     *
     * See [[IODirection]] for other syntax.

lib/src/main/scala/spinal/lib/bus/wishbone/WishboneDecoder.scala

@@ -57,10 +57,10 @@ class WishboneDecoder(config : WishboneConfig, decodings : Seq[AddressMapping])
   val selector = Vec(decodings.map(_.hit(io.input.ADR) && io.input.CYC))
   val selectorIndex = OHToUInt(selector)
 
-  // Generate the CYC sygnal for the selected slave
+  // Generate the CYC signal for the selected slave
   (io.outputs.map(_.CYC), selector).zipped.foreach(_ := _)
 
-  //Implementing the multiplexer logic, it thakes the one Hot bit vector/bit array as input
+  //Implementing the multiplexer logic, it takes the one Hot bit vector/bit array as input
   val selectedOutput = io.outputs(selectorIndex)
 
   io.input.ACK := selectedOutput.ACK

lib/src/main/scala/spinal/lib/sim/bus/wishbone/WishboneDriver.scala

@@ -137,7 +137,7 @@ class WishboneDriver(bus: Wishbone, clockdomain: ClockDomain){
       var timeout = 100
       while(busStatus.isCycle){
         timeout -= 1
-        assert(timeout > 0, s"${this} timed out")
+        assert(timeout > 0, s"${this} ${bus} timed out")
 
         requests += busStatus.isRequestAck.toInt