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dt-bindings: dmaengine: Document qcom,gpi dma binding
Add devicetree binding documentation for GPI DMA controller implemented on Qualcomm SoCs Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20201109085450.24843-2-vkoul@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
%YAML 1.2 | ||
--- | ||
$id: http://devicetree.org/schemas/dma/qcom,gpi.yaml# | ||
$schema: http://devicetree.org/meta-schemas/core.yaml# | ||
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title: Qualcomm Technologies Inc GPI DMA controller | ||
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maintainers: | ||
- Vinod Koul <vkoul@kernel.org> | ||
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description: | | ||
QCOM GPI DMA controller provides DMA capabilities for | ||
peripheral buses such as I2C, UART, and SPI. | ||
allOf: | ||
- $ref: "dma-controller.yaml#" | ||
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properties: | ||
compatible: | ||
enum: | ||
- qcom,sdm845-gpi-dma | ||
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reg: | ||
maxItems: 1 | ||
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interrupts: | ||
description: | ||
Interrupt lines for each GPI instance | ||
maxItems: 13 | ||
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"#dma-cells": | ||
const: 3 | ||
description: > | ||
DMA clients must use the format described in dma.txt, giving a phandle | ||
to the DMA controller plus the following 3 integer cells: | ||
- channel: if set to 0xffffffff, any available channel will be allocated | ||
for the client. Otherwise, the exact channel specified will be used. | ||
- seid: serial id of the client as defined in the SoC documentation. | ||
- client: type of the client as defined in dt-bindings/dma/qcom-gpi.h | ||
iommus: | ||
maxItems: 1 | ||
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dma-channels: | ||
maximum: 31 | ||
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dma-channel-mask: | ||
maxItems: 1 | ||
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required: | ||
- compatible | ||
- reg | ||
- interrupts | ||
- "#dma-cells" | ||
- iommus | ||
- dma-channels | ||
- dma-channel-mask | ||
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additionalProperties: false | ||
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examples: | ||
- | | ||
#include <dt-bindings/interrupt-controller/arm-gic.h> | ||
#include <dt-bindings/dma/qcom-gpi.h> | ||
gpi_dma0: dma-controller@800000 { | ||
compatible = "qcom,gpi-dma"; | ||
#dma-cells = <3>; | ||
reg = <0x00800000 0x60000>; | ||
iommus = <&apps_smmu 0x0016 0x0>; | ||
dma-channels = <13>; | ||
dma-channel-mask = <0xfa>; | ||
interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, | ||
<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, | ||
<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, | ||
<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, | ||
<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, | ||
<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, | ||
<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, | ||
<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, | ||
<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, | ||
<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, | ||
<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, | ||
<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, | ||
<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; | ||
}; | ||
... |
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/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ | ||
/* Copyright (c) 2020, Linaro Ltd. */ | ||
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#ifndef __DT_BINDINGS_DMA_QCOM_GPI_H__ | ||
#define __DT_BINDINGS_DMA_QCOM_GPI_H__ | ||
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#define QCOM_GPI_SPI 1 | ||
#define QCOM_GPI_UART 2 | ||
#define QCOM_GPI_I2C 3 | ||
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#endif /* __DT_BINDINGS_DMA_QCOM_GPI_H__ */ |