This is python library/program for extract some information from HDL designs. It uses hdlConvertorAst as dependence for reading/parsing VHDL/Verilog/SystemVerilog sources.
This module is under LGPLv3 license. See LICENSE file for more details.
hdl_analyzer_project.py script can be used to manipulate/create hdl_analyzer JSN project file.
hdl_analyzer_hiearchy.py script can be used to analyze hiearchy of module/instance.