Setting version to 0.5.0-RC2

Add support for scala 2.13 for helpers

Signed-off-by: Jean Bruant <jean.bruant@ovhcloud.com>

helpers/src/main/scala/tools/ModulePreset.scala

@@ -3,7 +3,6 @@ package sv2chisel.helpers.tools
 import chisel3.experimental.{RunFirrtlTransform}
 
 import firrtl._
-import firrtl.PrimOps._
 import firrtl.ir._
 import firrtl.ir.{AsyncResetType}
 import firrtl.annotations._
@@ -54,8 +53,8 @@ class ModulePreset extends Transform with DependencyAPIMigration with LazyLoggin
   ): CircuitState = {
 
     // Annotations to be appended and returned as result of the transform
-    val annos         = cs.annotations.to[ArrayBuffer]
-    val moduleSet     = presetModules.to[HashSet]
+    val annos         = ArrayBuffer(cs.annotations.toSeq:_*)
+    val moduleSet     = HashSet(presetModules.toSeq:_*)
     val circuitTarget = CircuitTarget(cs.circuit.main)
 
     /** Update annotated module
@@ -98,7 +97,7 @@ class ModulePreset extends Transform with DependencyAPIMigration with LazyLoggin
     // ensure that modules are processed in hierarchy order (avoid multiple runs)
     val modules = cs.circuit.modules.reverse.map(processModule)
     val circuit = cs.circuit.copy(modules = modules.reverse)
-    val result  = cs.copy(circuit = circuit, annotations = annos)
+    val result  = cs.copy(circuit = circuit, annotations = annos.toSeq)
     if (moduleSet.isEmpty) {
       result
     } else {

helpers/src/main/scala/tools/ParamWrapperGenerator.scala

@@ -68,7 +68,7 @@ private final case class VerilogPort(
   }
 
   /** emit the port for wrapper IOs */
-  def emit(): String = {
+  def emit: String = {
     s"$dir${getVerilogTypeRec(tpe)} $name"
   }
 
@@ -359,7 +359,7 @@ private final class VerilogParams() {
   }
 
   /** Emit the current set of parameters as verilog string for wrapper declaration */
-  def emit(): String = {
+  def emit: String = {
     params
       .map(p => {
         val decl = s"parameter ${p._1}"
@@ -515,7 +515,7 @@ object ParamWrapperGenerator {
     for ((p, m) <- instances) {
       verilogParams.addParams(p)
 
-      val ed                 = ChiselGen.elaborate(m.apply, args)
+      val ed                 = ChiselGen.elaborate(m.apply(), args)
       val (ports, hasReset)  = getPorts(ed.designOption.get, forcePreset, unflatPorts)
       val (topName, renames) = getNames(ed.designOption.get)
       val instName           = renames.newTopName(topName)
@@ -546,7 +546,7 @@ object ParamWrapperGenerator {
 
     val wrapper = ArrayBuffer[String]()
     wrapper += s"module $emittedName"
-    wrapper += verilogParams.emit()
+    wrapper += verilogParams.emit
     wrapper += autoIOs.map(_.emit).mkString("  (\n    ", ",\n    ", "\n  );\n")
     wrapper += "  initial begin\n"
     wrapper += "    if (!( "
@@ -602,7 +602,7 @@ object VerilogPortWrapper {
       args: Array[String] = Array.empty
   ): (String, String) = {
 
-    val ed                = ChiselGen.elaborate(module.apply, args)
+    val ed                = ChiselGen.elaborate(module.apply(), args)
     val (ports, hasReset) = getPorts(ed.designOption.get, forcePreset)
 
     val origInstName = ed.designOption.get.desiredName

helpers/src/test/scala/HwEnumSpec.scala

@@ -71,9 +71,9 @@ class HwEnumSpec extends AnyFlatSpec with VerilogMatchers {
       }
     }
     val verilog = (new ChiselStage()).emitVerilog(new Example(), setTestRunDir)
-    verilog should contain ("wire [1:0] test = in ? 2'h0 : 2'h2;")
-    verilog should contain ("wire  bool = funHw == 2'h0;")
-    verilog should contain ("assign out = bool ? test : 2'h0;")
+    verilog should containStr ("wire [1:0] test = in ? 2'h0 : 2'h2;")
+    verilog should containStr ("wire  bool = funHw == 2'h0;")
+    verilog should containStr ("assign out = bool ? test : 2'h0;")
 
   }
 
@@ -132,9 +132,9 @@ class HwEnumSpec extends AnyFlatSpec with VerilogMatchers {
       }
     }
     val verilog = (new ChiselStage()).emitVerilog(new Example(), setTestRunDir)
-    verilog should contain ("wire [3:0] test = in ? 4'h0 : 4'hc;")
-    verilog should contain ("wire  bool = funHw == 4'hc;")
-    verilog should contain ("assign out = bool ? test : 4'h0;")
+    verilog should containStr ("wire [3:0] test = in ? 4'h0 : 4'hc;")
+    verilog should containStr ("wire  bool = funHw == 4'hc;")
+    verilog should containStr ("assign out = bool ? test : 4'h0;")
 
   }
 

helpers/src/test/scala/bundleconvertSpec.scala

@@ -34,10 +34,10 @@ class bundleconvertSpec extends AnyFlatSpec with VerilogMatchers {
     }
     val verilog = (new ChiselStage()).emitVerilog(new SubRangeBundle(), setTestRunDir)
 
-    verilog should contain ("assign out_a = 1'h0;")
-    verilog should contain ("assign out_b = 1'h1;")
-    verilog should contain ("assign out_c = 5'h4;")
-    verilog should contain ("assign out_d = 1'h1;")
+    verilog should containStr ("assign out_a = 1'h0;")
+    verilog should containStr ("assign out_b = 1'h1;")
+    verilog should containStr ("assign out_c = 5'h4;")
+    verilog should containStr ("assign out_d = 1'h1;")
   }
 
 }

helpers/src/test/scala/tools/ChiselGenSpec.scala

@@ -26,7 +26,7 @@ class ChiselGenSpec extends AnyFlatSpec with VerilogMatchers {
 
   it should "just works with syncronous Reset" in {
     val verilog = ChiselGen.emit(new SimpleRegInit(), setTestRunDir)
-    verilog should contain(
+    verilog should containStr(
         "always @(posedge clock) begin",
         "if (reset) begin",
         "r <= 1'h0;",
@@ -39,8 +39,8 @@ class ChiselGenSpec extends AnyFlatSpec with VerilogMatchers {
 
   it should "just works with Preset" in {
     val verilog = ChiselGen.emitPreset(new SimpleRegInit(), setTestRunDir)
-    verilog should contain("reg  r = 1'h0;")
-    verilog should contain(
+    verilog should containStr("reg  r = 1'h0;")
+    verilog should containStr(
         "always @(posedge clock) begin",
         "r <= in;",
         "end"

helpers/src/test/scala/tools/DeepWhenSpec.scala

@@ -43,14 +43,14 @@ class DeepWhenSpec extends AnyFlatSpec with VerilogMatchers {
     val raw       = ChiselStage.emitVerilog(new BasicWhenInner())
     val processed = getProcessedVerilog(new BasicWhenInner())
 
-    raw should contain("innerA <= in;", "innerB <= in;")
+    raw should containStr("innerA <= in;", "innerB <= in;")
     processed shouldNot contain("innerA <= in;", "innerB <= in;")
   }
   it should "work with basic assignations" in {
     val processed = getProcessedVerilog(new BasicWhenInner())
 
-    processed should contain("if (en) begin", "innerA <= in;", "end")
-    processed should contain("if (~en) begin", "innerB <= in;", "end")
+    processed should containStr("if (en) begin", "innerA <= in;", "end")
+    processed should containStr("if (~en) begin", "innerB <= in;", "end")
   }
 
   class MoreAdvancedInner() extends Module {
@@ -75,9 +75,9 @@ class DeepWhenSpec extends AnyFlatSpec with VerilogMatchers {
 
   it should "work with advanced assignations" in {
     val processed = getProcessedVerilog(new MoreAdvancedInner())
-    processed should contain("if (en) begin", "inner1_test <= in;", "end")
-    processed should contain("if (en) begin", "inner1_testV_0 <= in;", "end")
-    processed should contain("if (en) begin", "inner1_testV_1 <= in;", "end")
+    processed should containStr("if (en) begin", "inner1_test <= in;", "end")
+    processed should containStr("if (en) begin", "inner1_testV_0 <= in;", "end")
+    processed should containStr("if (en) begin", "inner1_testV_1 <= in;", "end")
   }
 
   class InnerInner() extends Module {
@@ -102,7 +102,7 @@ class DeepWhenSpec extends AnyFlatSpec with VerilogMatchers {
   it should "work with inner inner assignations" in {
     val processed = getProcessedVerilog(new InnerInner())
 
-    processed should contain("if (cond_0 & cond_1) begin", "inner2 <= inner1;", "end")
-    processed should contain("if (cond_0) begin", "inner1 <= in;", "end")
+    processed should containStr("if (cond_0 & cond_1) begin", "inner2 <= inner1;", "end")
+    processed should containStr("if (cond_0) begin", "inner1 <= in;", "end")
   }
 }

helpers/src/test/scala/tools/ParamWrapperGeneratorSpec.scala

@@ -438,8 +438,8 @@ class ParamWrapperGeneratorSpec extends AnyFlatSpec with VerilogMatchers {
     val result = ParamWrapperGenerator.emit(instances, args = setTestRunDir)
     result should containExactly("module Test_0(")
     result should containExactly("module Test_1(")
-    result should contain("verilog_ext_module #(.WIDTH(5)) inner (")
-    result should contain("verilog_ext_module #(.WIDTH(10)) inner (")
+    result should containStr("verilog_ext_module #(.WIDTH(5)) inner (")
+    result should containStr("verilog_ext_module #(.WIDTH(10)) inner (")
   }
 
   it should s"handle forced names for top module" in {

helpers/src/test/scala/utils/VerilogMatchers.scala

@@ -7,27 +7,45 @@ package sv2chiselHelpersTests.utils
 import org.scalatest._
 import matchers.should._
 
+import collection.mutable.ArrayBuffer
+
 trait VerilogMatchers extends Matchers {
   import matchers._
 
   /** Checks that the emitted circuit has the expected lines in order */
   def containExactly(expectedLines: String*) = new VerilogStrictStringsMatcher(expectedLines)
-  def contain(expectedLines: String*)     = new VerilogFlexStringsMatcher(expectedLines)
+  def containStr(expectedLines: String*)     = new VerilogFlexStringsMatcher(expectedLines)
+
+  def findFaillingLine(data: Seq[String], expected: Seq[String]): String = {
+    val msg = ArrayBuffer[String]()
+    val starts = data.zipWithIndex.collect { case (s, t) if (s == expected.head) => t }
+    if(starts.isEmpty) msg += s"[DEBUG] Unable to find a first matching line (${expected.head})"
+    starts.foreach(i => {
+      msg += s"DEBUG: starting at index $i"
+      data.drop(i).zip(expected).foreach { 
+        case (chisel, exp) if (chisel != exp ) => msg += s"[DEBUG]: failing at `$chisel` (expected: `$exp`)"
+        case _ => 
+      }
+    })
+    msg.mkString("\n")
+  }
 
   class VerilogStrictStringsMatcher(expectedLines: Seq[String]) extends Matcher[String] {
     override def apply(verilog: String): MatchResult = {
+      val data = verilog.split("\n").toSeq
       MatchResult(
-          verilog.split("\n").containsSlice(expectedLines),
-          verilog + "\n did not contain \"" + expectedLines + "\"",
+          data.containsSlice(expectedLines),
+          verilog + "\n did not contain \"" + expectedLines + "\"\n" +"\nDetails:\n" + findFaillingLine(data, expectedLines),
           s"Emitted verilog contained $expectedLines"
       )
     }
   }
   class VerilogFlexStringsMatcher(expectedLines: Seq[String]) extends Matcher[String] {
     override def apply(verilog: String): MatchResult = {
+      val data = stripComments(verilog).split("\n").map(_.trim).toSeq
       MatchResult(
-          stripComments(verilog).split("\n").map(_.trim).containsSlice(expectedLines),
-          verilog + "\n did not contain \"" + expectedLines + "\"",
+          data.containsSlice(expectedLines),
+          verilog + "\n did not contain \"" + expectedLines + "\"\n" +"\nDetails:\n" + findFaillingLine(data, expectedLines),
           s"Emitted verilog contained $expectedLines"
       )
     }

helpers/src/test/scala/vecconvertSpec.scala

@@ -28,25 +28,25 @@ class vecconvertSpec extends AnyFlatSpec with VerilogMatchers {
       outC := "test".V.asUInt
     }
     val verilog = (new ChiselStage()).emitVerilog(new VecInitTest(), setTestRunDir)
-    verilog should contain ("assign outA_0 = 8'h74;")
-    verilog should contain ("assign outA_1 = 8'h65;")
-    verilog should contain ("assign outA_2 = 8'h73;")
-    verilog should contain ("assign outA_3 = 8'h74;")
-    verilog should contain ("assign outA_4 = 8'h74;")
-    verilog should contain ("assign outA_5 = 8'h65;")
-    verilog should contain ("assign outA_6 = 8'h73;")
-    verilog should contain ("assign outA_7 = 8'h74;")
+    verilog should containStr ("assign outA_0 = 8'h74;")
+    verilog should containStr ("assign outA_1 = 8'h65;")
+    verilog should containStr ("assign outA_2 = 8'h73;")
+    verilog should containStr ("assign outA_3 = 8'h74;")
+    verilog should containStr ("assign outA_4 = 8'h74;")
+    verilog should containStr ("assign outA_5 = 8'h65;")
+    verilog should containStr ("assign outA_6 = 8'h73;")
+    verilog should containStr ("assign outA_7 = 8'h74;")
 
-    verilog should contain ("assign outB_0 = 8'h0;")
-    verilog should contain ("assign outB_1 = 8'h0;")
-    verilog should contain ("assign outB_2 = 8'h0;")
-    verilog should contain ("assign outB_3 = 8'h0;")
-    verilog should contain ("assign outB_4 = 8'h74;")
-    verilog should contain ("assign outB_5 = 8'h65;")
-    verilog should contain ("assign outB_6 = 8'h73;")
-    verilog should contain ("assign outB_7 = 8'h74;")
+    verilog should containStr ("assign outB_0 = 8'h0;")
+    verilog should containStr ("assign outB_1 = 8'h0;")
+    verilog should containStr ("assign outB_2 = 8'h0;")
+    verilog should containStr ("assign outB_3 = 8'h0;")
+    verilog should containStr ("assign outB_4 = 8'h74;")
+    verilog should containStr ("assign outB_5 = 8'h65;")
+    verilog should containStr ("assign outB_6 = 8'h73;")
+    verilog should containStr ("assign outB_7 = 8'h74;")
 
-    verilog should contain ("assign outC = 64'h74736574;") // NB: reversed as expected
+    verilog should containStr ("assign outC = 64'h74736574;") // NB: reversed as expected
   }
 
   "Implicit subwords" should "enable direct subrange assignments" in {
@@ -59,11 +59,11 @@ class vecconvertSpec extends AnyFlatSpec with VerilogMatchers {
       outB(4, 3) := Seq(false.B, false.B)
     }
     val verilog = (new ChiselStage()).emitVerilog(new TestVecSubWords(), setTestRunDir)
-    verilog should contain ("assign outB_0 = 1'h0;")
-    verilog should contain ("assign outB_1 = 1'h1;")
-    verilog should contain ("assign outB_2 = 1'h1;")
-    verilog should contain ("assign outB_3 = 1'h0;")
-    verilog should contain ("assign outB_4 = 1'h0;")
+    verilog should containStr ("assign outB_0 = 1'h0;")
+    verilog should containStr ("assign outB_1 = 1'h1;")
+    verilog should containStr ("assign outB_2 = 1'h1;")
+    verilog should containStr ("assign outB_3 = 1'h0;")
+    verilog should containStr ("assign outB_4 = 1'h0;")
   }
   it should "enable direct subrange slicing and use in arithmetic expression" in {
     class TestVecSubWords() extends RawModule {
@@ -87,10 +87,10 @@ class vecconvertSpec extends AnyFlatSpec with VerilogMatchers {
 
     }
     val verilog = (new ChiselStage()).emitVerilog(new TestVecSubWords(), setTestRunDir)
-    verilog should contain ("assign outA = {in_2,in_1};")
-    verilog should contain ("assign checkA = 1'h1;")
-    verilog should contain ("assign checkB = 1'h1;")
-    verilog should contain ("assign checkC = 1'h1;")
+    verilog should containStr ("assign outA = {in_2,in_1};")
+    verilog should containStr ("assign checkA = 1'h1;")
+    verilog should containStr ("assign checkB = 1'h1;")
+    verilog should containStr ("assign checkC = 1'h1;")
     // NB : outB cannot be checked without involving intermediate wires whose names could change
   }
 
@@ -103,7 +103,7 @@ class vecconvertSpec extends AnyFlatSpec with VerilogMatchers {
       outB := Ones
     }
     val verilog = (new ChiselStage()).emitVerilog(new TestBitPattern(), setTestRunDir)
-    verilog should contain ("assign outA = 8'h0;")
-    verilog should contain ("assign outB = 8'hff;")
+    verilog should containStr ("assign outA = 8'h0;")
+    verilog should containStr ("assign outB = 8'hff;")
   }
 }

version.sbt

@@ -1 +1 @@
-ThisBuild / version := "0.5.0-SNAPSHOT"
+ThisBuild / version := "0.5.0-RC2"